bnx2x: Fix BCM578xx-B0 MDIO access
Fix MDIO access to Warpcore on new chip version of 578xx. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2953,7 +2953,9 @@ static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
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u32 val;
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u16 i;
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int rc = 0;
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if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
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bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
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EMAC_MDIO_STATUS_10MB);
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/* address */
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val = ((phy->addr << 21) | (devad << 16) | reg |
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EMAC_MDIO_COMM_COMMAND_ADDRESS |
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@ -3007,6 +3009,9 @@ static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
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}
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}
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if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
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bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
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EMAC_MDIO_STATUS_10MB);
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return rc;
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}
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@ -3016,6 +3021,9 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
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u32 tmp;
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u8 i;
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int rc = 0;
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if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
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bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
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EMAC_MDIO_STATUS_10MB);
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/* address */
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@ -3069,7 +3077,9 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
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bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
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}
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}
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if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
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bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
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EMAC_MDIO_STATUS_10MB);
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return rc;
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}
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@ -11118,6 +11128,8 @@ static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
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*/
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if (CHIP_REV(bp) == CHIP_REV_Ax)
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phy->flags |= FLAGS_MDC_MDIO_WA;
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else
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phy->flags |= FLAGS_MDC_MDIO_WA_B0;
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} else {
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switch (switch_cfg) {
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case SWITCH_CFG_1G:
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@ -145,6 +145,7 @@ struct bnx2x_phy {
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#define FLAGS_SFP_NOT_APPROVED (1<<7)
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#define FLAGS_MDC_MDIO_WA (1<<8)
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#define FLAGS_DUMMY_READ (1<<9)
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#define FLAGS_MDC_MDIO_WA_B0 (1<<10)
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#define FLAGS_TX_ERROR_CHECK (1<<12)
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/* preemphasis values for the rx side */
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@ -5624,8 +5624,9 @@
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#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
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#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
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#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
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#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
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#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
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#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
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#define EMAC_MDIO_STATUS_10MB (1L<<1)
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#define EMAC_MODE_25G_MODE (1L<<5)
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#define EMAC_MODE_HALF_DUPLEX (1L<<1)
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#define EMAC_MODE_PORT_GMII (2L<<2)
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@ -5636,6 +5637,7 @@
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#define EMAC_REG_EMAC_MAC_MATCH 0x10
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#define EMAC_REG_EMAC_MDIO_COMM 0xac
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#define EMAC_REG_EMAC_MDIO_MODE 0xb4
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#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
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#define EMAC_REG_EMAC_MODE 0x0
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#define EMAC_REG_EMAC_RX_MODE 0xc8
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#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
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