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amd/powerplay: Add structures required to report configuration change 

Add required structures for amd_powerplay_display_configuration_change

Signed-off-by: Eric Yang <eric.yang2@amd.com>
This commit is contained in:
Eric Yang 2015-12-01 13:23:07 -05:00 committed by Alex Deucher
parent 1c9a90820b
commit 14f634110f
5 changed files with 138 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
View File

@ -239,10 +239,10 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicUVDState);
cz_hwmgr->display_cfg.cpu_cc6_disable = false;
cz_hwmgr->display_cfg.cpu_pstate_disable = false;
cz_hwmgr->display_cfg.nb_pstate_switch_disable = false;
cz_hwmgr->display_cfg.cpu_pstate_separation_time = 0;
cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DisableVoltageIsland);
@ -784,8 +784,11 @@ static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
void *storage, int result)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) {
/* TO DO get from dal PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks); */
PHM_PlatformCaps_SclkDeepSleep)) {
uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
if (clks == 0)
clks = CZ_MIN_DEEP_SLEEP_SCLK;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_SetMinDeepSleepSclk,
CZ_MIN_DEEP_SLEEP_SCLK);
@ -873,8 +876,8 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
if (hw_data->sys_info.nb_dpm_enable) {
disable_switch = hw_data->display_cfg.nb_pstate_switch_disable ? true : false;
enable_low_mem_state = hw_data->display_cfg.nb_pstate_switch_disable ? false : true;
disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
if (pnew_state->action == FORCE_HIGH)
cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
@ -1530,18 +1533,18 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
}
static void cz_hw_print_display_cfg(
const struct amd_pp_display_configuration *display_cfg)
const struct cc6_settings *cc6_settings)
{
PP_DBG_LOG("New Display Configuration:\n");
PP_DBG_LOG(" cpu_cc6_disable: %d\n",
display_cfg->cpu_cc6_disable);
cc6_settings->cpu_cc6_disable);
PP_DBG_LOG(" cpu_pstate_disable: %d\n",
display_cfg->cpu_pstate_disable);
cc6_settings->cpu_pstate_disable);
PP_DBG_LOG(" nb_pstate_switch_disable: %d\n",
display_cfg->nb_pstate_switch_disable);
cc6_settings->nb_pstate_switch_disable);
PP_DBG_LOG(" cpu_pstate_separation_time: %d\n\n",
display_cfg->cpu_pstate_separation_time);
cc6_settings->cpu_pstate_separation_time);
}
static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
@ -1549,18 +1552,20 @@ static void cz_hw_print_display_cfg(
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
uint32_t data = 0;
if (hw_data->cc6_setting_changed == true) {
if (hw_data->cc6_settings.cc6_setting_changed == true) {
cz_hw_print_display_cfg(&hw_data->display_cfg);
hw_data->cc6_settings.cc6_setting_changed = false;
data |= (hw_data->display_cfg.cpu_pstate_separation_time
cz_hw_print_display_cfg(&hw_data->cc6_settings);
data |= (hw_data->cc6_settings.cpu_pstate_separation_time
& PWRMGT_SEPARATION_TIME_MASK)
<< PWRMGT_SEPARATION_TIME_SHIFT;
data|= (hw_data->display_cfg.cpu_cc6_disable ? 0x1 : 0x0)
data|= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
<< PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
data|= (hw_data->display_cfg.cpu_pstate_disable ? 0x1 : 0x0)
data|= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
<< PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
@ -1569,30 +1574,39 @@ static void cz_hw_print_display_cfg(
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_SetDisplaySizePowerParams,
data);
hw_data->cc6_setting_changed = false;
}
return 0;
}
static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
{
{
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
if (separation_time != hw_data->display_cfg.cpu_pstate_separation_time
|| cc6_disable != hw_data->display_cfg.cpu_cc6_disable
|| pstate_disable != hw_data->display_cfg.cpu_pstate_disable
|| pstate_switch_disable != hw_data->display_cfg.nb_pstate_switch_disable) {
if (separation_time !=
hw_data->cc6_settings.cpu_pstate_separation_time
|| cc6_disable !=
hw_data->cc6_settings.cpu_cc6_disable
|| pstate_disable !=
hw_data->cc6_settings.cpu_pstate_disable
|| pstate_switch_disable !=
hw_data->cc6_settings.nb_pstate_switch_disable) {
hw_data->display_cfg.cpu_pstate_separation_time = separation_time;
hw_data->display_cfg.cpu_cc6_disable = cc6_disable;
hw_data->display_cfg.cpu_pstate_disable = pstate_disable;
hw_data->display_cfg.nb_pstate_switch_disable = pstate_switch_disable;
hw_data->cc6_setting_changed = true;
hw_data->cc6_settings.cc6_setting_changed = true;
hw_data->cc6_settings.cpu_pstate_separation_time =
separation_time;
hw_data->cc6_settings.cpu_cc6_disable =
cc6_disable;
hw_data->cc6_settings.cpu_pstate_disable =
pstate_disable;
hw_data->cc6_settings.nb_pstate_switch_disable =
pstate_switch_disable;
}
return 0;
}

11
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
View File

@ -176,6 +176,14 @@ struct cz_power_state {
#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000 /* bit 23 */
#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000 /* bit 24 */
struct cc6_settings {
bool cc6_setting_changed;
bool nb_pstate_switch_disable;/* controls NB PState switch */
bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
bool cpu_pstate_disable;
uint32_t cpu_pstate_separation_time;
};
struct cz_hwmgr {
uint32_t activity_target[CZ_MAX_HARDWARE_POWERLEVELS];
uint32_t dpm_interval;
@ -238,7 +246,7 @@ struct cz_hwmgr {
uint32_t highest_valid;
uint32_t high_voltage_threshold;
uint32_t is_nb_dpm_enabled;
struct amd_pp_display_configuration display_cfg; /* set by DAL */
struct cc6_settings cc6_settings;
uint32_t is_voltage_island_enabled;
bool pgacpinit;
@ -304,7 +312,6 @@ struct cz_hwmgr {
uint32_t max_sclk_level;
uint32_t num_of_clk_entries;
bool cc6_setting_changed;
};
struct pp_hwmgr;

17
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
View File

@ -249,16 +249,21 @@ int phm_check_states_equal(struct pp_hwmgr *hwmgr,
int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
const struct amd_pp_display_configuration *display_config)
{
if (hwmgr == NULL || hwmgr->hwmgr_func->store_cc6_data == NULL)
if (hwmgr == NULL)
return -EINVAL;
hwmgr->display_config = *display_config;
/* to do pass other display configuration in furture */
return hwmgr->hwmgr_func->store_cc6_data(hwmgr,
display_config->cpu_pstate_separation_time,
display_config->cpu_cc6_disable,
display_config->cpu_pstate_disable,
display_config->nb_pstate_switch_disable);
if (hwmgr->hwmgr_func->store_cc6_data)
hwmgr->hwmgr_func->store_cc6_data(hwmgr,
display_config->cpu_pstate_separation_time,
display_config->cpu_cc6_disable,
display_config->cpu_pstate_disable,
display_config->nb_pstate_switch_disable);
return 0;
}
int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,

73
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
View File

@ -130,12 +130,85 @@ struct amd_pp_init {
uint32_t chip_id;
uint32_t rev_id;
};
enum amd_pp_display_config_type{
AMD_PP_DisplayConfigType_None = 0,
AMD_PP_DisplayConfigType_DP54 ,
AMD_PP_DisplayConfigType_DP432 ,
AMD_PP_DisplayConfigType_DP324 ,
AMD_PP_DisplayConfigType_DP27,
AMD_PP_DisplayConfigType_DP243,
AMD_PP_DisplayConfigType_DP216,
AMD_PP_DisplayConfigType_DP162,
AMD_PP_DisplayConfigType_HDMI6G ,
AMD_PP_DisplayConfigType_HDMI297 ,
AMD_PP_DisplayConfigType_HDMI162,
AMD_PP_DisplayConfigType_LVDS,
AMD_PP_DisplayConfigType_DVI,
AMD_PP_DisplayConfigType_WIRELESS,
AMD_PP_DisplayConfigType_VGA
};
struct single_display_configuration
{
uint32_t controller_index;
uint32_t controller_id;
uint32_t signal_type;
uint32_t display_state;
/* phy id for the primary internal transmitter */
uint8_t primary_transmitter_phyi_d;
/* bitmap with the active lanes */
uint8_t primary_transmitter_active_lanemap;
/* phy id for the secondary internal transmitter (for dual-link dvi) */
uint8_t secondary_transmitter_phy_id;
/* bitmap with the active lanes */
uint8_t secondary_transmitter_active_lanemap;
/* misc phy settings for SMU. */
uint32_t config_flags;
uint32_t display_type;
uint32_t view_resolution_cx;
uint32_t view_resolution_cy;
enum amd_pp_display_config_type displayconfigtype;
uint32_t vertical_refresh; /* for active display */
};
#define MAX_NUM_DISPLAY 32
struct amd_pp_display_configuration {
bool nb_pstate_switch_disable;/* controls NB PState switch */
bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
bool cpu_pstate_disable;
uint32_t cpu_pstate_separation_time;
uint32_t num_display; /* total number of display*/
uint32_t num_path_including_non_display;
uint32_t crossfire_display_index;
uint32_t min_mem_set_clock;
uint32_t min_core_set_clock;
/* unit 10KHz x bit*/
uint32_t min_bus_bandwidth;
/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
uint32_t min_core_set_clock_in_sr;
struct single_display_configuration displays[MAX_NUM_DISPLAY];
uint32_t vrefresh; /* for active display*/
uint32_t min_vblank_time; /* for active display*/
bool multi_monitor_in_sync;
/* Controller Index of primary display - used in MCLK SMC switching hang
* SW Workaround*/
uint32_t crtc_index;
/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
uint32_t line_time_in_us;
bool invalid_vblank_time;
uint32_t display_clk;
/*
* for given display configuration if multimonitormnsync == false then
* Memory clock DPMS with this latency or below is allowed, DPMS with
* higher latency not allowed.
*/
uint32_t dce_tolerable_mclk_in_active_latency;
};
struct amd_pp_dal_clock_info {

1
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
View File

@ -601,6 +601,7 @@ struct pp_hwmgr {
struct pp_power_state *request_ps;
struct pp_power_state *boot_ps;
struct pp_power_state *uvd_ps;
struct amd_pp_display_configuration display_config;
};