sh-pfc: r8a7790: Remove deprecated RDS pins
The pins have been removed from the datasheet, remove them here as well. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Shinya Kuribayashi
Laurent Pinchart
parent
9f2edd4113
commit
14da999bd6
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@ -283,7 +283,7 @@ enum {
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/* IPSR7 */
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FN_ETH_MDIO, FN_HRTS0_N_E,
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FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
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FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
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FN_HTX0_F, FN_BPFCLK_G,
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FN_ETH_TX_EN, FN_SIM0_CLK_C,
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FN_HRTS0_N_F, FN_ETH_MAGIC,
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FN_SIM0_RST_C, FN_ETH_TXD0,
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@ -353,10 +353,10 @@ enum {
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FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
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FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
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FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
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FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
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FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
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FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
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FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
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FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
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FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
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FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
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FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
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FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
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@ -377,12 +377,12 @@ enum {
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FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
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FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
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FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
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FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
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FN_RDS_DATA_E, FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
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FN_FMIN_E, FN_FMIN_F,
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FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
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FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
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FN_I2C2_SDA_B, FN_MLB_DAT, FN_SPV_EVEN,
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FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
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FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
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FN_SSI_SCK0129, FN_CAN_CLK_B,
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FN_MOUT0,
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/* IPSR12 */
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@ -409,12 +409,12 @@ enum {
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/* IPSR13 */
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FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
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FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
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FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
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FN_SCIFB1_CTS_N, FN_BPFCLK_D,
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FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
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FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6,
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FN_BPFCLK_F, FN_SSI_WS6,
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FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
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FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
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FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
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FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
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FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
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FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
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FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
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@ -422,8 +422,8 @@ enum {
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FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
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FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
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FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
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FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B,
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FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8,
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FN_BPFCLK_E, FN_SSI_SDATA7_B,
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FN_FMIN_G, FN_SSI_SDATA8,
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FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
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FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
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FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
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@ -514,8 +514,6 @@ enum {
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FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
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FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
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FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
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FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
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FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
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FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
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FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
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@ -656,7 +654,7 @@ enum {
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ETH_MDIO_MARK, HRTS0_N_E_MARK,
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SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
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HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
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HTX0_F_MARK, BPFCLK_G_MARK,
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ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
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HRTS0_N_F_MARK, ETH_MAGIC_MARK,
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SIM0_RST_C_MARK, ETH_TXD0_MARK,
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@ -723,10 +721,10 @@ enum {
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SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
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VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
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TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
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SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
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SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
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VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
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TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
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SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
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SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
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VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
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GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
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MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
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@ -746,12 +744,12 @@ enum {
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SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
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VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
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MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
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RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
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RDS_DATA_E_MARK, MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
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FMIN_E_MARK, FMIN_F_MARK,
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MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
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MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
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I2C2_SDA_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
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SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
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RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
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SSI_SCK0129_MARK, CAN_CLK_B_MARK,
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MOUT0_MARK,
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SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
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@ -776,12 +774,12 @@ enum {
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SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
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LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
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SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
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SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
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DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
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BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
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BPFCLK_F_MARK, SSI_WS6_MARK,
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SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
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LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
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FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
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FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
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CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
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SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
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CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
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@ -789,8 +787,8 @@ enum {
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LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
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STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
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TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
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BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
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FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
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BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
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FMIN_G_MARK, SSI_SDATA8_MARK,
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STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
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CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
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STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
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@ -1240,7 +1238,6 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
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PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
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PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
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PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
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PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
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PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
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PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
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@ -1421,7 +1418,6 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
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PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
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PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
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PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
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PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
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PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
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PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
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@ -1431,7 +1427,6 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
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PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
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PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
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PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
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PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
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PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
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PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
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@ -1494,11 +1489,8 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
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PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
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PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
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PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
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PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
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PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
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PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
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PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
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PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
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PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
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PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
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@ -1512,7 +1504,6 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
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PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
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PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
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PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
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PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
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PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
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PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
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@ -1583,12 +1574,10 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
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PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
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PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
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PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2),
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PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
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PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
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PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
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PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
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PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4),
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PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
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PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
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PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
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@ -1597,7 +1586,6 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
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PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
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PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
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PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2),
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PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
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PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
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PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
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@ -1623,10 +1611,8 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
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PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
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PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
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PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3),
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PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
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PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
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PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5),
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PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
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PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
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PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
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@ -3490,8 +3476,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
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/* IP7_7_6 [2] */
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FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
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/* IP7_5_3 [3] */
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FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
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0, 0, 0,
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FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
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/* IP7_2_0 [3] */
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FN_ETH_MDIO, 0, FN_HRTS0_N_E,
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FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
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@ -3584,11 +3569,11 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
|
||||
FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
|
||||
/* IP10_22_19 [4] */
|
||||
FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
|
||||
FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
|
||||
FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
|
||||
FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP10_18_15 [4] */
|
||||
FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
|
||||
FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
|
||||
FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
|
||||
FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
|
||||
0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -3617,7 +3602,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
|
||||
/* IP11_29_27 [3] */
|
||||
FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
|
||||
FN_RDS_CLK_B, 0, 0,
|
||||
0, 0, 0,
|
||||
/* IP11_26_24 [3] */
|
||||
FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
|
||||
0, 0, 0,
|
||||
|
|
@ -3625,8 +3610,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
|
||||
/* IP11_21_18 [4] */
|
||||
FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
|
||||
FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
|
||||
FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
|
||||
0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP11_17_15 [3] */
|
||||
FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
|
||||
FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
|
||||
|
|
@ -3701,8 +3685,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* IP13_22_19 [4] */
|
||||
FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
|
||||
FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
|
||||
FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F,
|
||||
0, 0, 0, 0,
|
||||
0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
|
||||
/* IP13_18_16 [3] */
|
||||
FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
|
||||
FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
|
||||
|
|
@ -3710,15 +3693,15 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
|
||||
FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
|
||||
/* IP13_12_10 [3] */
|
||||
FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
|
||||
FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
|
||||
FN_CAN_DEBUGOUT8, 0, 0,
|
||||
/* IP13_9_7 [3] */
|
||||
FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
|
||||
FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
|
||||
/* IP13_6_3 [4] */
|
||||
FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
|
||||
FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
|
||||
FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
|
||||
FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0,
|
||||
FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_2_0 [3] */
|
||||
FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
|
||||
FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
|
||||
|
|
@ -3912,9 +3895,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
|
||||
/* SEL_GPS [2] */
|
||||
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
|
||||
/* SEL_RDS [3] */
|
||||
FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
|
||||
FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
|
||||
/* RESERVED [3] */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* SEL_SIM [2] */
|
||||
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
|
||||
/* SEL_SSI8 [2] */
|
||||
|
|
|
|||
Loading…
Reference in New Issue