mtd: nand: remove AG-AND support
We have only one AG-AND driver and it was not touched since 2005. It looks like AG-AND was not really make it to mass-production and can be considered a dead technology. Along with the AG-AND support, this patch removes the BBT_AUTO_REFRESH feature, because the only user of this feature is AG-AND. And even though it is implemented as a generic feature, I prefer to remove it because NAND flashes do not really need it in this form. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -4,7 +4,6 @@
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* Overview:
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* This is the generic MTD driver for NAND flash devices. It should be
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* capable of working with almost all NAND chips currently available.
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* Basic support for AG-AND chips is provided.
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*
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* Additional technical information is available on
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* http://www.linux-mtd.infradead.org/doc/nand.html
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@ -22,8 +21,6 @@
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* Enable cached programming for 2k page size chips
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* Check, if mtd->ecctype should be set to MTD_ECC_HW
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* if we have HW ECC support.
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* The AG-AND chips have nice features for speed improvement,
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* which are not supported yet. Read / program 4 pages in one go.
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* BBT table is not serialized, has to be fixed
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*
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* This program is free software; you can redistribute it and/or modify
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@ -836,10 +833,7 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
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*/
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ndelay(100);
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if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
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chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
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else
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chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
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chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
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if (in_interrupt() || oops_in_progress)
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panic_nand_wait(mtd, chip, timeo);
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@ -2480,24 +2474,6 @@ static void single_erase_cmd(struct mtd_info *mtd, int page)
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chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
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}
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/**
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* multi_erase_cmd - [GENERIC] AND specific block erase command function
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* @mtd: MTD device structure
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* @page: the page address of the block which will be erased
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*
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* AND multi block erase command function. Erase 4 consecutive blocks.
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*/
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static void multi_erase_cmd(struct mtd_info *mtd, int page)
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{
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struct nand_chip *chip = mtd->priv;
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/* Send commands to erase a block */
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chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
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chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
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chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
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chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
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chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
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}
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/**
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* nand_erase - [MTD Interface] erase block(s)
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* @mtd: MTD device structure
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@ -2510,7 +2486,6 @@ static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
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return nand_erase_nand(mtd, instr, 0);
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}
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#define BBT_PAGE_MASK 0xffffff3f
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/**
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* nand_erase_nand - [INTERN] erase block(s)
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* @mtd: MTD device structure
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@ -2524,8 +2499,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
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{
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int page, status, pages_per_block, ret, chipnr;
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struct nand_chip *chip = mtd->priv;
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loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
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unsigned int bbt_masked_page = 0xffffffff;
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loff_t len;
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pr_debug("%s: start = 0x%012llx, len = %llu\n",
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@ -2556,15 +2529,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
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goto erase_exit;
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}
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/*
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* If BBT requires refresh, set the BBT page mask to see if the BBT
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* should be rewritten. Otherwise the mask is set to 0xffffffff which
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* can not be matched. This is also done when the bbt is actually
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* erased to avoid recursive updates.
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*/
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if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
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bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
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/* Loop through the pages */
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len = instr->len;
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@ -2610,15 +2574,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
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goto erase_exit;
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}
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/*
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* If BBT requires refresh, set the BBT rewrite flag to the
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* page being erased.
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*/
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if (bbt_masked_page != 0xffffffff &&
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(page & BBT_PAGE_MASK) == bbt_masked_page)
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rewrite_bbt[chipnr] =
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((loff_t)page << chip->page_shift);
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/* Increment page address and decrement length */
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len -= (1 << chip->phys_erase_shift);
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page += pages_per_block;
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@ -2628,15 +2583,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
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chipnr++;
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chip->select_chip(mtd, -1);
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chip->select_chip(mtd, chipnr);
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/*
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* If BBT requires refresh and BBT-PERCHIP, set the BBT
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* page mask to see if this BBT should be rewritten.
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*/
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if (bbt_masked_page != 0xffffffff &&
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(chip->bbt_td->options & NAND_BBT_PERCHIP))
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bbt_masked_page = chip->bbt_td->pages[chipnr] &
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BBT_PAGE_MASK;
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}
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}
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instr->state = MTD_ERASE_DONE;
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@ -2653,23 +2599,6 @@ erase_exit:
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if (!ret)
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mtd_erase_callback(instr);
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/*
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* If BBT requires refresh and erase was successful, rewrite any
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* selected bad block tables.
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*/
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if (bbt_masked_page == 0xffffffff || ret)
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return ret;
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for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
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if (!rewrite_bbt[chipnr])
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continue;
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/* Update the BBT for chip */
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pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
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__func__, chipnr, rewrite_bbt[chipnr],
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chip->bbt_td->pages[chipnr]);
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nand_update_bbt(mtd, rewrite_bbt[chipnr]);
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}
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/* Return more or less happy */
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return ret;
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}
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@ -3302,12 +3231,7 @@ ident_done:
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}
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chip->badblockbits = 8;
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/* Check for AND chips with 4 page planes */
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if (chip->options & NAND_4PAGE_ARRAY)
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chip->erase_cmd = multi_erase_cmd;
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else
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chip->erase_cmd = single_erase_cmd;
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chip->erase_cmd = single_erase_cmd;
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/* Do not replace user supplied command function! */
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if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
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@ -1240,15 +1240,6 @@ int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
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*/
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static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
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static uint8_t scan_agand_pattern[] = { 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7 };
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static struct nand_bbt_descr agand_flashbased = {
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.options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
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.offs = 0x20,
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.len = 6,
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.pattern = scan_agand_pattern
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};
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/* Generic flash bbt descriptors */
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static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
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static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
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@ -1333,22 +1324,6 @@ int nand_default_bbt(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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/*
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* Default for AG-AND. We must use a flash based bad block table as the
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* devices have factory marked _good_ blocks. Erasing those blocks
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* leads to loss of the good / bad information, so we _must_ store this
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* information in a good / bad table during startup.
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*/
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if (this->options & NAND_IS_AND) {
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/* Use the default pattern descriptors */
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if (!this->bbt_td) {
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this->bbt_td = &bbt_main_descr;
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this->bbt_md = &bbt_mirror_descr;
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}
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this->bbt_options |= NAND_BBT_USE_FLASH;
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return nand_scan_bbt(mtd, &agand_flashbased);
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}
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/* Is a flash based bad block table requested? */
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if (this->bbt_options & NAND_BBT_USE_FLASH) {
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/* Use the default pattern descriptors */
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@ -134,19 +134,6 @@ struct nand_flash_dev nand_flash_ids[] = {
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{"NAND 64GiB 1,8V 16-bit", 0x2E, 0, 65536, 0, LP_OPTIONS16},
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{"NAND 64GiB 3,3V 16-bit", 0x4E, 0, 65536, 0, LP_OPTIONS16},
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/*
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* Renesas AND 1 Gigabit. Those chips do not support extended id and
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* have a strange page/block layout ! The chosen minimum erasesize is
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* 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page
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* planes 1 block = 2 pages, but due to plane arrangement the blocks
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* 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would
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* increase the eraseblock size so we chose a combined one which can be
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* erased in one go There are more speed improvements for reads and
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* writes possible, but not implemented now
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*/
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{"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000,
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NAND_IS_AND | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH},
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{NULL,}
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};
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@ -171,22 +171,6 @@ typedef enum {
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#define NAND_CACHEPRG 0x00000008
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/* Chip has copy back function */
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#define NAND_COPYBACK 0x00000010
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/*
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* AND Chip which has 4 banks and a confusing page / block
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* assignment. See Renesas datasheet for further information.
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*/
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#define NAND_IS_AND 0x00000020
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/*
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* Chip has a array of 4 pages which can be read without
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* additional ready /busy waits.
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*/
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#define NAND_4PAGE_ARRAY 0x00000040
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/*
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* Chip requires that BBT is periodically rewritten to prevent
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* bits from adjacent blocks from 'leaking' in altering data.
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* This happens with the Renesas AG-AND chips, possibly others.
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*/
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#define BBT_AUTO_REFRESH 0x00000080
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/*
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* Chip requires ready check on read (for auto-incremented sequential read).
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* True only for small page devices; large page devices do not support
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