[SPARC64]: Add SG merging support back into IOMMU code.
Mimicks almost perfectly the powerpc IOMMU code, except that it doesn't have the IOMMU_PAGE_SIZE != PAGE_SIZE handling, and it also lacks the device dma mask support bits. I'll add that later as time permits, but this gets us at least back to where we were beforehand. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
David S. Miller
parent
d284142cba
commit
13fa14e185
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@ -512,124 +512,209 @@ static void dma_4u_unmap_single(struct device *dev, dma_addr_t bus_addr,
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static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction)
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{
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unsigned long flags, ctx, i, npages, iopte_protection;
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struct scatterlist *sg;
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struct scatterlist *s, *outs, *segstart;
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unsigned long flags, handle, prot, ctx;
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dma_addr_t dma_next = 0, dma_addr;
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unsigned int max_seg_size;
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int outcount, incount, i;
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struct strbuf *strbuf;
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struct iommu *iommu;
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iopte_t *base;
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u32 dma_base;
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/* Fast path single entry scatterlists. */
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if (nelems == 1) {
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sglist->dma_address =
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dma_4u_map_single(dev, sg_virt(sglist),
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sglist->length, direction);
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if (unlikely(sglist->dma_address == DMA_ERROR_CODE))
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return 0;
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sglist->dma_length = sglist->length;
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return 1;
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}
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BUG_ON(direction == DMA_NONE);
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iommu = dev->archdata.iommu;
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strbuf = dev->archdata.stc;
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if (unlikely(direction == DMA_NONE))
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goto bad_no_ctx;
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npages = calc_npages(sglist, nelems);
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if (nelems == 0 || !iommu)
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return 0;
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spin_lock_irqsave(&iommu->lock, flags);
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base = alloc_npages(dev, iommu, npages);
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = iommu_alloc_ctx(iommu);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (base == NULL)
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goto bad;
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dma_base = iommu->page_table_map_base +
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((base - iommu->page_table) << IO_PAGE_SHIFT);
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if (strbuf->strbuf_enabled)
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iopte_protection = IOPTE_STREAMING(ctx);
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prot = IOPTE_STREAMING(ctx);
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else
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iopte_protection = IOPTE_CONSISTENT(ctx);
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prot = IOPTE_CONSISTENT(ctx);
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if (direction != DMA_TO_DEVICE)
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iopte_protection |= IOPTE_WRITE;
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prot |= IOPTE_WRITE;
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for_each_sg(sglist, sg, nelems, i) {
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unsigned long paddr = SG_ENT_PHYS_ADDRESS(sg);
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unsigned long slen = sg->length;
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unsigned long this_npages;
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outs = s = segstart = &sglist[0];
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outcount = 1;
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incount = nelems;
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handle = 0;
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this_npages = iommu_num_pages(paddr, slen);
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/* Init first segment length for backout at failure */
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outs->dma_length = 0;
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sg->dma_address = dma_base | (paddr & ~IO_PAGE_MASK);
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sg->dma_length = slen;
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max_seg_size = dma_get_max_seg_size(dev);
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for_each_sg(sglist, s, nelems, i) {
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unsigned long paddr, npages, entry, slen;
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iopte_t *base;
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slen = s->length;
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/* Sanity check */
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if (slen == 0) {
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dma_next = 0;
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continue;
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}
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/* Allocate iommu entries for that segment */
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paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
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npages = iommu_num_pages(paddr, slen);
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entry = iommu_range_alloc(dev, iommu, npages, &handle);
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/* Handle failure */
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if (unlikely(entry == DMA_ERROR_CODE)) {
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if (printk_ratelimit())
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printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
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" npages %lx\n", iommu, paddr, npages);
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goto iommu_map_failed;
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}
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base = iommu->page_table + entry;
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/* Convert entry to a dma_addr_t */
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dma_addr = iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT);
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dma_addr |= (s->offset & ~IO_PAGE_MASK);
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/* Insert into HW table */
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paddr &= IO_PAGE_MASK;
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while (this_npages--) {
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iopte_val(*base) = iopte_protection | paddr;
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while (npages--) {
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iopte_val(*base) = prot | paddr;
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base++;
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paddr += IO_PAGE_SIZE;
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dma_base += IO_PAGE_SIZE;
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}
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/* If we are in an open segment, try merging */
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if (segstart != s) {
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/* We cannot merge if:
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* - allocated dma_addr isn't contiguous to previous allocation
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*/
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if ((dma_addr != dma_next) ||
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(outs->dma_length + s->length > max_seg_size)) {
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/* Can't merge: create a new segment */
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segstart = s;
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outcount++;
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outs = sg_next(outs);
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} else {
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outs->dma_length += s->length;
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}
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}
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if (segstart == s) {
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/* This is a new segment, fill entries */
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outs->dma_address = dma_addr;
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outs->dma_length = slen;
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}
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/* Calculate next page pointer for contiguous check */
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dma_next = dma_addr + slen;
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}
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return nelems;
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (outcount < incount) {
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outs = sg_next(outs);
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outs->dma_address = DMA_ERROR_CODE;
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outs->dma_length = 0;
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}
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return outcount;
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iommu_map_failed:
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for_each_sg(sglist, s, nelems, i) {
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if (s->dma_length != 0) {
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unsigned long vaddr, npages, entry, i;
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iopte_t *base;
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vaddr = s->dma_address & IO_PAGE_MASK;
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npages = iommu_num_pages(s->dma_address, s->dma_length);
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iommu_range_free(iommu, vaddr, npages);
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entry = (vaddr - iommu->page_table_map_base)
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>> IO_PAGE_SHIFT;
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base = iommu->page_table + entry;
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for (i = 0; i < npages; i++)
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iopte_make_dummy(iommu, base + i);
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s->dma_address = DMA_ERROR_CODE;
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s->dma_length = 0;
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}
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if (s == outs)
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break;
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}
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spin_unlock_irqrestore(&iommu->lock, flags);
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bad:
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iommu_free_ctx(iommu, ctx);
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bad_no_ctx:
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if (printk_ratelimit())
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WARN_ON(1);
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return 0;
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}
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/* If contexts are being used, they are the same in all of the mappings
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* we make for a particular SG.
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*/
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static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg)
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{
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unsigned long ctx = 0;
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if (iommu->iommu_ctxflush) {
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iopte_t *base;
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u32 bus_addr;
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bus_addr = sg->dma_address & IO_PAGE_MASK;
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base = iommu->page_table +
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((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
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}
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return ctx;
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}
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static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction)
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{
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unsigned long flags, ctx, i, npages;
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unsigned long flags, ctx;
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struct scatterlist *sg;
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struct strbuf *strbuf;
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struct iommu *iommu;
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iopte_t *base;
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u32 bus_addr;
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if (unlikely(direction == DMA_NONE)) {
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if (printk_ratelimit())
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WARN_ON(1);
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}
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BUG_ON(direction == DMA_NONE);
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iommu = dev->archdata.iommu;
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strbuf = dev->archdata.stc;
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bus_addr = sglist->dma_address & IO_PAGE_MASK;
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npages = calc_npages(sglist, nelems);
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base = iommu->page_table +
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((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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ctx = fetch_sg_ctx(iommu, sglist);
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spin_lock_irqsave(&iommu->lock, flags);
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/* Record the context, if any. */
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
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sg = sglist;
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while (nelems--) {
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dma_addr_t dma_handle = sg->dma_address;
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unsigned int len = sg->dma_length;
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unsigned long npages, entry;
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iopte_t *base;
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int i;
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/* Step 1: Kick data out of streaming buffers if necessary. */
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if (strbuf->strbuf_enabled)
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strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
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if (!len)
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break;
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npages = iommu_num_pages(dma_handle, len);
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iommu_range_free(iommu, dma_handle, npages);
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/* Step 2: Clear out the TSB entries. */
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for (i = 0; i < npages; i++)
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iopte_make_dummy(iommu, base + i);
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entry = ((dma_handle - iommu->page_table_map_base)
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>> IO_PAGE_SHIFT);
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base = iommu->page_table + entry;
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iommu_range_free(iommu, bus_addr, npages);
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dma_handle &= IO_PAGE_MASK;
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if (strbuf->strbuf_enabled)
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strbuf_flush(strbuf, iommu, dma_handle, ctx,
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npages, direction);
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for (i = 0; i < npages; i++)
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iopte_make_dummy(iommu, base + i);
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sg = sg_next(sg);
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}
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iommu_free_ctx(iommu, ctx);
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@ -89,6 +89,17 @@ static long iommu_batch_flush(struct iommu_batch *p)
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return 0;
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}
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static inline void iommu_batch_new_entry(unsigned long entry)
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{
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struct iommu_batch *p = &__get_cpu_var(iommu_batch);
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if (p->entry + p->npages == entry)
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return;
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if (p->entry != ~0UL)
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iommu_batch_flush(p);
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p->entry = entry;
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}
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/* Interrupts must be disabled. */
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static inline long iommu_batch_add(u64 phys_page)
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{
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@ -320,88 +331,131 @@ static void dma_4v_unmap_single(struct device *dev, dma_addr_t bus_addr,
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static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction)
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{
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unsigned long flags, npages, i, prot;
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u32 dma_base, orig_dma_base;
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struct scatterlist *sg;
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struct scatterlist *s, *outs, *segstart;
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unsigned long flags, handle, prot;
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dma_addr_t dma_next = 0, dma_addr;
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unsigned int max_seg_size;
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int outcount, incount, i;
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struct iommu *iommu;
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long entry, err;
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long err;
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/* Fast path single entry scatterlists. */
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if (nelems == 1) {
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sglist->dma_address =
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dma_4v_map_single(dev, sg_virt(sglist),
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sglist->length, direction);
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if (unlikely(sglist->dma_address == DMA_ERROR_CODE))
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return 0;
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sglist->dma_length = sglist->length;
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return 1;
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}
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BUG_ON(direction == DMA_NONE);
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iommu = dev->archdata.iommu;
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if (nelems == 0 || !iommu)
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return 0;
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if (unlikely(direction == DMA_NONE))
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goto bad;
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npages = calc_npages(sglist, nelems);
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spin_lock_irqsave(&iommu->lock, flags);
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entry = iommu_range_alloc(dev, iommu, npages, NULL);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry == DMA_ERROR_CODE))
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goto bad;
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orig_dma_base = dma_base = iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT);
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prot = HV_PCI_MAP_ATTR_READ;
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if (direction != DMA_TO_DEVICE)
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prot |= HV_PCI_MAP_ATTR_WRITE;
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local_irq_save(flags);
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outs = s = segstart = &sglist[0];
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outcount = 1;
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incount = nelems;
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handle = 0;
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iommu_batch_start(dev, prot, entry);
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/* Init first segment length for backout at failure */
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outs->dma_length = 0;
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for_each_sg(sglist, sg, nelems, i) {
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unsigned long paddr = SG_ENT_PHYS_ADDRESS(sg);
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unsigned long slen = sg->length;
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unsigned long this_npages;
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spin_lock_irqsave(&iommu->lock, flags);
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this_npages = iommu_num_pages(paddr, slen);
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iommu_batch_start(dev, prot, ~0UL);
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sg->dma_address = dma_base | (paddr & ~IO_PAGE_MASK);
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sg->dma_length = slen;
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max_seg_size = dma_get_max_seg_size(dev);
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for_each_sg(sglist, s, nelems, i) {
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unsigned long paddr, npages, entry, slen;
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paddr &= IO_PAGE_MASK;
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while (this_npages--) {
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err = iommu_batch_add(paddr);
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if (unlikely(err < 0L)) {
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local_irq_restore(flags);
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goto iommu_map_failed;
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}
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paddr += IO_PAGE_SIZE;
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dma_base += IO_PAGE_SIZE;
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slen = s->length;
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/* Sanity check */
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if (slen == 0) {
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dma_next = 0;
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continue;
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}
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/* Allocate iommu entries for that segment */
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paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
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npages = iommu_num_pages(paddr, slen);
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entry = iommu_range_alloc(dev, iommu, npages, &handle);
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/* Handle failure */
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if (unlikely(entry == DMA_ERROR_CODE)) {
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if (printk_ratelimit())
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printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
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" npages %lx\n", iommu, paddr, npages);
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goto iommu_map_failed;
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}
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iommu_batch_new_entry(entry);
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/* Convert entry to a dma_addr_t */
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dma_addr = iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT);
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dma_addr |= (s->offset & ~IO_PAGE_MASK);
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/* Insert into HW table */
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paddr &= IO_PAGE_MASK;
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while (npages--) {
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err = iommu_batch_add(paddr);
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if (unlikely(err < 0L))
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goto iommu_map_failed;
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paddr += IO_PAGE_SIZE;
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}
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/* If we are in an open segment, try merging */
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if (segstart != s) {
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/* We cannot merge if:
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* - allocated dma_addr isn't contiguous to previous allocation
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*/
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if ((dma_addr != dma_next) ||
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(outs->dma_length + s->length > max_seg_size)) {
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/* Can't merge: create a new segment */
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segstart = s;
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outcount++;
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outs = sg_next(outs);
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} else {
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outs->dma_length += s->length;
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}
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}
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if (segstart == s) {
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/* This is a new segment, fill entries */
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outs->dma_address = dma_addr;
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outs->dma_length = slen;
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}
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/* Calculate next page pointer for contiguous check */
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dma_next = dma_addr + slen;
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}
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err = iommu_batch_end();
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local_irq_restore(flags);
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if (unlikely(err < 0L))
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goto iommu_map_failed;
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return nelems;
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spin_unlock_irqrestore(&iommu->lock, flags);
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bad:
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if (printk_ratelimit())
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WARN_ON(1);
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return 0;
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if (outcount < incount) {
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outs = sg_next(outs);
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outs->dma_address = DMA_ERROR_CODE;
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outs->dma_length = 0;
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}
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return outcount;
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iommu_map_failed:
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spin_lock_irqsave(&iommu->lock, flags);
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iommu_range_free(iommu, orig_dma_base, npages);
|
||||
for_each_sg(sglist, s, nelems, i) {
|
||||
if (s->dma_length != 0) {
|
||||
unsigned long vaddr, npages;
|
||||
|
||||
vaddr = s->dma_address & IO_PAGE_MASK;
|
||||
npages = iommu_num_pages(s->dma_address, s->dma_length);
|
||||
iommu_range_free(iommu, vaddr, npages);
|
||||
/* XXX demap? XXX */
|
||||
s->dma_address = DMA_ERROR_CODE;
|
||||
s->dma_length = 0;
|
||||
}
|
||||
if (s == outs)
|
||||
break;
|
||||
}
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
|
@ -410,39 +464,43 @@ iommu_map_failed:
|
|||
static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
||||
int nelems, enum dma_data_direction direction)
|
||||
{
|
||||
unsigned long flags, npages;
|
||||
struct pci_pbm_info *pbm;
|
||||
u32 devhandle, bus_addr;
|
||||
struct scatterlist *sg;
|
||||
struct iommu *iommu;
|
||||
long entry;
|
||||
unsigned long flags;
|
||||
u32 devhandle;
|
||||
|
||||
if (unlikely(direction == DMA_NONE)) {
|
||||
if (printk_ratelimit())
|
||||
WARN_ON(1);
|
||||
}
|
||||
BUG_ON(direction == DMA_NONE);
|
||||
|
||||
iommu = dev->archdata.iommu;
|
||||
pbm = dev->archdata.host_controller;
|
||||
devhandle = pbm->devhandle;
|
||||
|
||||
bus_addr = sglist->dma_address & IO_PAGE_MASK;
|
||||
|
||||
npages = calc_npages(sglist, nelems);
|
||||
|
||||
entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
||||
|
||||
spin_lock_irqsave(&iommu->lock, flags);
|
||||
|
||||
iommu_range_free(iommu, bus_addr, npages);
|
||||
sg = sglist;
|
||||
while (nelems--) {
|
||||
dma_addr_t dma_handle = sg->dma_address;
|
||||
unsigned int len = sg->dma_length;
|
||||
unsigned long npages, entry;
|
||||
|
||||
do {
|
||||
unsigned long num;
|
||||
if (!len)
|
||||
break;
|
||||
npages = iommu_num_pages(dma_handle, len);
|
||||
iommu_range_free(iommu, dma_handle, npages);
|
||||
|
||||
num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
|
||||
npages);
|
||||
entry += num;
|
||||
npages -= num;
|
||||
} while (npages != 0);
|
||||
entry = ((dma_handle - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
||||
while (npages) {
|
||||
unsigned long num;
|
||||
|
||||
num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
|
||||
npages);
|
||||
entry += num;
|
||||
npages -= num;
|
||||
}
|
||||
|
||||
sg = sg_next(sg);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
/* BIO layer definitions. */
|
||||
extern unsigned long kern_base, kern_size;
|
||||
#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
|
||||
#define BIO_VMERGE_BOUNDARY 0
|
||||
#define BIO_VMERGE_BOUNDARY 8192
|
||||
|
||||
static inline u8 _inb(unsigned long addr)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue