ARM: OMAP3: Remove legacy support for am35xx-emac
This is no longer needed now that 3517 is booting in device tree only mode. Signed-off-by: Tony Lindgren <tony@atomide.com>
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13eeb0f326
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@ -281,7 +281,4 @@ ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
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obj-y += hwspinlock.o
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endif
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emac-$(CONFIG_TI_DAVINCI_EMAC) := am35xx-emac.o
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obj-y += $(emac-m) $(emac-y)
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obj-y += common-board-devices.o twl-common.o dss-common.o
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@ -1,114 +0,0 @@
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/*
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* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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*
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* Based on mach-omap2/board-am3517evm.c
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* Copyright (C) 2009 Texas Instruments Incorporated
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* Author: Ranjith Lohithakshan <ranjithl@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
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* whether express or implied; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/err.h>
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#include <linux/davinci_emac.h>
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#include "omap_device.h"
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#include "am35xx.h"
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#include "control.h"
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#include "am35xx-emac.h"
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static void am35xx_enable_emac_int(void)
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{
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u32 v;
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v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
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AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
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omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
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omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
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}
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static void am35xx_disable_emac_int(void)
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{
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u32 v;
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v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
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omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
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omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
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}
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static struct emac_platform_data am35xx_emac_pdata = {
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.ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET,
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.ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET,
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.ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET,
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.ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE,
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.hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR,
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.version = EMAC_VERSION_2,
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.interrupt_enable = am35xx_enable_emac_int,
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.interrupt_disable = am35xx_disable_emac_int,
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};
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static struct mdio_platform_data am35xx_mdio_pdata;
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static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
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void *pdata, int pdata_len)
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{
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struct platform_device *pdev;
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pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len);
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if (IS_ERR(pdev)) {
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WARN(1, "Can't build omap_device for %s:%s.\n",
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oh->class->name, oh->name);
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return PTR_ERR(pdev);
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}
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return 0;
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}
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void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
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{
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struct omap_hwmod *oh;
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u32 v;
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int ret;
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oh = omap_hwmod_lookup("davinci_mdio");
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if (!oh) {
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pr_err("Could not find davinci_mdio hwmod\n");
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return;
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}
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am35xx_mdio_pdata.bus_freq = mdio_bus_freq;
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ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata,
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sizeof(am35xx_mdio_pdata));
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if (ret) {
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pr_err("Could not build davinci_mdio hwmod device\n");
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return;
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}
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oh = omap_hwmod_lookup("davinci_emac");
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if (!oh) {
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pr_err("Could not find davinci_emac hwmod\n");
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return;
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}
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am35xx_emac_pdata.rmii_en = rmii_en;
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ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata,
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sizeof(am35xx_emac_pdata));
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if (ret) {
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pr_err("Could not build davinci_emac hwmod device\n");
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return;
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}
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v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
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v &= ~AM35XX_CPGMACSS_SW_RST;
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omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
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omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
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}
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@ -1,15 +0,0 @@
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/*
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* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define AM35XX_DEFAULT_MDIO_FREQUENCY 1000000
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#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
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void am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en);
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#else
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static inline void am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) {}
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#endif
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@ -1,46 +0,0 @@
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/*:
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* Address mappings and base address for AM35XX specific interconnects
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* and peripherals.
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*
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* Copyright (C) 2009 Texas Instruments
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*
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* Author: Sriramakrishnan <srk@ti.com>
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_AM35XX_H
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#define __ASM_ARCH_AM35XX_H
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/*
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* Base addresses
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* Note: OMAP3430 IVA2 memory space is being used for AM35xx IPSS modules
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*/
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#define AM35XX_IPSS_EMAC_BASE 0x5C000000
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#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
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#define AM35XX_IPSS_HECC_BASE 0x5C050000
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#define AM35XX_IPSS_VPFE_BASE 0x5C060000
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/* HECC module specifc offset definitions */
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#define AM35XX_HECC_SCC_HECC_OFFSET (0x0)
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#define AM35XX_HECC_SCC_RAM_OFFSET (0x3000)
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#define AM35XX_HECC_RAM_OFFSET (0x3000)
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#define AM35XX_HECC_MBOX_OFFSET (0x2000)
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#define AM35XX_HECC_INT_LINE (0x0)
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#define AM35XX_HECC_VERSION (0x1)
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#define AM35XX_EMAC_CNTRL_OFFSET (0x10000)
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#define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0)
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#define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000)
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#define AM35XX_EMAC_MDIO_OFFSET (0x30000)
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#define AM35XX_IPSS_MDIO_BASE (AM35XX_IPSS_EMAC_BASE + \
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AM35XX_EMAC_MDIO_OFFSET)
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#define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000)
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#define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \
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AM3517_EMAC_CNTRL_RAM_OFFSET)
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#define AM35XX_EMAC_HW_RAM_ADDR (0x01E20000)
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#endif /* __ASM_ARCH_AM35XX_H */
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@ -29,8 +29,6 @@
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#include <linux/platform_data/mailbox-omap.h>
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#include <plat/dmtimer.h>
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#include "am35xx.h"
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#include "soc.h"
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#include "omap_hwmod.h"
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#include "omap_hwmod_common_data.h"
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@ -50,6 +48,8 @@
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* elsewhere.
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*/
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#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
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/*
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* IP blocks
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*/
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@ -3459,15 +3459,6 @@ static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
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{
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.pa_start = AM35XX_IPSS_MDIO_BASE,
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.pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
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.flags = ADDR_TYPE_RT,
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},
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{ }
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};
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/* l4_core -> davinci mdio */
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/*
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* XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
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@ -3478,25 +3469,15 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &am35xx_mdio_hwmod,
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.clk = "emac_fck",
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.addr = am35xx_mdio_addrs,
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
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{ .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
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{ .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
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{ .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
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{ .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
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{ .irq = -1 },
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};
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static struct omap_hwmod_class am35xx_emac_class = {
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.name = "davinci_emac",
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};
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static struct omap_hwmod am35xx_emac_hwmod = {
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.name = "davinci_emac",
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.mpu_irqs = am35xx_emac_mpu_irqs,
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.class = &am35xx_emac_class,
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/*
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* According to Mark Greer, the MPU will not return from WFI
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@ -3519,15 +3500,6 @@ static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
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{
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.pa_start = AM35XX_IPSS_EMAC_BASE,
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.pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
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.flags = ADDR_TYPE_RT,
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},
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{ }
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};
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/* l4_core -> davinci emac */
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/*
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* XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
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@ -3538,7 +3510,6 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &am35xx_emac_hwmod,
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.clk = "emac_ick",
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.addr = am35xx_emac_addrs,
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.user = OCP_USER_MPU,
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};
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@ -19,7 +19,6 @@
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#include <linux/platform_data/pinctrl-single.h>
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#include <linux/platform_data/iommu-omap.h>
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#include "am35xx.h"
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#include "common.h"
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#include "common-board-devices.h"
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#include "dss-common.h"
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