iommu/vt-d: Make use of iova deferred flushing
Remove the deferred flushing implementation in the Intel VT-d driver and use the one from the common iova code instead. Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Joerg Roedel
parent
c8acb28b33
commit
13cf017446
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@ -458,31 +458,6 @@ static LIST_HEAD(dmar_rmrr_units);
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#define for_each_rmrr_units(rmrr) \
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list_for_each_entry(rmrr, &dmar_rmrr_units, list)
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static void flush_unmaps_timeout(unsigned long data);
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struct deferred_flush_entry {
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unsigned long iova_pfn;
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unsigned long nrpages;
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struct dmar_domain *domain;
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struct page *freelist;
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};
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#define HIGH_WATER_MARK 250
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struct deferred_flush_table {
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int next;
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struct deferred_flush_entry entries[HIGH_WATER_MARK];
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};
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struct deferred_flush_data {
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spinlock_t lock;
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int timer_on;
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struct timer_list timer;
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long size;
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struct deferred_flush_table *tables;
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};
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static DEFINE_PER_CPU(struct deferred_flush_data, deferred_flush);
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/* bitmap for indexing intel_iommus */
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static int g_num_of_iommus;
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@ -1309,6 +1284,13 @@ static void dma_free_pagelist(struct page *freelist)
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}
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}
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static void iova_entry_free(unsigned long data)
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{
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struct page *freelist = (struct page *)data;
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dma_free_pagelist(freelist);
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}
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/* iommu handling */
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static int iommu_alloc_root_entry(struct intel_iommu *iommu)
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{
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@ -1622,6 +1604,25 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu,
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addr, mask);
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}
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static void iommu_flush_iova(struct iova_domain *iovad)
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{
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struct dmar_domain *domain;
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int idx;
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domain = container_of(iovad, struct dmar_domain, iovad);
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for_each_domain_iommu(idx, domain) {
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struct intel_iommu *iommu = g_iommus[idx];
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u16 did = domain->iommu_did[iommu->seq_id];
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iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
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if (!cap_caching_mode(iommu->cap))
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iommu_flush_dev_iotlb(get_iommu_domain(iommu, did),
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0, MAX_AGAW_PFN_WIDTH);
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}
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}
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static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
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{
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u32 pmen;
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@ -1932,9 +1933,16 @@ static int domain_init(struct dmar_domain *domain, struct intel_iommu *iommu,
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{
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int adjust_width, agaw;
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unsigned long sagaw;
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int err;
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init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
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DMA_32BIT_PFN);
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err = init_iova_flush_queue(&domain->iovad,
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iommu_flush_iova, iova_entry_free);
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if (err)
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return err;
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domain_reserve_special_ranges(domain);
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/* calculate AGAW */
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@ -1986,14 +1994,6 @@ static void domain_exit(struct dmar_domain *domain)
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if (!domain)
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return;
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/* Flush any lazy unmaps that may reference this domain */
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if (!intel_iommu_strict) {
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int cpu;
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for_each_possible_cpu(cpu)
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flush_unmaps_timeout(cpu);
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}
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/* Remove associated devices and clear attached or cached domains */
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rcu_read_lock();
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domain_remove_dev_info(domain);
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@ -3206,7 +3206,7 @@ static int __init init_dmars(void)
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bool copied_tables = false;
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struct device *dev;
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struct intel_iommu *iommu;
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int i, ret, cpu;
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int i, ret;
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/*
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* for each drhd
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@ -3239,22 +3239,6 @@ static int __init init_dmars(void)
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goto error;
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}
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for_each_possible_cpu(cpu) {
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struct deferred_flush_data *dfd = per_cpu_ptr(&deferred_flush,
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cpu);
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dfd->tables = kzalloc(g_num_of_iommus *
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sizeof(struct deferred_flush_table),
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GFP_KERNEL);
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if (!dfd->tables) {
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ret = -ENOMEM;
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goto free_g_iommus;
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}
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spin_lock_init(&dfd->lock);
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setup_timer(&dfd->timer, flush_unmaps_timeout, cpu);
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}
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for_each_active_iommu(iommu, drhd) {
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g_iommus[iommu->seq_id] = iommu;
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@ -3437,10 +3421,9 @@ free_iommu:
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disable_dmar_iommu(iommu);
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free_dmar_iommu(iommu);
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}
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free_g_iommus:
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for_each_possible_cpu(cpu)
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kfree(per_cpu_ptr(&deferred_flush, cpu)->tables);
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kfree(g_iommus);
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error:
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return ret;
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}
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@ -3645,110 +3628,6 @@ static dma_addr_t intel_map_page(struct device *dev, struct page *page,
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dir, *dev->dma_mask);
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}
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static void flush_unmaps(struct deferred_flush_data *flush_data)
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{
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int i, j;
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flush_data->timer_on = 0;
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/* just flush them all */
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for (i = 0; i < g_num_of_iommus; i++) {
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struct intel_iommu *iommu = g_iommus[i];
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struct deferred_flush_table *flush_table =
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&flush_data->tables[i];
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if (!iommu)
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continue;
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if (!flush_table->next)
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continue;
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/* In caching mode, global flushes turn emulation expensive */
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if (!cap_caching_mode(iommu->cap))
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iommu->flush.flush_iotlb(iommu, 0, 0, 0,
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DMA_TLB_GLOBAL_FLUSH);
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for (j = 0; j < flush_table->next; j++) {
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unsigned long mask;
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struct deferred_flush_entry *entry =
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&flush_table->entries[j];
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unsigned long iova_pfn = entry->iova_pfn;
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unsigned long nrpages = entry->nrpages;
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struct dmar_domain *domain = entry->domain;
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struct page *freelist = entry->freelist;
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/* On real hardware multiple invalidations are expensive */
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if (cap_caching_mode(iommu->cap))
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iommu_flush_iotlb_psi(iommu, domain,
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mm_to_dma_pfn(iova_pfn),
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nrpages, !freelist, 0);
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else {
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mask = ilog2(nrpages);
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iommu_flush_dev_iotlb(domain,
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(uint64_t)iova_pfn << PAGE_SHIFT, mask);
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}
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free_iova_fast(&domain->iovad, iova_pfn, nrpages);
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if (freelist)
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dma_free_pagelist(freelist);
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}
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flush_table->next = 0;
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}
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flush_data->size = 0;
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}
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static void flush_unmaps_timeout(unsigned long cpuid)
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{
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struct deferred_flush_data *flush_data = per_cpu_ptr(&deferred_flush, cpuid);
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unsigned long flags;
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spin_lock_irqsave(&flush_data->lock, flags);
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flush_unmaps(flush_data);
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spin_unlock_irqrestore(&flush_data->lock, flags);
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}
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static void add_unmap(struct dmar_domain *dom, unsigned long iova_pfn,
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unsigned long nrpages, struct page *freelist)
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{
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unsigned long flags;
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int entry_id, iommu_id;
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struct intel_iommu *iommu;
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struct deferred_flush_entry *entry;
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struct deferred_flush_data *flush_data;
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flush_data = raw_cpu_ptr(&deferred_flush);
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/* Flush all CPUs' entries to avoid deferring too much. If
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* this becomes a bottleneck, can just flush us, and rely on
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* flush timer for the rest.
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*/
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if (flush_data->size == HIGH_WATER_MARK) {
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int cpu;
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for_each_online_cpu(cpu)
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flush_unmaps_timeout(cpu);
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}
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spin_lock_irqsave(&flush_data->lock, flags);
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iommu = domain_get_iommu(dom);
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iommu_id = iommu->seq_id;
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entry_id = flush_data->tables[iommu_id].next;
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++(flush_data->tables[iommu_id].next);
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entry = &flush_data->tables[iommu_id].entries[entry_id];
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entry->domain = dom;
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entry->iova_pfn = iova_pfn;
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entry->nrpages = nrpages;
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entry->freelist = freelist;
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if (!flush_data->timer_on) {
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mod_timer(&flush_data->timer, jiffies + msecs_to_jiffies(10));
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flush_data->timer_on = 1;
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}
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flush_data->size++;
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spin_unlock_irqrestore(&flush_data->lock, flags);
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}
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static void intel_unmap(struct device *dev, dma_addr_t dev_addr, size_t size)
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{
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struct dmar_domain *domain;
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@ -3784,7 +3663,8 @@ static void intel_unmap(struct device *dev, dma_addr_t dev_addr, size_t size)
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free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(nrpages));
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dma_free_pagelist(freelist);
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} else {
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add_unmap(domain, iova_pfn, nrpages, freelist);
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queue_iova(&domain->iovad, iova_pfn, nrpages,
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(unsigned long)freelist);
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/*
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* queue up the release of the unmap to save the 1/6th of the
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* cpu used up by the iotlb flush operation...
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@ -4721,7 +4601,6 @@ static void free_all_cpu_cached_iovas(unsigned int cpu)
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static int intel_iommu_cpu_dead(unsigned int cpu)
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{
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free_all_cpu_cached_iovas(cpu);
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flush_unmaps_timeout(cpu);
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return 0;
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}
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