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microblaze: Change temp register for cmdline 

For copy was used r7 register when CONFIG_CMDLINE_BOOL option
is enabled. But r7 stores pointer to fdt that's why machine_early_init
not detect compiled-in DTB.

I also moved kernel PID setup to have TLB init in one block

Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek 2010-02-04 11:42:24 +01:00
parent d79f3b06a9
commit 137d0795a7
1 changed files with 7 additions and 6 deletions
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13
arch/microblaze/kernel/head.S
View File

@ -99,8 +99,8 @@ no_fdt_arg:
tophys(r4,r4) /* convert to phys address */ tophys(r4,r4) /* convert to phys address */
ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
_copy_command_line: _copy_command_line:
lbu r7, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */ lbu r2, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */
sb r7, r4, r6 /* addr[r4+r6]= r7*/ sb r2, r4, r6 /* addr[r4+r6]= r7*/
addik r6, r6, 1 /* increment counting */ addik r6, r6, 1 /* increment counting */
bgtid r3, _copy_command_line /* loop for all entries */ bgtid r3, _copy_command_line /* loop for all entries */
addik r3, r3, -1 /* descrement loop */ addik r3, r3, -1 /* descrement loop */
@ -136,6 +136,11 @@ _invalidate:
addik r3, r3, -1 addik r3, r3, -1
/* sync */ /* sync */
/* Setup the kernel PID */
mts rpid,r0 /* Load the kernel PID */
nop
bri 4
/* /*
* We should still be executing code at physical address area * We should still be executing code at physical address area
* RAM_BASEADDR at this point. However, kernel code is at * RAM_BASEADDR at this point. However, kernel code is at
@ -146,10 +151,6 @@ _invalidate:
addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */ addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
tophys(r4,r3) /* Load the kernel physical address */ tophys(r4,r3) /* Load the kernel physical address */
mts rpid,r0 /* Load the kernel PID */
nop
bri 4
/* /*
* Configure and load two entries into TLB slots 0 and 1. * Configure and load two entries into TLB slots 0 and 1.
* In case we are pinning TLBs, these are reserved in by the * In case we are pinning TLBs, these are reserved in by the