arm: omap: irq: reorganize code a little bit
no functional changes, just moving code around. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -57,10 +57,6 @@
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* for each bank.. when in doubt, consult the TRM.
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*/
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static struct irq_domain *domain;
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static void __iomem *omap_irq_base;
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static int omap_nr_irqs = 96;
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/* Structure to save interrupt controller context */
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struct omap_intc_regs {
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u32 sysconfig;
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@ -70,6 +66,11 @@ struct omap_intc_regs {
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u32 ilr[INTCPS_NR_ILR_REGS];
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u32 mir[INTCPS_NR_MIR_REGS];
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};
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static struct omap_intc_regs intc_context;
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static struct irq_domain *domain;
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static void __iomem *omap_irq_base;
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static int omap_nr_irqs = 96;
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/* INTC bank register get/set */
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static void intc_writel(u32 reg, u32 val)
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@ -82,6 +83,61 @@ static u32 intc_readl(u32 reg)
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return readl_relaxed(omap_irq_base + reg);
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}
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void omap_intc_save_context(void)
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{
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int i;
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intc_context.sysconfig =
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intc_readl(INTC_SYSCONFIG);
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intc_context.protection =
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intc_readl(INTC_PROTECTION);
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intc_context.idle =
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intc_readl(INTC_IDLE);
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intc_context.threshold =
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intc_readl(INTC_THRESHOLD);
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for (i = 0; i < omap_nr_irqs; i++)
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intc_context.ilr[i] =
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intc_readl((INTC_ILR0 + 0x4 * i));
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for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
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intc_context.mir[i] =
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intc_readl(INTC_MIR0 + (0x20 * i));
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}
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void omap_intc_restore_context(void)
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{
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int i;
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intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
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intc_writel(INTC_PROTECTION, intc_context.protection);
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intc_writel(INTC_IDLE, intc_context.idle);
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intc_writel(INTC_THRESHOLD, intc_context.threshold);
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for (i = 0; i < omap_nr_irqs; i++)
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intc_writel(INTC_ILR0 + 0x4 * i,
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intc_context.ilr[i]);
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for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
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intc_writel(INTC_MIR0 + 0x20 * i,
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intc_context.mir[i]);
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/* MIRs are saved and restore with other PRCM registers */
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}
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void omap3_intc_prepare_idle(void)
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{
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/*
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* Disable autoidle as it can stall interrupt controller,
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* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
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*/
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intc_writel(INTC_SYSCONFIG, 0);
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}
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void omap3_intc_resume_idle(void)
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{
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/* Re-enable autoidle */
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intc_writel(INTC_SYSCONFIG, 1);
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}
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/* XXX: FIQ and additional INTC support (only MPU at the moment) */
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static void omap_ack_irq(struct irq_data *d)
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{
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@ -125,6 +181,12 @@ int omap_irq_pending(void)
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return 0;
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}
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void omap3_intc_suspend(void)
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{
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/* A pending interrupt would prevent OMAP from entering suspend */
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omap_ack_irq(NULL);
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}
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static __init void
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omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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{
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@ -265,69 +327,6 @@ void __init omap_intc_of_init(void)
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of_irq_init(irq_match);
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}
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static struct omap_intc_regs intc_context;
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void omap_intc_save_context(void)
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{
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int i;
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intc_context.sysconfig =
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intc_readl(INTC_SYSCONFIG);
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intc_context.protection =
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intc_readl(INTC_PROTECTION);
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intc_context.idle =
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intc_readl(INTC_IDLE);
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intc_context.threshold =
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intc_readl(INTC_THRESHOLD);
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for (i = 0; i < omap_nr_irqs; i++)
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intc_context.ilr[i] =
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intc_readl((INTC_ILR0 + 0x4 * i));
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for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
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intc_context.mir[i] =
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intc_readl(INTC_MIR0 + (0x20 * i));
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}
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void omap_intc_restore_context(void)
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{
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int i;
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intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
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intc_writel(INTC_PROTECTION, intc_context.protection);
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intc_writel(INTC_IDLE, intc_context.idle);
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intc_writel(INTC_THRESHOLD, intc_context.threshold);
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for (i = 0; i < omap_nr_irqs; i++)
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intc_writel(INTC_ILR0 + 0x4 * i,
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intc_context.ilr[i]);
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for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
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intc_writel(INTC_MIR0 + 0x20 * i,
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intc_context.mir[i]);
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/* MIRs are saved and restore with other PRCM registers */
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}
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void omap3_intc_suspend(void)
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{
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/* A pending interrupt would prevent OMAP from entering suspend */
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omap_ack_irq(NULL);
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}
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void omap3_intc_prepare_idle(void)
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{
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/*
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* Disable autoidle as it can stall interrupt controller,
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* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
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*/
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intc_writel(INTC_SYSCONFIG, 0);
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}
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void omap3_intc_resume_idle(void)
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{
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/* Re-enable autoidle */
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intc_writel(INTC_SYSCONFIG, 1);
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}
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asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
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{
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omap_intc_handle_irq(regs);
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