MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd
Compared to the old xrx200_phy_fw driver the new version has multiple enhancements. The name of the firmware files does not have to be added to all .dts files anymore - one now configures the GPHY mode (FE or GE) instead. Each GPHY can now also boot separate firmware (thus mixing of GE and FE GPHYs is now possible). The new implementation is based on the RCU syscon-mfd and uses the reeset_controller framework instead of raw RCU register reads/writes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Cc: john@phrozen.org Cc: p.zabel@pengutronix.de Cc: kishon@ti.com Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17128/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Martin Blumenstingl
Ralf Baechle
parent
ba73f0bcce
commit
126534141b
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@ -0,0 +1,36 @@
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Lantiq XWAY SoC GPHY binding
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============================
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This binding describes a software-defined ethernet PHY, provided by the RCU
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module on newer Lantiq XWAY SoCs (xRX200 and newer).
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-------------------------------------------------------------------------------
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Required properties:
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- compatible : Should be one of
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"lantiq,xrx200a1x-gphy"
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"lantiq,xrx200a2x-gphy"
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"lantiq,xrx300-gphy"
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"lantiq,xrx330-gphy"
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- reg : Addrress of the GPHY FW load address register
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- resets : Must reference the RCU GPHY reset bit
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- reset-names : One entry, value must be "gphy" or optional "gphy2"
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- clocks : A reference to the (PMU) GPHY clock gate
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Optional properties:
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- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
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<dt-bindings/mips/lantiq_xway_gphy.h>
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-------------------------------------------------------------------------------
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Example for the GPHys on the xRX200 SoCs:
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#include <dt-bindings/mips/lantiq_rcu_gphy.h>
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gphy0: gphy@20 {
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compatible = "lantiq,xrx200a2x-gphy";
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reg = <0x20 0x4>;
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resets = <&reset0 31 30>, <&reset1 7 7>;
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reset-names = "gphy", "gphy2";
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clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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@ -518,7 +518,8 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
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PMU_PPE_DP | PMU_PPE_TC);
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clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
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clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
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clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY);
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clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY);
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clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
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clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
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clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
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@ -541,7 +542,8 @@ void __init ltq_soc_init(void)
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PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
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PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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PMU_PPE_QSB | PMU_PPE_TOP);
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clkdev_add_pmu("1f203000.rcu", "gphy", 0, 0, PMU_GPHY);
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clkdev_add_pmu("1f203020.gphy", NULL, 0, 0, PMU_GPHY);
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clkdev_add_pmu("1f203068.gphy", NULL, 0, 0, PMU_GPHY);
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clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
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clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
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clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
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@ -1 +1,2 @@
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obj-y += fpi-bus.o
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obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
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@ -0,0 +1,260 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2012 John Crispin <blogic@phrozen.org>
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* Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/firmware.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/reboot.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/property.h>
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#include <dt-bindings/mips/lantiq_rcu_gphy.h>
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#include <lantiq_soc.h>
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#define XRX200_GPHY_FW_ALIGN (16 * 1024)
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struct xway_gphy_priv {
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struct clk *gphy_clk_gate;
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struct reset_control *gphy_reset;
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struct reset_control *gphy_reset2;
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struct notifier_block gphy_reboot_nb;
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void __iomem *membase;
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char *fw_name;
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};
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struct xway_gphy_match_data {
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char *fe_firmware_name;
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char *ge_firmware_name;
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};
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static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
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.fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
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.ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
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};
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static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
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.fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
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.ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
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};
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static const struct xway_gphy_match_data xrx300_gphy_data = {
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.fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
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.ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
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};
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static const struct of_device_id xway_gphy_match[] = {
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{ .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
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{ .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
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{ .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
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{ .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, xway_gphy_match);
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static struct xway_gphy_priv *to_xway_gphy_priv(struct notifier_block *nb)
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{
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return container_of(nb, struct xway_gphy_priv, gphy_reboot_nb);
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}
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static int xway_gphy_reboot_notify(struct notifier_block *reboot_nb,
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unsigned long code, void *unused)
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{
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struct xway_gphy_priv *priv = to_xway_gphy_priv(reboot_nb);
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if (priv) {
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reset_control_assert(priv->gphy_reset);
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reset_control_assert(priv->gphy_reset2);
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}
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return NOTIFY_DONE;
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}
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static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
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dma_addr_t *dev_addr)
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{
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const struct firmware *fw;
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void *fw_addr;
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dma_addr_t dma_addr;
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size_t size;
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int ret;
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ret = request_firmware(&fw, priv->fw_name, dev);
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if (ret) {
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dev_err(dev, "failed to load firmware: %s, error: %i\n",
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priv->fw_name, ret);
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return ret;
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}
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/*
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* GPHY cores need the firmware code in a persistent and contiguous
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* memory area with a 16 kB boundary aligned start address.
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*/
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size = fw->size + XRX200_GPHY_FW_ALIGN;
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fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
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if (fw_addr) {
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fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
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*dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
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memcpy(fw_addr, fw->data, fw->size);
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} else {
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dev_err(dev, "failed to alloc firmware memory\n");
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ret = -ENOMEM;
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}
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release_firmware(fw);
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return ret;
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}
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static int xway_gphy_of_probe(struct platform_device *pdev,
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struct xway_gphy_priv *priv)
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{
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struct device *dev = &pdev->dev;
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const struct xway_gphy_match_data *gphy_fw_name_cfg;
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u32 gphy_mode;
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int ret;
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struct resource *res_gphy;
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gphy_fw_name_cfg = of_device_get_match_data(dev);
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priv->gphy_clk_gate = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->gphy_clk_gate)) {
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dev_err(dev, "Failed to lookup gate clock\n");
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return PTR_ERR(priv->gphy_clk_gate);
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}
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res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->membase = devm_ioremap_resource(dev, res_gphy);
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if (IS_ERR(priv->membase))
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return PTR_ERR(priv->membase);
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priv->gphy_reset = devm_reset_control_get(dev, "gphy");
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if (IS_ERR(priv->gphy_reset)) {
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if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
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dev_err(dev, "Failed to lookup gphy reset\n");
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return PTR_ERR(priv->gphy_reset);
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}
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priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2");
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if (IS_ERR(priv->gphy_reset2))
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return PTR_ERR(priv->gphy_reset2);
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ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
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/* Default to GE mode */
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if (ret)
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gphy_mode = GPHY_MODE_GE;
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switch (gphy_mode) {
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case GPHY_MODE_FE:
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priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
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break;
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case GPHY_MODE_GE:
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priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
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break;
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default:
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dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
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return -EINVAL;
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}
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return 0;
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}
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static int xway_gphy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct xway_gphy_priv *priv;
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dma_addr_t fw_addr = 0;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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ret = xway_gphy_of_probe(pdev, priv);
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if (ret)
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return ret;
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ret = clk_prepare_enable(priv->gphy_clk_gate);
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if (ret)
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return ret;
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ret = xway_gphy_load(dev, priv, &fw_addr);
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if (ret) {
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clk_disable_unprepare(priv->gphy_clk_gate);
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return ret;
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}
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reset_control_assert(priv->gphy_reset);
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reset_control_assert(priv->gphy_reset2);
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iowrite32be(fw_addr, priv->membase);
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reset_control_deassert(priv->gphy_reset);
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reset_control_deassert(priv->gphy_reset2);
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/* assert the gphy reset because it can hang after a reboot: */
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priv->gphy_reboot_nb.notifier_call = xway_gphy_reboot_notify;
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priv->gphy_reboot_nb.priority = -1;
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ret = register_reboot_notifier(&priv->gphy_reboot_nb);
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if (ret)
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dev_warn(dev, "Failed to register reboot notifier\n");
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platform_set_drvdata(pdev, priv);
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return ret;
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}
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static int xway_gphy_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
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int ret;
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reset_control_assert(priv->gphy_reset);
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reset_control_assert(priv->gphy_reset2);
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iowrite32be(0, priv->membase);
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clk_disable_unprepare(priv->gphy_clk_gate);
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ret = unregister_reboot_notifier(&priv->gphy_reboot_nb);
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if (ret)
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dev_warn(dev, "Failed to unregister reboot notifier\n");
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return 0;
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}
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static struct platform_driver xway_gphy_driver = {
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.probe = xway_gphy_probe,
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.remove = xway_gphy_remove,
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.driver = {
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.name = "xway-rcu-gphy",
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.of_match_table = xway_gphy_match,
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},
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};
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module_platform_driver(xway_gphy_driver);
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MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
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MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
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MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
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MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
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MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
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MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
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MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
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MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
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MODULE_LICENSE("GPL");
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@ -0,0 +1,15 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
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*/
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#ifndef _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
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#define _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
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#define GPHY_MODE_GE 1
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#define GPHY_MODE_FE 2
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#endif /* _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H */
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