hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sparc: io: implement dummy relaxed accessor macros for writes 

write{b,w,l,q}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.

This patch adds dummy macros for the write accessors to sparc, in the
same vein as the dummy definitions for the relaxed read accessors. The
existing relaxed read{b,w,l} accessors are moved into asm/io.h, since
they are identical between 32-bit and 64-bit machines.

Acked-by: "David S. Miller" <davem@davemloft.net>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon 2013-09-04 11:34:08 +01:00
parent 5da590574c
commit 1191ccb34c
3 changed files with 11 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/sparc/include/asm/io.h
View File

@ -10,6 +10,15 @@
* Defines used for both SPARC32 and SPARC64
*/
/* Relaxed accessors for MMIO */
#define readb_relaxed(__addr) readb(__addr)
#define readw_relaxed(__addr) readw(__addr)
#define readl_relaxed(__addr) readl(__addr)
#define writeb_relaxed(__b, __addr) writeb(__b, __addr)
#define writew_relaxed(__w, __addr) writew(__w, __addr)
#define writel_relaxed(__l, __addr) writel(__l, __addr)
/* Big endian versions of memory read/write routines */
#define readb_be(__addr) __raw_readb(__addr)
#define readw_be(__addr) __raw_readw(__addr)

4
arch/sparc/include/asm/io_32.h
View File

@ -4,10 +4,6 @@
#include <linux/kernel.h>
#include <linux/ioport.h> /* struct resource */
#define readb_relaxed(__addr) readb(__addr)
#define readw_relaxed(__addr) readw(__addr)
#define readl_relaxed(__addr) readl(__addr)
#define IO_SPACE_LIMIT 0xffffffff
#define memset_io(d,c,sz) _memset_io(d,c,sz)

8
arch/sparc/include/asm/io_64.h
View File

@ -136,6 +136,7 @@ static inline u32 readl(const volatile void __iomem *addr)
}
#define readq readq
#define readq_relaxed readq
static inline u64 readq(const volatile void __iomem *addr)
{ u64 ret;
@ -175,6 +176,7 @@ static inline void writel(u32 l, volatile void __iomem *addr)
}
#define writeq writeq
#define writeq_relaxed writeq
static inline void writeq(u64 q, volatile void __iomem *addr)
{
__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
@ -183,7 +185,6 @@ static inline void writeq(u64 q, volatile void __iomem *addr)
: "memory");
}
#define inb inb
static inline u8 inb(unsigned long addr)
{
@ -264,11 +265,6 @@ static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned l
outsl((unsigned long __force)port, buf, count);
}
#define readb_relaxed(__addr) readb(__addr)
#define readw_relaxed(__addr) readw(__addr)
#define readl_relaxed(__addr) readl(__addr)
#define readq_relaxed(__addr) readq(__addr)
/* Valid I/O Space regions are anywhere, because each PCI bus supported
* can live in an arbitrary area of the physical address range.
*/