brcmsmac: correct phy registers for TSSI-based power control
A number of additional phy registers needs to be programmed when using TSSI-based power control. Tested-by: David Herrmann <dh.herrmann@gmail.com> Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -2020,6 +2020,16 @@ wlc_lcnphy_set_tssi_mux(struct brcms_phy *pi, enum lcnphy_tssi_mode pos)
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} else {
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mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1);
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mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
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mod_radio_reg(pi, RADIO_2064_REG028, 0x1, 0x0);
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mod_radio_reg(pi, RADIO_2064_REG11A, 0x4, 1<<2);
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mod_radio_reg(pi, RADIO_2064_REG036, 0x10, 0x0);
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mod_radio_reg(pi, RADIO_2064_REG11A, 0x10, 1<<4);
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mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0);
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mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x77);
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mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0xe<<1);
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mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 1<<7);
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mod_radio_reg(pi, RADIO_2064_REG005, 0x7, 1<<1);
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mod_radio_reg(pi, RADIO_2064_REG029, 0xf0, 0<<4);
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}
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} else {
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mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2);
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@ -2106,6 +2116,7 @@ static void wlc_lcnphy_pwrctrl_rssiparams(struct brcms_phy *pi)
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(auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
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mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5));
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mod_radio_reg(pi, RADIO_2064_REG07C, (1 << 0), (1 << 0));
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}
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static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
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@ -2218,6 +2229,10 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
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mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8);
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mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x0);
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mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0);
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mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
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wlc_lcnphy_pwrctrl_rssiparams(pi);
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}
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@ -3096,6 +3111,11 @@ static void wlc_lcnphy_tx_pwr_ctrl_init(struct brcms_phy_pub *ppi)
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wlc_lcnphy_write_table(pi, &tab);
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tab.tbl_offset++;
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}
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mod_phy_reg(pi, 0x4d0, (0x1 << 0), (0) << 0);
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mod_phy_reg(pi, 0x4d3, (0xff << 0), (0) << 0);
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mod_phy_reg(pi, 0x4d3, (0xff << 8), (0) << 8);
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mod_phy_reg(pi, 0x4d0, (0x1 << 4), (0) << 4);
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mod_phy_reg(pi, 0x4d0, (0x1 << 2), (0) << 2);
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mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7);
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