Merge branch 'pci/host-thunder' into next
* pci/host-thunder: PCI/ACPI: Add ThunderX pass2.x 2nd node MCFG quirk PCI/ACPI: Tidy up MCFG quirk whitespace PCI: Avoid generating invalid ThunderX2 DMA aliases PCI: Add device flag PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT PCI: Apply Cavium ACS quirk only to CN81xx/CN83xx/CN88xx devices
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commit
1154768ad3
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@ -54,6 +54,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
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#define QCOM_ECAM32(seg) \
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{ "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
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QCOM_ECAM32(0),
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QCOM_ECAM32(1),
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QCOM_ECAM32(2),
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@ -68,6 +69,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
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{ "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
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{ "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
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{ "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
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HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
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HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
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HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
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@ -77,6 +79,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
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#define THUNDER_PEM_RES(addr, node) \
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DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
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#define THUNDER_PEM_QUIRK(rev, node) \
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{ "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
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&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
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@ -90,13 +93,16 @@ static struct mcfg_fixup mcfg_quirks[] = {
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&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
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{ "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
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&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
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/* SoC pass2.x */
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THUNDER_PEM_QUIRK(1, 0),
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THUNDER_PEM_QUIRK(1, 1),
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#define THUNDER_ECAM_QUIRK(rev, seg) \
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{ "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
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&pci_thunder_ecam_ops }
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/* SoC pass2.x */
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THUNDER_PEM_QUIRK(1, 0),
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THUNDER_PEM_QUIRK(1, 1),
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THUNDER_ECAM_QUIRK(1, 10),
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/* SoC pass1.x */
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THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
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THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
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@ -112,9 +118,11 @@ static struct mcfg_fixup mcfg_quirks[] = {
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#define XGENE_V1_ECAM_MCFG(rev, seg) \
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{"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
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&xgene_v1_pcie_ecam_ops }
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#define XGENE_V2_ECAM_MCFG(rev, seg) \
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{"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
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&xgene_v2_pcie_ecam_ops }
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/* X-Gene SoC with v1 PCIe controller */
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XGENE_V1_ECAM_MCFG(1, 0),
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XGENE_V1_ECAM_MCFG(1, 1),
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@ -3957,6 +3957,20 @@ static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
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/*
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* The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
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* associated not at the root bus, but at a bridge below. This quirk avoids
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* generating invalid DMA aliases.
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*/
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static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
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{
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pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
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quirk_bridge_cavm_thrx2_pcie_root);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
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quirk_bridge_cavm_thrx2_pcie_root);
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/*
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* Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
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* class code. Fix it.
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@ -4095,6 +4109,9 @@ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
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acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
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PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
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if (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff)))
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return -ENOTTY;
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return acs_flags ? 0 : 1;
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}
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@ -60,6 +60,10 @@ int pci_for_each_dma_alias(struct pci_dev *pdev,
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tmp = bus->self;
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/* stop at bridge where translation unit is associated */
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if (tmp->dev_flags & PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT)
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return ret;
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/*
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* PCIe-to-PCI/X bridges alias transactions from downstream
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* devices using the subordinate bus number (PCI Express to
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@ -178,6 +178,8 @@ enum pci_dev_flags {
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PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
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/* Get VPD from function 0 VPD */
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PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
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/* a non-root bridge where translation occurs, stop alias search here */
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PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
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};
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enum pci_irq_reroute_variant {
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