iio: adc: add exynos adc driver under iio framwork
This patch adds New driver to support: 1. Supports ADC IF found on EXYNOS4412/EXYNOS5250 and future SoCs from Samsung 2. Add ADC driver under iio/adc framework 3. Also adds the Documentation for device tree bindings Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Naveen Krishna Chatradhi
Jonathan Cameron
parent
43bb786ad2
commit
10f5b14811
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@ -0,0 +1,52 @@
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Samsung Exynos Analog to Digital Converter bindings
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This devicetree binding are for the new adc driver written fori
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Exynos4 and upward SoCs from Samsung.
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New driver handles the following
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1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
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and future SoCs from Samsung
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2. Add ADC driver under iio/adc framework
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3. Also adds the Documentation for device tree bindings
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Required properties:
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- compatible: Must be "samsung,exynos-adc-v1"
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for exynos4412/5250 controllers.
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Must be "samsung,exynos-adc-v2" for
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future controllers.
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- reg: Contains ADC register address range (base address and
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length).
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- interrupts: Contains the interrupt information for the timer. The
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format is being dependent on which interrupt controller
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the Samsung device uses.
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- #io-channel-cells = <1>; As ADC has multiple outputs
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Note: child nodes can be added for auto probing from device tree.
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Example: adding device info in dtsi file
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adc: adc@12D10000 {
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compatible = "samsung,exynos-adc-v1";
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reg = <0x12D10000 0x100>;
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interrupts = <0 106 0>;
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#io-channel-cells = <1>;
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io-channel-ranges;
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};
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Example: Adding child nodes in dts file
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adc@12D10000 {
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/* NTC thermistor is a hwmon device */
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ncp15wb473@0 {
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compatible = "ntc,ncp15wb473";
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pullup-uV = <1800000>;
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pullup-ohm = <47000>;
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pulldown-ohm = <0>;
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io-channels = <&adc 4>;
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};
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};
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Note: Does not apply to ADC driver under arch/arm/plat-samsung/
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Note: The child node can be added under the adc node or seperately.
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@ -103,6 +103,13 @@ config AT91_ADC
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help
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Say yes here to build support for Atmel AT91 ADC.
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config EXYNOS_ADC
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bool "Exynos ADC driver support"
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help
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Core support for the ADC block found in the Samsung EXYNOS series
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of SoCs for drivers such as the touchscreen and hwmon to use to share
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this resource.
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config LP8788_ADC
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bool "LP8788 ADC driver"
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depends on MFD_LP8788
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@ -11,6 +11,7 @@ obj-$(CONFIG_AD7791) += ad7791.o
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obj-$(CONFIG_AD7793) += ad7793.o
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obj-$(CONFIG_AD7887) += ad7887.o
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obj-$(CONFIG_AT91_ADC) += at91_adc.o
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obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o
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obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o
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obj-$(CONFIG_MAX1363) += max1363.o
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obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
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@ -0,0 +1,440 @@
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/*
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* exynos_adc.c - Support for ADC in EXYNOS SoCs
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*
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* 8 ~ 10 channel, 10/12-bit ADC
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*
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* Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/regulator/consumer.h>
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#include <linux/of_platform.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/machine.h>
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#include <linux/iio/driver.h>
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enum adc_version {
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ADC_V1,
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ADC_V2
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};
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/* EXYNOS4412/5250 ADC_V1 registers definitions */
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#define ADC_V1_CON(x) ((x) + 0x00)
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#define ADC_V1_DLY(x) ((x) + 0x08)
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#define ADC_V1_DATX(x) ((x) + 0x0C)
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#define ADC_V1_INTCLR(x) ((x) + 0x18)
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#define ADC_V1_MUX(x) ((x) + 0x1c)
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/* Future ADC_V2 registers definitions */
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#define ADC_V2_CON1(x) ((x) + 0x00)
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#define ADC_V2_CON2(x) ((x) + 0x04)
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#define ADC_V2_STAT(x) ((x) + 0x08)
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#define ADC_V2_INT_EN(x) ((x) + 0x10)
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#define ADC_V2_INT_ST(x) ((x) + 0x14)
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#define ADC_V2_VER(x) ((x) + 0x20)
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/* Bit definitions for ADC_V1 */
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#define ADC_V1_CON_RES (1u << 16)
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#define ADC_V1_CON_PRSCEN (1u << 14)
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#define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
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#define ADC_V1_CON_STANDBY (1u << 2)
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/* Bit definitions for ADC_V2 */
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#define ADC_V2_CON1_SOFT_RESET (1u << 2)
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#define ADC_V2_CON2_OSEL (1u << 10)
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#define ADC_V2_CON2_ESEL (1u << 9)
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#define ADC_V2_CON2_HIGHF (1u << 8)
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#define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4)
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#define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0)
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#define ADC_V2_CON2_ACH_MASK 0xF
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#define MAX_ADC_V2_CHANNELS 10
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#define MAX_ADC_V1_CHANNELS 8
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/* Bit definitions common for ADC_V1 and ADC_V2 */
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#define ADC_CON_EN_START (1u << 0)
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#define ADC_DATX_MASK 0xFFF
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#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(1000))
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struct exynos_adc {
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void __iomem *regs;
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struct clk *clk;
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unsigned int irq;
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struct regulator *vdd;
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struct completion completion;
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u32 value;
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unsigned int version;
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};
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static const struct of_device_id exynos_adc_match[] = {
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{ .compatible = "samsung,exynos-adc-v1", .data = (void *)ADC_V1 },
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{ .compatible = "samsung,exynos-adc-v2", .data = (void *)ADC_V2 },
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{},
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};
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MODULE_DEVICE_TABLE(of, exynos_adc_match);
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static inline unsigned int exynos_adc_get_version(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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match = of_match_node(exynos_adc_match, pdev->dev.of_node);
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return (unsigned int)match->data;
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}
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static int exynos_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long mask)
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{
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struct exynos_adc *info = iio_priv(indio_dev);
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unsigned long timeout;
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u32 con1, con2;
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if (mask != IIO_CHAN_INFO_RAW)
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return -EINVAL;
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mutex_lock(&indio_dev->mlock);
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/* Select the channel to be used and Trigger conversion */
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if (info->version == ADC_V2) {
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con2 = readl(ADC_V2_CON2(info->regs));
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con2 &= ~ADC_V2_CON2_ACH_MASK;
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con2 |= ADC_V2_CON2_ACH_SEL(chan->address);
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writel(con2, ADC_V2_CON2(info->regs));
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con1 = readl(ADC_V2_CON1(info->regs));
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writel(con1 | ADC_CON_EN_START,
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ADC_V2_CON1(info->regs));
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} else {
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writel(chan->address, ADC_V1_MUX(info->regs));
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con1 = readl(ADC_V1_CON(info->regs));
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writel(con1 | ADC_CON_EN_START,
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ADC_V1_CON(info->regs));
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}
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timeout = wait_for_completion_interruptible_timeout
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(&info->completion, EXYNOS_ADC_TIMEOUT);
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*val = info->value;
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mutex_unlock(&indio_dev->mlock);
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if (timeout == 0)
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return -ETIMEDOUT;
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return IIO_VAL_INT;
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}
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static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
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{
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struct exynos_adc *info = (struct exynos_adc *)dev_id;
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/* Read value */
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info->value = readl(ADC_V1_DATX(info->regs)) &
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ADC_DATX_MASK;
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/* clear irq */
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if (info->version == ADC_V2)
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writel(1, ADC_V2_INT_ST(info->regs));
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else
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writel(1, ADC_V1_INTCLR(info->regs));
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complete(&info->completion);
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return IRQ_HANDLED;
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}
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static int exynos_adc_reg_access(struct iio_dev *indio_dev,
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unsigned reg, unsigned writeval,
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unsigned *readval)
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{
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struct exynos_adc *info = iio_priv(indio_dev);
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if (readval == NULL)
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return -EINVAL;
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*readval = readl(info->regs + reg);
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return 0;
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}
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static const struct iio_info exynos_adc_iio_info = {
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.read_raw = &exynos_read_raw,
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.debugfs_reg_access = &exynos_adc_reg_access,
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.driver_module = THIS_MODULE,
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};
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#define ADC_CHANNEL(_index, _id) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = _index, \
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.address = _index, \
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.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT, \
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.datasheet_name = _id, \
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}
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static const struct iio_chan_spec exynos_adc_iio_channels[] = {
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ADC_CHANNEL(0, "adc0"),
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ADC_CHANNEL(1, "adc1"),
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ADC_CHANNEL(2, "adc2"),
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ADC_CHANNEL(3, "adc3"),
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ADC_CHANNEL(4, "adc4"),
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ADC_CHANNEL(5, "adc5"),
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ADC_CHANNEL(6, "adc6"),
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ADC_CHANNEL(7, "adc7"),
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ADC_CHANNEL(8, "adc8"),
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ADC_CHANNEL(9, "adc9"),
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};
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static int exynos_adc_remove_devices(struct device *dev, void *c)
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{
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struct platform_device *pdev = to_platform_device(dev);
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platform_device_unregister(pdev);
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return 0;
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}
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static void exynos_adc_hw_init(struct exynos_adc *info)
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{
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u32 con1, con2;
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if (info->version == ADC_V2) {
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con1 = ADC_V2_CON1_SOFT_RESET;
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writel(con1, ADC_V2_CON1(info->regs));
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con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
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ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
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writel(con2, ADC_V2_CON2(info->regs));
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/* Enable interrupts */
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writel(1, ADC_V2_INT_EN(info->regs));
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} else {
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/* set default prescaler values and Enable prescaler */
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con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
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/* Enable 12-bit ADC resolution */
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con1 |= ADC_V1_CON_RES;
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writel(con1, ADC_V1_CON(info->regs));
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}
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}
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static int exynos_adc_probe(struct platform_device *pdev)
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{
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struct exynos_adc *info = NULL;
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struct device_node *np = pdev->dev.of_node;
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struct iio_dev *indio_dev = NULL;
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struct resource *mem;
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int ret = -ENODEV;
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int irq;
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if (!np)
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return ret;
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indio_dev = iio_device_alloc(sizeof(struct exynos_adc));
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if (!indio_dev) {
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dev_err(&pdev->dev, "failed allocating iio device\n");
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return -ENOMEM;
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}
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info = iio_priv(indio_dev);
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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info->regs = devm_request_and_ioremap(&pdev->dev, mem);
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if (!info->regs) {
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ret = -ENOMEM;
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goto err_iio;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "no irq resource?\n");
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ret = irq;
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goto err_iio;
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}
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info->irq = irq;
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init_completion(&info->completion);
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ret = request_irq(info->irq, exynos_adc_isr,
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0, dev_name(&pdev->dev), info);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
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info->irq);
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goto err_iio;
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}
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info->clk = devm_clk_get(&pdev->dev, "adc");
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if (IS_ERR(info->clk)) {
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dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
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PTR_ERR(info->clk));
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ret = PTR_ERR(info->clk);
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goto err_irq;
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}
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info->vdd = devm_regulator_get(&pdev->dev, "vdd");
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if (IS_ERR(info->vdd)) {
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dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
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PTR_ERR(info->vdd));
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ret = PTR_ERR(info->vdd);
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goto err_irq;
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}
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info->version = exynos_adc_get_version(pdev);
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platform_set_drvdata(pdev, indio_dev);
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indio_dev->name = dev_name(&pdev->dev);
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indio_dev->dev.parent = &pdev->dev;
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indio_dev->dev.of_node = pdev->dev.of_node;
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indio_dev->info = &exynos_adc_iio_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = exynos_adc_iio_channels;
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if (info->version == ADC_V1)
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indio_dev->num_channels = MAX_ADC_V1_CHANNELS;
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else
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indio_dev->num_channels = MAX_ADC_V2_CHANNELS;
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ret = iio_device_register(indio_dev);
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if (ret)
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goto err_irq;
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ret = regulator_enable(info->vdd);
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if (ret)
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goto err_iio_dev;
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clk_prepare_enable(info->clk);
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exynos_adc_hw_init(info);
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ret = of_platform_populate(np, exynos_adc_match, NULL, &pdev->dev);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed adding child nodes\n");
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goto err_of_populate;
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}
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return 0;
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err_of_populate:
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device_for_each_child(&pdev->dev, NULL,
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exynos_adc_remove_devices);
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regulator_disable(info->vdd);
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clk_disable_unprepare(info->clk);
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err_iio_dev:
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iio_device_unregister(indio_dev);
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err_irq:
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free_irq(info->irq, info);
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err_iio:
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iio_device_free(indio_dev);
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return ret;
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}
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static int exynos_adc_remove(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev = platform_get_drvdata(pdev);
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struct exynos_adc *info = iio_priv(indio_dev);
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device_for_each_child(&pdev->dev, NULL,
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exynos_adc_remove_devices);
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regulator_disable(info->vdd);
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clk_disable_unprepare(info->clk);
|
||||
iio_device_unregister(indio_dev);
|
||||
free_irq(info->irq, info);
|
||||
iio_device_free(indio_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos_adc_suspend(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct exynos_adc *info = platform_get_drvdata(pdev);
|
||||
u32 con;
|
||||
|
||||
if (info->version == ADC_V2) {
|
||||
con = readl(ADC_V2_CON1(info->regs));
|
||||
con &= ~ADC_CON_EN_START;
|
||||
writel(con, ADC_V2_CON1(info->regs));
|
||||
} else {
|
||||
con = readl(ADC_V1_CON(info->regs));
|
||||
con |= ADC_V1_CON_STANDBY;
|
||||
writel(con, ADC_V1_CON(info->regs));
|
||||
}
|
||||
|
||||
clk_disable_unprepare(info->clk);
|
||||
regulator_disable(info->vdd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos_adc_resume(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct exynos_adc *info = platform_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
ret = regulator_enable(info->vdd);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clk_prepare_enable(info->clk);
|
||||
|
||||
exynos_adc_hw_init(info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
|
||||
exynos_adc_suspend,
|
||||
exynos_adc_resume);
|
||||
|
||||
static struct platform_driver exynos_adc_driver = {
|
||||
.probe = exynos_adc_probe,
|
||||
.remove = exynos_adc_remove,
|
||||
.driver = {
|
||||
.name = "exynos-adc",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(exynos_adc_match),
|
||||
.pm = &exynos_adc_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(exynos_adc_driver);
|
||||
|
||||
MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
|
||||
MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue