MIPS: Add P6600 cases to CPU switch statements
Add cases supporting the P6600 CPU to various switch statements in core MIPS kernel code that define behaviour dependent upon the CPU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Petri Gynther <pgynther@google.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12343/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -79,6 +79,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
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#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
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case CPU_I6400:
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case CPU_P6600:
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#endif
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#ifdef CONFIG_SYS_HAS_CPU_R3000
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@ -539,6 +539,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
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switch (c->cputype) {
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case CPU_PROAPTIV:
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case CPU_P5600:
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case CPU_P6600:
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/* proAptiv & related cores use Config6 to enable the FTLB */
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config = read_c0_config6();
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/* Clear the old probability value */
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@ -1556,6 +1556,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
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#endif
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break;
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case CPU_P5600:
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case CPU_P6600:
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case CPU_I6400:
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/* 8-bit event numbers */
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raw_id = config & 0x1ff;
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@ -1718,6 +1719,11 @@ init_hw_perf_events(void)
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mipspmu.general_event_map = &mipsxxcore_event_map2;
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mipspmu.cache_event_map = &mipsxxcore_cache_map2;
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break;
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case CPU_P6600:
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mipspmu.name = "mips/P6600";
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mipspmu.general_event_map = &mipsxxcore_event_map2;
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mipspmu.cache_event_map = &mipsxxcore_cache_map2;
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break;
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case CPU_I6400:
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mipspmu.name = "mips/I6400";
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mipspmu.general_event_map = &mipsxxcore_event_map2;
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@ -210,6 +210,7 @@ void spram_config(void)
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case CPU_P5600:
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case CPU_QEMU_GENERIC:
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case CPU_I6400:
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case CPU_P6600:
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config0 = read_c0_config();
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/* FIXME: addresses are Malta specific */
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if (config0 & (1<<24)) {
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@ -1644,6 +1644,7 @@ static inline void parity_protection_init(void)
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case CPU_P5600:
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case CPU_QEMU_GENERIC:
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case CPU_I6400:
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case CPU_P6600:
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{
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#define ERRCTL_PE 0x80000000
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#define ERRCTL_L2P 0x00800000
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@ -1285,6 +1285,7 @@ static void probe_pcache(void)
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case CPU_M5150:
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case CPU_QEMU_GENERIC:
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case CPU_I6400:
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case CPU_P6600:
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if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
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(c->icache.waysize > PAGE_SIZE))
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c->icache.flags |= MIPS_CACHE_ALIASES;
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@ -141,6 +141,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
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case CPU_P5600:
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case CPU_BMIPS5000:
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case CPU_QEMU_GENERIC:
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case CPU_P6600:
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if (config2 & (1 << 12))
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return 0;
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}
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