OMAPDSS: DPI: use new clock calculation code
Use the new clock calculation code in the DPI driver. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen
parent
36816faadf
commit
100c826235
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@ -105,31 +105,170 @@ static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
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}
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}
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struct dpi_clk_calc_ctx {
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struct platform_device *dsidev;
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/* inputs */
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unsigned long pck_min, pck_max;
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/* outputs */
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struct dsi_clock_info dsi_cinfo;
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struct dss_clock_info dss_cinfo;
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struct dispc_clock_info dispc_cinfo;
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};
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static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
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unsigned long pck, void *data)
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{
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struct dpi_clk_calc_ctx *ctx = data;
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/*
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* Odd dividers give us uneven duty cycle, causing problem when level
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* shifted. So skip all odd dividers when the pixel clock is on the
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* higher side.
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*/
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if (ctx->pck_min >= 1000000) {
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if (lckd > 1 && lckd % 2 != 0)
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return false;
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if (pckd > 1 && pckd % 2 != 0)
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return false;
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}
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ctx->dispc_cinfo.lck_div = lckd;
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ctx->dispc_cinfo.pck_div = pckd;
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ctx->dispc_cinfo.lck = lck;
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ctx->dispc_cinfo.pck = pck;
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return true;
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}
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static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
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void *data)
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{
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struct dpi_clk_calc_ctx *ctx = data;
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/*
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* Odd dividers give us uneven duty cycle, causing problem when level
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* shifted. So skip all odd dividers when the pixel clock is on the
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* higher side.
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*/
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if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 1000000)
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return false;
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ctx->dsi_cinfo.regm_dispc = regm_dispc;
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ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
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return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
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dpi_calc_dispc_cb, ctx);
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}
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static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
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unsigned long pll,
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void *data)
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{
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struct dpi_clk_calc_ctx *ctx = data;
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ctx->dsi_cinfo.regn = regn;
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ctx->dsi_cinfo.regm = regm;
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ctx->dsi_cinfo.fint = fint;
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ctx->dsi_cinfo.clkin4ddr = pll;
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return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min,
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dpi_calc_hsdiv_cb, ctx);
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}
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static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data)
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{
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struct dpi_clk_calc_ctx *ctx = data;
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ctx->dss_cinfo.fck = fck;
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ctx->dss_cinfo.fck_div = fckd;
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return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
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dpi_calc_dispc_cb, ctx);
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}
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static bool dpi_dsi_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
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{
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unsigned long clkin;
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unsigned long pll_min, pll_max;
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clkin = dsi_get_pll_clkin(dpi.dsidev);
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memset(ctx, 0, sizeof(*ctx));
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ctx->dsidev = dpi.dsidev;
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ctx->pck_min = pck - 1000;
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ctx->pck_max = pck + 1000;
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ctx->dsi_cinfo.clkin = clkin;
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pll_min = 0;
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pll_max = 0;
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return dsi_pll_calc(dpi.dsidev, clkin,
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pll_min, pll_max,
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dpi_calc_pll_cb, ctx);
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}
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static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
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{
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int i;
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/*
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* DSS fck gives us very few possibilities, so finding a good pixel
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* clock may not be possible. We try multiple times to find the clock,
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* each time widening the pixel clock range we look for, up to
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* +/- 1MHz.
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*/
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for (i = 0; i < 10; ++i) {
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bool ok;
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memset(ctx, 0, sizeof(*ctx));
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if (pck > 1000 * i * i * i)
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ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
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else
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ctx->pck_min = 0;
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ctx->pck_max = pck + 1000 * i * i * i;
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ok = dss_div_calc(ctx->pck_min, dpi_calc_dss_cb, ctx);
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if (ok)
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return ok;
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}
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return false;
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}
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static int dpi_set_dsi_clk(enum omap_channel channel,
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unsigned long pck_req, unsigned long *fck, int *lck_div,
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int *pck_div)
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{
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struct dsi_clock_info dsi_cinfo;
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struct dispc_clock_info dispc_cinfo;
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struct dpi_clk_calc_ctx ctx;
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int r;
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bool ok;
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r = dsi_pll_calc_clock_div_pck(dpi.dsidev, pck_req, &dsi_cinfo,
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&dispc_cinfo);
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if (r)
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return r;
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ok = dpi_dsi_clk_calc(pck_req, &ctx);
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if (!ok)
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return -EINVAL;
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r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
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r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo);
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if (r)
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return r;
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dss_select_lcd_clk_source(channel,
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dpi_get_alt_clk_src(channel));
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dpi.mgr_config.clock_info = dispc_cinfo;
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dpi.mgr_config.clock_info = ctx.dispc_cinfo;
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*fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
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*lck_div = dispc_cinfo.lck_div;
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*pck_div = dispc_cinfo.pck_div;
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*fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
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*lck_div = ctx.dispc_cinfo.lck_div;
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*pck_div = ctx.dispc_cinfo.pck_div;
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return 0;
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}
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@ -137,23 +276,23 @@ static int dpi_set_dsi_clk(enum omap_channel channel,
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static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck,
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int *lck_div, int *pck_div)
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{
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struct dss_clock_info dss_cinfo;
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struct dispc_clock_info dispc_cinfo;
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struct dpi_clk_calc_ctx ctx;
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int r;
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bool ok;
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r = dss_calc_clock_div(pck_req, &dss_cinfo, &dispc_cinfo);
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ok = dpi_dss_clk_calc(pck_req, &ctx);
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if (!ok)
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return -EINVAL;
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r = dss_set_clock_div(&ctx.dss_cinfo);
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if (r)
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return r;
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r = dss_set_clock_div(&dss_cinfo);
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if (r)
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return r;
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dpi.mgr_config.clock_info = ctx.dispc_cinfo;
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dpi.mgr_config.clock_info = dispc_cinfo;
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*fck = dss_cinfo.fck;
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*lck_div = dispc_cinfo.lck_div;
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*pck_div = dispc_cinfo.pck_div;
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*fck = ctx.dss_cinfo.fck;
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*lck_div = ctx.dispc_cinfo.lck_div;
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*pck_div = ctx.dispc_cinfo.pck_div;
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return 0;
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}
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@ -333,12 +472,12 @@ EXPORT_SYMBOL(omapdss_dpi_set_timings);
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int dpi_check_timings(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings)
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{
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int r;
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struct omap_overlay_manager *mgr = dpi.output.manager;
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int lck_div, pck_div;
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unsigned long fck;
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unsigned long pck;
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struct dispc_clock_info dispc_cinfo;
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struct dpi_clk_calc_ctx ctx;
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bool ok;
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if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
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return -EINVAL;
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@ -347,28 +486,21 @@ int dpi_check_timings(struct omap_dss_device *dssdev,
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return -EINVAL;
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if (dpi.dsidev) {
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struct dsi_clock_info dsi_cinfo;
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r = dsi_pll_calc_clock_div_pck(dpi.dsidev,
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timings->pixel_clock * 1000,
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&dsi_cinfo, &dispc_cinfo);
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ok = dpi_dsi_clk_calc(timings->pixel_clock * 1000, &ctx);
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if (!ok)
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return -EINVAL;
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if (r)
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return r;
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fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
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fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
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} else {
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struct dss_clock_info dss_cinfo;
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r = dss_calc_clock_div(timings->pixel_clock * 1000,
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&dss_cinfo, &dispc_cinfo);
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ok = dpi_dss_clk_calc(timings->pixel_clock * 1000, &ctx);
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if (!ok)
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return -EINVAL;
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if (r)
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return r;
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fck = dss_cinfo.fck;
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fck = ctx.dss_cinfo.fck;
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}
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lck_div = dispc_cinfo.lck_div;
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pck_div = dispc_cinfo.pck_div;
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lck_div = ctx.dispc_cinfo.lck_div;
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pck_div = ctx.dispc_cinfo.pck_div;
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pck = fck / lck_div / pck_div / 1000;
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