hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'cxgb4-next' 

Hariprasad Shenai says:

====================
RDMA/cxgb4,cxgb4vf,csiostor: Cleanup macros

This series continues to cleanup all the macros/register defines related to
filter, port, VI, queue, RSS, LDST, firmware, etc that are defined in t4fw_api.h
and the affected files.

Will post few more series so that we can cover all the macros so that they all
follow the same style to be consistent.

The patches series is created against 'net-next' tree.
And includes patches on cxgb4, cxgb4vf, iw_cxgb4 and csiostor driver.

We have included all the maintainers of respective drivers. Kindly review the
change and let us know in case of any review comments.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2014-11-22 16:57:52 -05:00
parent 2f90ade661 b2e1a3f091
commit 100414137e
17 changed files with 1925 additions and 1242 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/infiniband/hw/cxgb4/cm.c
View File

@ -478,7 +478,7 @@ static void send_flowc(struct c4iw_ep *ep, struct sk_buff *skb)
16)) | FW_WR_FLOWID_V(ep->hwtid));
flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
flowc->mnemval[0].val = cpu_to_be32(FW_PFVF_CMD_PFN
flowc->mnemval[0].val = cpu_to_be32(FW_PFVF_CMD_PFN_V
(ep->com.dev->rdev.lldi.pf));
flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
flowc->mnemval[1].val = cpu_to_be32(ep->tx_chan);
@ -1762,10 +1762,10 @@ static void send_fw_act_open_req(struct c4iw_ep *ep, unsigned int atid)
req->le.pport = sin->sin_port;
req->le.u.ipv4.pip = sin->sin_addr.s_addr;
req->tcb.t_state_to_astid =
htonl(V_FW_OFLD_CONNECTION_WR_T_STATE(TCP_SYN_SENT) |
V_FW_OFLD_CONNECTION_WR_ASTID(atid));
htonl(FW_OFLD_CONNECTION_WR_T_STATE_V(TCP_SYN_SENT) |
FW_OFLD_CONNECTION_WR_ASTID_V(atid));
req->tcb.cplrxdataack_cplpassacceptrpl =
htons(F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK);
htons(FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F);
req->tcb.tx_max = (__force __be32) jiffies;
req->tcb.rcv_adv = htons(1);
best_mtu(ep->com.dev->rdev.lldi.mtus, ep->mtu, &mtu_idx,
@ -3539,7 +3539,7 @@ static void send_fw_pass_open_req(struct c4iw_dev *dev, struct sk_buff *skb,
memset(req, 0, sizeof(*req));
req->op_compl = htonl(V_WR_OP(FW_OFLD_CONNECTION_WR) | FW_WR_COMPL_F);
req->len16_pkd = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*req), 16)));
req->le.version_cpl = htonl(F_FW_OFLD_CONNECTION_WR_CPL);
req->le.version_cpl = htonl(FW_OFLD_CONNECTION_WR_CPL_F);
req->le.filter = (__force __be32) filter;
req->le.lport = lport;
req->le.pport = rport;
@ -3548,9 +3548,9 @@ static void send_fw_pass_open_req(struct c4iw_dev *dev, struct sk_buff *skb,
req->tcb.rcv_nxt = htonl(rcv_isn + 1);
req->tcb.rcv_adv = htons(window);
req->tcb.t_state_to_astid =
htonl(V_FW_OFLD_CONNECTION_WR_T_STATE(TCP_SYN_RECV) |
V_FW_OFLD_CONNECTION_WR_RCV_SCALE(cpl->tcpopt.wsf) |
V_FW_OFLD_CONNECTION_WR_ASTID(
htonl(FW_OFLD_CONNECTION_WR_T_STATE_V(TCP_SYN_RECV) |
FW_OFLD_CONNECTION_WR_RCV_SCALE_V(cpl->tcpopt.wsf) |
FW_OFLD_CONNECTION_WR_ASTID_V(
GET_PASS_OPEN_TID(ntohl(cpl->tos_stid))));
/*

8
drivers/infiniband/hw/cxgb4/provider.c
View File

@ -408,10 +408,10 @@ static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr,
PDBG("%s dev 0x%p\n", __func__, dev);
return sprintf(buf, "%u.%u.%u.%u\n",
FW_HDR_FW_VER_MAJOR_GET(c4iw_dev->rdev.lldi.fw_vers),
FW_HDR_FW_VER_MINOR_GET(c4iw_dev->rdev.lldi.fw_vers),
FW_HDR_FW_VER_MICRO_GET(c4iw_dev->rdev.lldi.fw_vers),
FW_HDR_FW_VER_BUILD_GET(c4iw_dev->rdev.lldi.fw_vers));
FW_HDR_FW_VER_MAJOR_G(c4iw_dev->rdev.lldi.fw_vers),
FW_HDR_FW_VER_MINOR_G(c4iw_dev->rdev.lldi.fw_vers),
FW_HDR_FW_VER_MICRO_G(c4iw_dev->rdev.lldi.fw_vers),
FW_HDR_FW_VER_BUILD_G(c4iw_dev->rdev.lldi.fw_vers));
}
static ssize_t show_hca(struct device *dev, struct device_attribute *attr,

8
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
View File

@ -318,10 +318,10 @@ struct adapter_params {
#include "t4fw_api.h"
#define FW_VERSION(chip) ( \
FW_HDR_FW_VER_MAJOR_GET(chip##FW_VERSION_MAJOR) | \
FW_HDR_FW_VER_MINOR_GET(chip##FW_VERSION_MINOR) | \
FW_HDR_FW_VER_MICRO_GET(chip##FW_VERSION_MICRO) | \
FW_HDR_FW_VER_BUILD_GET(chip##FW_VERSION_BUILD))
FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
struct fw_info {

14
drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.c
View File

@ -243,7 +243,7 @@ void cxgb4_dcb_handle_fw_update(struct adapter *adap,
const struct fw_port_cmd *pcmd)
{
const union fw_port_dcb *fwdcb = &pcmd->u.dcb;
int port = FW_PORT_CMD_PORTID_GET(be32_to_cpu(pcmd->op_to_portid));
int port = FW_PORT_CMD_PORTID_G(be32_to_cpu(pcmd->op_to_portid));
struct net_device *dev = adap->port[port];
struct port_info *pi = netdev_priv(dev);
struct port_dcb_info *dcb = &pi->dcb;
@ -256,12 +256,12 @@ void cxgb4_dcb_handle_fw_update(struct adapter *adap,
if (dcb_type == FW_PORT_DCB_TYPE_CONTROL) {
enum cxgb4_dcb_state_input input =
((pcmd->u.dcb.control.all_syncd_pkd &
FW_PORT_CMD_ALL_SYNCD)
FW_PORT_CMD_ALL_SYNCD_F)
? CXGB4_DCB_STATE_FW_ALLSYNCED
: CXGB4_DCB_STATE_FW_INCOMPLETE);
if (dcb->dcb_version != FW_PORT_DCB_VER_UNKNOWN) {
dcb_running_version = FW_PORT_CMD_DCB_VERSION_GET(
dcb_running_version = FW_PORT_CMD_DCB_VERSION_G(
be16_to_cpu(
pcmd->u.dcb.control.dcb_version_to_app_state));
if (dcb_running_version == FW_PORT_DCB_VER_CEE1D01 ||
@ -519,7 +519,7 @@ static void cxgb4_setpgtccfg_tx(struct net_device *dev, int tc,
INIT_PORT_DCB_WRITE_CMD(pcmd, pi->port_id);
if (pi->dcb.state == CXGB4_DCB_STATE_HOST)
pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY);
pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY_F);
err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
if (err != FW_PORT_DCB_CFG_SUCCESS)
@ -583,7 +583,7 @@ static void cxgb4_setpgbwgcfg_tx(struct net_device *dev, int pgid,
INIT_PORT_DCB_WRITE_CMD(pcmd, pi->port_id);
if (pi->dcb.state == CXGB4_DCB_STATE_HOST)
pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY);
pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY_F);
err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
@ -623,7 +623,7 @@ static void cxgb4_setpfccfg(struct net_device *dev, int priority, u8 pfccfg)
INIT_PORT_DCB_WRITE_CMD(pcmd, pi->port_id);
if (pi->dcb.state == CXGB4_DCB_STATE_HOST)
pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY);
pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY_F);
pcmd.u.dcb.pfc.type = FW_PORT_DCB_TYPE_PFC;
pcmd.u.dcb.pfc.pfcen = pi->dcb.pfcen;
@ -842,7 +842,7 @@ static int __cxgb4_setapp(struct net_device *dev, u8 app_idtype, u16 app_id,
/* write out new app table entry */
INIT_PORT_DCB_WRITE_CMD(pcmd, pi->port_id);
if (pi->dcb.state == CXGB4_DCB_STATE_HOST)
pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY);
pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY_F);
pcmd.u.dcb.app_priority.type = FW_PORT_DCB_TYPE_APP_ID;
pcmd.u.dcb.app_priority.protocolid = cpu_to_be16(app_id);

4
drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h
View File

@ -45,9 +45,9 @@
cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | \
FW_CMD_REQUEST_F | \
FW_CMD_##__op##_F | \
FW_PORT_CMD_PORTID(__port)); \
FW_PORT_CMD_PORTID_V(__port)); \
(__pcmd).action_to_len16 = \
cpu_to_be32(FW_PORT_CMD_ACTION(__action) | \
cpu_to_be32(FW_PORT_CMD_ACTION_V(__action) | \
FW_LEN16(pcmd)); \
} while (0)

193
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
View File

@ -141,7 +141,7 @@ static unsigned int pfvfres_pmask(struct adapter *adapter,
* Give PF's access to all of the ports.
*/
if (vf == 0)
return FW_PFVF_CMD_PMASK_MASK;
return FW_PFVF_CMD_PMASK_M;
/*
* For VFs, we'll assign them access to the ports based purely on the
@ -512,9 +512,10 @@ static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
u32 name, value;
int err;
name = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
FW_PARAMS_PARAM_YZ(txq->q.cntxt_id));
name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
FW_PARAMS_PARAM_X_V(
FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
value = enable ? i : 0xffffffff;
/* Since we can be called while atomic (from "interrupt
@ -709,7 +710,7 @@ EXPORT_SYMBOL(cxgb4_dcb_enabled);
/* Handle a Data Center Bridging update message from the firmware. */
static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
{
int port = FW_PORT_CMD_PORTID_GET(ntohl(pcmd->op_to_portid));
int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
struct net_device *dev = adap->port[port];
int old_dcb_enabled = cxgb4_dcb_enabled(dev);
int new_dcb_enabled;
@ -834,15 +835,15 @@ static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
const struct fw_port_cmd *pcmd = (const void *)p->data;
unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
unsigned int action =
FW_PORT_CMD_ACTION_GET(ntohl(pcmd->action_to_len16));
FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
if (cmd == FW_PORT_CMD &&
action == FW_PORT_ACTION_GET_PORT_INFO) {
int port = FW_PORT_CMD_PORTID_GET(
int port = FW_PORT_CMD_PORTID_G(
be32_to_cpu(pcmd->op_to_portid));
struct net_device *dev = q->adap->port[port];
int state_input = ((pcmd->u.info.dcbxdis_pkd &
FW_PORT_CMD_DCBXDIS)
FW_PORT_CMD_DCBXDIS_F)
? CXGB4_DCB_INPUT_FW_DISABLED
: CXGB4_DCB_INPUT_FW_ENABLED);
@ -1342,49 +1343,49 @@ static int set_filter_wr(struct adapter *adapter, int fidx)
fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
fwr->tid_to_iq =
htonl(V_FW_FILTER_WR_TID(ftid) |
V_FW_FILTER_WR_RQTYPE(f->fs.type) |
V_FW_FILTER_WR_NOREPLY(0) |
V_FW_FILTER_WR_IQ(f->fs.iq));
htonl(FW_FILTER_WR_TID_V(ftid) |
FW_FILTER_WR_RQTYPE_V(f->fs.type) |
FW_FILTER_WR_NOREPLY_V(0) |
FW_FILTER_WR_IQ_V(f->fs.iq));
fwr->del_filter_to_l2tix =
htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
f->fs.newvlan == VLAN_REWRITE) |
V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
f->fs.newvlan == VLAN_REWRITE) |
V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
V_FW_FILTER_WR_PRIO(f->fs.prio) |
V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
FW_FILTER_WR_PRIO_V(f->fs.prio) |
FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
fwr->ethtype = htons(f->fs.val.ethtype);
fwr->ethtypem = htons(f->fs.mask.ethtype);
fwr->frag_to_ovlan_vldm =
(V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
(FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
fwr->smac_sel = 0;
fwr->rx_chan_rx_rpl_iq =
htons(V_FW_FILTER_WR_RX_CHAN(0) |
V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
htons(FW_FILTER_WR_RX_CHAN_V(0) |
FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
fwr->maci_to_matchtypem =
htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
V_FW_FILTER_WR_PORT(f->fs.val.iport) |
V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
FW_FILTER_WR_PORT_V(f->fs.val.iport) |
FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
fwr->ptcl = f->fs.val.proto;
fwr->ptclm = f->fs.mask.proto;
fwr->ttyp = f->fs.val.tos;
@ -1615,14 +1616,14 @@ static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
if (adapter->params.fw_vers)
snprintf(info->fw_version, sizeof(info->fw_version),
"%u.%u.%u.%u, TP %u.%u.%u.%u",
FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers),
FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
}
static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
@ -2717,9 +2718,10 @@ static int set_rspq_intr_params(struct sge_rspq *q,
new_idx = closest_thres(&adap->sge, cnt);
if (q->desc && q->pktcnt_idx != new_idx) {
/* the queue has already been created, update it */
v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
FW_PARAMS_PARAM_YZ(q->cntxt_id);
v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
FW_PARAMS_PARAM_X_V(
FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
&new_idx);
if (err)
@ -2933,7 +2935,7 @@ static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
int ret;
const struct firmware *fw;
struct adapter *adap = netdev2adap(netdev);
unsigned int mbox = FW_PCIE_FW_MASTER_MASK + 1;
unsigned int mbox = PCIE_FW_MASTER_M + 1;
ef->data[sizeof(ef->data) - 1] = '\0';
ret = request_firmware(&fw, ef->data, adap->pdev_dev);
@ -3044,45 +3046,45 @@ static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
info->data = 0;
switch (info->flow_type) {
case TCP_V4_FLOW:
if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F)
info->data = RXH_IP_SRC | RXH_IP_DST |
RXH_L4_B_0_1 | RXH_L4_B_2_3;
else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
info->data = RXH_IP_SRC | RXH_IP_DST;
break;
case UDP_V4_FLOW:
if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
(v & FW_RSS_VI_CONFIG_CMD_UDPEN))
if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) &&
(v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
info->data = RXH_IP_SRC | RXH_IP_DST |
RXH_L4_B_0_1 | RXH_L4_B_2_3;
else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
info->data = RXH_IP_SRC | RXH_IP_DST;
break;
case SCTP_V4_FLOW:
case AH_ESP_V4_FLOW:
case IPV4_FLOW:
if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
info->data = RXH_IP_SRC | RXH_IP_DST;
break;
case TCP_V6_FLOW:
if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F)
info->data = RXH_IP_SRC | RXH_IP_DST |
RXH_L4_B_0_1 | RXH_L4_B_2_3;
else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
info->data = RXH_IP_SRC | RXH_IP_DST;
break;
case UDP_V6_FLOW:
if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
(v & FW_RSS_VI_CONFIG_CMD_UDPEN))
if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) &&
(v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
info->data = RXH_IP_SRC | RXH_IP_DST |
RXH_L4_B_0_1 | RXH_L4_B_2_3;
else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
info->data = RXH_IP_SRC | RXH_IP_DST;
break;
case SCTP_V6_FLOW:
case AH_ESP_V6_FLOW:
case IPV6_FLOW:
if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
info->data = RXH_IP_SRC | RXH_IP_DST;
break;
}
@ -3418,7 +3420,7 @@ int cxgb4_clip_get(const struct net_device *dev,
memset(&c, 0, sizeof(c));
c.op_to_write = htonl(FW_CMD_OP_V(FW_CLIP_CMD) |
FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_ALLOC | FW_LEN16(c));
c.alloc_to_len16 = htonl(FW_CLIP_CMD_ALLOC_F | FW_LEN16(c));
c.ip_hi = *(__be64 *)(lip->s6_addr);
c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
@ -3435,7 +3437,7 @@ int cxgb4_clip_release(const struct net_device *dev,
memset(&c, 0, sizeof(c));
c.op_to_write = htonl(FW_CMD_OP_V(FW_CLIP_CMD) |
FW_CMD_REQUEST_F | FW_CMD_READ_F);
c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_FREE | FW_LEN16(c));
c.alloc_to_len16 = htonl(FW_CLIP_CMD_FREE_F | FW_LEN16(c));
c.ip_hi = *(__be64 *)(lip->s6_addr);
c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
@ -4870,11 +4872,11 @@ static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
htonl(FW_CMD_OP_V(FW_LDST_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_READ_F |
FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE));
ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS(1);
ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
ldst_cmd.u.pcie.ctrl_to_fn =
(FW_LDST_CMD_LC | FW_LDST_CMD_FN(adap->fn));
(FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->fn));
ldst_cmd.u.pcie.r = reg;
ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
&ldst_cmd);
@ -4986,8 +4988,8 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
ret = t4_config_glbl_rss(adap, adap->fn,
FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
if (ret < 0)
return ret;
@ -5148,8 +5150,8 @@ static int adap_init0_config(struct adapter *adapter, int reset)
if (cf->size >= FLASH_CFG_MAX_SIZE)
ret = -ENOMEM;
else {
params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
ret = t4_query_params(adapter, adapter->mbox,
adapter->fn, 0, 1, params, val);
if (ret == 0) {
@ -5167,8 +5169,8 @@ static int adap_init0_config(struct adapter *adapter, int reset)
size_t size = cf->size & ~0x3;
__be32 *data = (__be32 *)cf->data;
mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
mtype = FW_PARAMS_PARAM_Y_G(val[0]);
maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
spin_lock(&adapter->win0_lock);
ret = t4_memory_rw(adapter, 0, mtype, maddr,
@ -5209,9 +5211,9 @@ static int adap_init0_config(struct adapter *adapter, int reset)
FW_CMD_REQUEST_F |
FW_CMD_READ_F);
caps_cmd.cfvalid_to_len16 =
htonl(FW_CAPS_CONFIG_CMD_CFVALID |
FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
FW_LEN16(caps_cmd));
ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
&caps_cmd);
@ -5363,10 +5365,10 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
adapter->flags |= RSS_TNLALLLOOKUP;
ret = t4_config_glbl_rss(adapter, adapter->mbox,
FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F |
((adapter->flags & RSS_TNLALLLOOKUP) ?
FW_RSS_GLB_CONFIG_CMD_TNLALLLKP : 0));
FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F : 0));
if (ret < 0)
goto bye;
@ -5377,7 +5379,7 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
PFRES_NEQ, PFRES_NETHCTRL,
PFRES_NIQFLINT, PFRES_NIQ,
PFRES_TC, PFRES_NVI,
FW_PFVF_CMD_CMASK_MASK,
FW_PFVF_CMD_CMASK_M,
pfvfres_pmask(adapter, adapter->fn, 0),
PFRES_NEXACTF,
PFRES_R_CAPS, PFRES_WX_CAPS);
@ -5422,7 +5424,7 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
VFRES_NEQ, VFRES_NETHCTRL,
VFRES_NIQFLINT, VFRES_NIQ,
VFRES_TC, VFRES_NVI,
FW_PFVF_CMD_CMASK_MASK,
FW_PFVF_CMD_CMASK_M,
pfvfres_pmask(
adapter, pf, vf),
VFRES_NEXACTF,
@ -5686,8 +5688,8 @@ static int adap_init0(struct adapter *adap)
* and portvec ...
*/
v =
FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
if (ret < 0)
goto bye;
@ -5723,8 +5725,9 @@ static int adap_init0(struct adapter *adap)
* Find out whether we're dealing with a version of
* the firmware which has configuration file support.
*/
params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(
FW_PARAMS_PARAM_DEV_CF));
ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
params, val);
@ -5784,14 +5787,14 @@ static int adap_init0(struct adapter *adap)
* Grab some of our basic fundamental operating parameters.
*/
#define FW_PARAM_DEV(param) \
(FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
#define FW_PARAM_PFVF(param) \
FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)| \
FW_PARAMS_PARAM_Y(0) | \
FW_PARAMS_PARAM_Z(0)
FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
FW_PARAMS_PARAM_Y_V(0) | \
FW_PARAMS_PARAM_Z_V(0)
params[0] = FW_PARAM_PFVF(EQ_START);
params[1] = FW_PARAM_PFVF(L2T_START);

4
drivers/net/ethernet/chelsio/cxgb4/l2t.c
View File

@ -435,9 +435,9 @@ u64 cxgb4_select_ntuple(struct net_device *dev,
if (tp->vnic_shift >= 0) {
u32 viid = cxgb4_port_viid(dev);
u32 vf = FW_VIID_VIN_GET(viid);
u32 vf = FW_VIID_VIN_G(viid);
u32 pf = FW_VIID_PFN_G(viid);
u32 vld = FW_VIID_VIVLD_GET(viid);
u32 vld = FW_VIID_VIVLD_G(viid);
ntuple |= (u64)(V_FT_VNID_ID_VF(vf) |
V_FT_VNID_ID_PF(pf) |

115
drivers/net/ethernet/chelsio/cxgb4/sge.c
View File

@ -2299,18 +2299,18 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_CMD_EXEC_F |
FW_IQ_CMD_PFN(adap->fn) | FW_IQ_CMD_VFN(0));
c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC | FW_IQ_CMD_IQSTART(1) |
FW_IQ_CMD_PFN_V(adap->fn) | FW_IQ_CMD_VFN_V(0));
c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F | FW_IQ_CMD_IQSTART_F |
FW_LEN16(c));
c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
FW_IQ_CMD_IQASYNCH(fwevtq) | FW_IQ_CMD_VIID(pi->viid) |
FW_IQ_CMD_IQANDST(intr_idx < 0) | FW_IQ_CMD_IQANUD(1) |
FW_IQ_CMD_IQANDSTINDEX(intr_idx >= 0 ? intr_idx :
c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) |
FW_IQ_CMD_IQASYNCH_V(fwevtq) | FW_IQ_CMD_VIID_V(pi->viid) |
FW_IQ_CMD_IQANDST_V(intr_idx < 0) | FW_IQ_CMD_IQANUD_V(1) |
FW_IQ_CMD_IQANDSTINDEX_V(intr_idx >= 0 ? intr_idx :
-intr_idx - 1));
c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
FW_IQ_CMD_IQGTSMODE |
FW_IQ_CMD_IQINTCNTTHRESH(iq->pktcnt_idx) |
FW_IQ_CMD_IQESIZE(ilog2(iq->iqe_len) - 4));
c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(pi->tx_chan) |
FW_IQ_CMD_IQGTSMODE_F |
FW_IQ_CMD_IQINTCNTTHRESH_V(iq->pktcnt_idx) |
FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4));
c.iqsize = htons(iq->size);
c.iqaddr = cpu_to_be64(iq->phys_addr);
@ -2323,12 +2323,12 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
goto fl_nomem;
flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN(1) |
FW_IQ_CMD_FL0FETCHRO(1) |
FW_IQ_CMD_FL0DATARO(1) |
FW_IQ_CMD_FL0PADEN(1));
c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN(2) |
FW_IQ_CMD_FL0FBMAX(3));
c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN_F |
FW_IQ_CMD_FL0FETCHRO_F |
FW_IQ_CMD_FL0DATARO_F |
FW_IQ_CMD_FL0PADEN_F);
c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN_V(2) |
FW_IQ_CMD_FL0FBMAX_V(3));
c.fl0size = htons(flsz);
c.fl0addr = cpu_to_be64(fl->addr);
}
@ -2425,19 +2425,20 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_CMD_EXEC_F |
FW_EQ_ETH_CMD_PFN(adap->fn) | FW_EQ_ETH_CMD_VFN(0));
c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC |
FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
c.viid_pkd = htonl(FW_EQ_ETH_CMD_AUTOEQUEQE |
FW_EQ_ETH_CMD_VIID(pi->viid));
c.fetchszm_to_iqid = htonl(FW_EQ_ETH_CMD_HOSTFCMODE(2) |
FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) |
FW_EQ_ETH_CMD_FETCHRO(1) |
FW_EQ_ETH_CMD_IQID(iqid));
c.dcaen_to_eqsize = htonl(FW_EQ_ETH_CMD_FBMIN(2) |
FW_EQ_ETH_CMD_FBMAX(3) |
FW_EQ_ETH_CMD_CIDXFTHRESH(5) |
FW_EQ_ETH_CMD_EQSIZE(nentries));
FW_EQ_ETH_CMD_PFN_V(adap->fn) |
FW_EQ_ETH_CMD_VFN_V(0));
c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F |
FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c));
c.viid_pkd = htonl(FW_EQ_ETH_CMD_AUTOEQUEQE_F |
FW_EQ_ETH_CMD_VIID_V(pi->viid));
c.fetchszm_to_iqid = htonl(FW_EQ_ETH_CMD_HOSTFCMODE_V(2) |
FW_EQ_ETH_CMD_PCIECHN_V(pi->tx_chan) |
FW_EQ_ETH_CMD_FETCHRO_V(1) |
FW_EQ_ETH_CMD_IQID_V(iqid));
c.dcaen_to_eqsize = htonl(FW_EQ_ETH_CMD_FBMIN_V(2) |
FW_EQ_ETH_CMD_FBMAX_V(3) |
FW_EQ_ETH_CMD_CIDXFTHRESH_V(5) |
FW_EQ_ETH_CMD_EQSIZE_V(nentries));
c.eqaddr = cpu_to_be64(txq->q.phys_addr);
ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
@ -2451,7 +2452,7 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
return ret;
}
init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_GET(ntohl(c.eqid_pkd)));
init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_G(ntohl(c.eqid_pkd)));
txq->txq = netdevq;
txq->tso = txq->tx_cso = txq->vlan_ins = 0;
txq->mapping_err = 0;
@ -2478,20 +2479,20 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_CMD_EXEC_F |
FW_EQ_CTRL_CMD_PFN(adap->fn) |
FW_EQ_CTRL_CMD_VFN(0));
c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC |
FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID(cmplqid));
FW_EQ_CTRL_CMD_PFN_V(adap->fn) |
FW_EQ_CTRL_CMD_VFN_V(0));
c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F |
FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c));
c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID_V(cmplqid));
c.physeqid_pkd = htonl(0);
c.fetchszm_to_iqid = htonl(FW_EQ_CTRL_CMD_HOSTFCMODE(2) |
FW_EQ_CTRL_CMD_PCIECHN(pi->tx_chan) |
FW_EQ_CTRL_CMD_FETCHRO |
FW_EQ_CTRL_CMD_IQID(iqid));
c.dcaen_to_eqsize = htonl(FW_EQ_CTRL_CMD_FBMIN(2) |
FW_EQ_CTRL_CMD_FBMAX(3) |
FW_EQ_CTRL_CMD_CIDXFTHRESH(5) |
FW_EQ_CTRL_CMD_EQSIZE(nentries));
c.fetchszm_to_iqid = htonl(FW_EQ_CTRL_CMD_HOSTFCMODE_V(2) |
FW_EQ_CTRL_CMD_PCIECHN_V(pi->tx_chan) |
FW_EQ_CTRL_CMD_FETCHRO_F |
FW_EQ_CTRL_CMD_IQID_V(iqid));
c.dcaen_to_eqsize = htonl(FW_EQ_CTRL_CMD_FBMIN_V(2) |
FW_EQ_CTRL_CMD_FBMAX_V(3) |
FW_EQ_CTRL_CMD_CIDXFTHRESH_V(5) |
FW_EQ_CTRL_CMD_EQSIZE_V(nentries));
c.eqaddr = cpu_to_be64(txq->q.phys_addr);
ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
@ -2503,7 +2504,7 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
return ret;
}
init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_GET(ntohl(c.cmpliqid_eqid)));
init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_G(ntohl(c.cmpliqid_eqid)));
txq->adap = adap;
skb_queue_head_init(&txq->sendq);
tasklet_init(&txq->qresume_tsk, restart_ctrlq, (unsigned long)txq);
@ -2532,18 +2533,18 @@ int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_CMD_EXEC_F |
FW_EQ_OFLD_CMD_PFN(adap->fn) |
FW_EQ_OFLD_CMD_VFN(0));
c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC |
FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
c.fetchszm_to_iqid = htonl(FW_EQ_OFLD_CMD_HOSTFCMODE(2) |
FW_EQ_OFLD_CMD_PCIECHN(pi->tx_chan) |
FW_EQ_OFLD_CMD_FETCHRO(1) |
FW_EQ_OFLD_CMD_IQID(iqid));
c.dcaen_to_eqsize = htonl(FW_EQ_OFLD_CMD_FBMIN(2) |
FW_EQ_OFLD_CMD_FBMAX(3) |
FW_EQ_OFLD_CMD_CIDXFTHRESH(5) |
FW_EQ_OFLD_CMD_EQSIZE(nentries));
FW_EQ_OFLD_CMD_PFN_V(adap->fn) |
FW_EQ_OFLD_CMD_VFN_V(0));
c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F |
FW_EQ_OFLD_CMD_EQSTART_F | FW_LEN16(c));
c.fetchszm_to_iqid = htonl(FW_EQ_OFLD_CMD_HOSTFCMODE_V(2) |
FW_EQ_OFLD_CMD_PCIECHN_V(pi->tx_chan) |
FW_EQ_OFLD_CMD_FETCHRO_F |
FW_EQ_OFLD_CMD_IQID_V(iqid));
c.dcaen_to_eqsize = htonl(FW_EQ_OFLD_CMD_FBMIN_V(2) |
FW_EQ_OFLD_CMD_FBMAX_V(3) |
FW_EQ_OFLD_CMD_CIDXFTHRESH_V(5) |
FW_EQ_OFLD_CMD_EQSIZE_V(nentries));
c.eqaddr = cpu_to_be64(txq->q.phys_addr);
ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
@ -2557,7 +2558,7 @@ int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
return ret;
}
init_txq(adap, &txq->q, FW_EQ_OFLD_CMD_EQID_GET(ntohl(c.eqid_pkd)));
init_txq(adap, &txq->q, FW_EQ_OFLD_CMD_EQID_G(ntohl(c.eqid_pkd)));
txq->adap = adap;
skb_queue_head_init(&txq->sendq);
tasklet_init(&txq->qresume_tsk, restart_ofldq, (unsigned long)txq);

292
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
View File

@ -188,9 +188,9 @@ static void t4_report_fw_error(struct adapter *adap)
u32 pcie_fw;
pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
if (pcie_fw & FW_PCIE_FW_ERR)
if (pcie_fw & PCIE_FW_ERR)
dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
reason[FW_PCIE_FW_EVAL_GET(pcie_fw)]);
reason[PCIE_FW_EVAL_G(pcie_fw)]);
}
/*
@ -711,8 +711,8 @@ int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
* Ask firmware for the Core Clock since it knows how to translate the
* Reference Clock ('V2') VPD field into a Core Clock value ...
*/
cclk_param = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
ret = t4_query_params(adapter, adapter->mbox, 0, 0,
1, &cclk_param, &cclk_val);
@ -993,10 +993,10 @@ static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
install:
dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
"installing firmware %u.%u.%u.%u on card.\n",
FW_HDR_FW_VER_MAJOR_GET(c), FW_HDR_FW_VER_MINOR_GET(c),
FW_HDR_FW_VER_MICRO_GET(c), FW_HDR_FW_VER_BUILD_GET(c), reason,
FW_HDR_FW_VER_MAJOR_GET(k), FW_HDR_FW_VER_MINOR_GET(k),
FW_HDR_FW_VER_MICRO_GET(k), FW_HDR_FW_VER_BUILD_GET(k));
FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
return 1;
}
@ -1068,12 +1068,12 @@ int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
"driver compiled with %d.%d.%d.%d, "
"card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
state,
FW_HDR_FW_VER_MAJOR_GET(d), FW_HDR_FW_VER_MINOR_GET(d),
FW_HDR_FW_VER_MICRO_GET(d), FW_HDR_FW_VER_BUILD_GET(d),
FW_HDR_FW_VER_MAJOR_GET(c), FW_HDR_FW_VER_MINOR_GET(c),
FW_HDR_FW_VER_MICRO_GET(c), FW_HDR_FW_VER_BUILD_GET(c),
FW_HDR_FW_VER_MAJOR_GET(k), FW_HDR_FW_VER_MINOR_GET(k),
FW_HDR_FW_VER_MICRO_GET(k), FW_HDR_FW_VER_BUILD_GET(k));
FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
ret = EINVAL;
goto bye;
}
@ -1237,7 +1237,7 @@ int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
struct link_config *lc)
{
struct fw_port_cmd c;
unsigned int fc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO);
unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
lc->link_ok = 0;
if (lc->requested_fc & PAUSE_RX)
@ -1247,8 +1247,8 @@ int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
memset(&c, 0, sizeof(c));
c.op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) | FW_CMD_REQUEST_F |
FW_CMD_EXEC_F | FW_PORT_CMD_PORTID(port));
c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
FW_CMD_EXEC_F | FW_PORT_CMD_PORTID_V(port));
c.action_to_len16 = htonl(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
FW_LEN16(c));
if (!(lc->supported & FW_PORT_CAP_ANEG)) {
@ -1277,8 +1277,8 @@ int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
memset(&c, 0, sizeof(c));
c.op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) | FW_CMD_REQUEST_F |
FW_CMD_EXEC_F | FW_PORT_CMD_PORTID(port));
c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
FW_CMD_EXEC_F | FW_PORT_CMD_PORTID_V(port));
c.action_to_len16 = htonl(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
FW_LEN16(c));
c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG);
return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
@ -1564,7 +1564,7 @@ static void cim_intr_handler(struct adapter *adapter)
int fat;
if (t4_read_reg(adapter, MA_PCIE_FW) & FW_PCIE_FW_ERR)
if (t4_read_reg(adapter, MA_PCIE_FW) & PCIE_FW_ERR)
t4_report_fw_error(adapter);
fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
@ -2074,7 +2074,7 @@ int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
memset(&cmd, 0, sizeof(cmd));
cmd.op_to_viid = htonl(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
FW_RSS_IND_TBL_CMD_VIID(viid));
FW_RSS_IND_TBL_CMD_VIID_V(viid));
cmd.retval_len16 = htonl(FW_LEN16(cmd));
/* each fw_rss_ind_tbl_cmd takes up to 32 entries */
@ -2091,13 +2091,13 @@ int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
while (nq > 0) {
unsigned int v;
v = FW_RSS_IND_TBL_CMD_IQ0(*rsp);
v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
if (++rsp >= rsp_end)
rsp = rspq;
v |= FW_RSS_IND_TBL_CMD_IQ1(*rsp);
v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
if (++rsp >= rsp_end)
rsp = rspq;
v |= FW_RSS_IND_TBL_CMD_IQ2(*rsp);
v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
if (++rsp >= rsp_end)
rsp = rspq;
@ -2131,10 +2131,10 @@ int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
c.retval_len16 = htonl(FW_LEN16(c));
if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
} else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
c.u.basicvirtual.mode_pkd =
htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
htonl(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags);
} else
return -EINVAL;
@ -2556,11 +2556,11 @@ void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
memset(wr, 0, sizeof(*wr));
wr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
wr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*wr) / 16));
wr->tid_to_iq = htonl(V_FW_FILTER_WR_TID(ftid) |
V_FW_FILTER_WR_NOREPLY(qid < 0));
wr->del_filter_to_l2tix = htonl(F_FW_FILTER_WR_DEL_FILTER);
wr->tid_to_iq = htonl(FW_FILTER_WR_TID_V(ftid) |
FW_FILTER_WR_NOREPLY_V(qid < 0));
wr->del_filter_to_l2tix = htonl(FW_FILTER_WR_DEL_FILTER_F);
if (qid >= 0)
wr->rx_chan_rx_rpl_iq = htons(V_FW_FILTER_WR_RX_RPL_IQ(qid));
wr->rx_chan_rx_rpl_iq = htons(FW_FILTER_WR_RX_RPL_IQ_V(qid));
}
#define INIT_CMD(var, cmd, rd_wr) do { \
@ -2577,7 +2577,7 @@ int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
memset(&c, 0, sizeof(c));
c.op_to_addrspace = htonl(FW_CMD_OP_V(FW_LDST_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F |
FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE));
FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE));
c.cycles_to_len16 = htonl(FW_LEN16(c));
c.u.addrval.addr = htonl(addr);
c.u.addrval.val = htonl(val);
@ -2604,10 +2604,10 @@ int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
memset(&c, 0, sizeof(c));
c.op_to_addrspace = htonl(FW_CMD_OP_V(FW_LDST_CMD) | FW_CMD_REQUEST_F |
FW_CMD_READ_F | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
FW_CMD_READ_F | FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO));
c.cycles_to_len16 = htonl(FW_LEN16(c));
c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
FW_LDST_CMD_MMD(mmd));
c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR_V(phy_addr) |
FW_LDST_CMD_MMD_V(mmd));
c.u.mdio.raddr = htons(reg);
ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
@ -2634,10 +2634,10 @@ int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
memset(&c, 0, sizeof(c));
c.op_to_addrspace = htonl(FW_CMD_OP_V(FW_LDST_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
FW_CMD_WRITE_F | FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO));
c.cycles_to_len16 = htonl(FW_LEN16(c));
c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
FW_LDST_CMD_MMD(mmd));
c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR_V(phy_addr) |
FW_LDST_CMD_MMD_V(mmd));
c.u.mdio.raddr = htons(reg);
c.u.mdio.rval = htons(val);
@ -2774,13 +2774,13 @@ retry:
memset(&c, 0, sizeof(c));
INIT_CMD(c, HELLO, WRITE);
c.err_to_clearinit = htonl(
FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
FW_HELLO_CMD_MBMASTER_MASK) |
FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
FW_HELLO_CMD_STAGE(fw_hello_cmd_stage_os) |
FW_HELLO_CMD_CLEARINIT);
FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ? mbox :
FW_HELLO_CMD_MBMASTER_M) |
FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
FW_HELLO_CMD_CLEARINIT_F);
/*
* Issue the HELLO command to the firmware. If it's not successful
@ -2793,17 +2793,17 @@ retry:
if (ret < 0) {
if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
goto retry;
if (t4_read_reg(adap, MA_PCIE_FW) & FW_PCIE_FW_ERR)
if (t4_read_reg(adap, MA_PCIE_FW) & PCIE_FW_ERR)
t4_report_fw_error(adap);
return ret;
}
v = ntohl(c.err_to_clearinit);
master_mbox = FW_HELLO_CMD_MBMASTER_GET(v);
master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
if (state) {
if (v & FW_HELLO_CMD_ERR)
if (v & FW_HELLO_CMD_ERR_F)
*state = DEV_STATE_ERR;
else if (v & FW_HELLO_CMD_INIT)
else if (v & FW_HELLO_CMD_INIT_F)
*state = DEV_STATE_INIT;
else
*state = DEV_STATE_UNINIT;
@ -2818,9 +2818,9 @@ retry:
* and we wouldn't want to fail pointlessly. (This can happen when an
* OS loads lots of different drivers rapidly at the same time). In
* this case, the Master PF returned by the firmware will be
* FW_PCIE_FW_MASTER_MASK so the test below will work ...
* PCIE_FW_MASTER_M so the test below will work ...
*/
if ((v & (FW_HELLO_CMD_ERR|FW_HELLO_CMD_INIT)) == 0 &&
if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
master_mbox != mbox) {
int waiting = FW_CMD_HELLO_TIMEOUT;
@ -2844,7 +2844,7 @@ retry:
* our retries ...
*/
pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
if (!(pcie_fw & (FW_PCIE_FW_ERR|FW_PCIE_FW_INIT))) {
if (!(pcie_fw & (PCIE_FW_ERR|PCIE_FW_INIT))) {
if (waiting <= 0) {
if (retries-- > 0)
goto retry;
@ -2859,9 +2859,9 @@ retry:
* report errors preferentially.
*/
if (state) {
if (pcie_fw & FW_PCIE_FW_ERR)
if (pcie_fw & PCIE_FW_ERR)
*state = DEV_STATE_ERR;
else if (pcie_fw & FW_PCIE_FW_INIT)
else if (pcie_fw & PCIE_FW_INIT)
*state = DEV_STATE_INIT;
}
@ -2870,9 +2870,9 @@ retry:
* there's not a valid Master PF, grab its identity
* for our caller.
*/
if (master_mbox == FW_PCIE_FW_MASTER_MASK &&
(pcie_fw & FW_PCIE_FW_MASTER_VLD))
master_mbox = FW_PCIE_FW_MASTER_GET(pcie_fw);
if (master_mbox == PCIE_FW_MASTER_M &&
(pcie_fw & PCIE_FW_MASTER_VLD))
master_mbox = PCIE_FW_MASTER_G(pcie_fw);
break;
}
}
@ -2940,7 +2940,7 @@ int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
* Issues a RESET command to firmware (if desired) with a HALT indication
* and then puts the microprocessor into RESET state. The RESET command
* will only be issued if a legitimate mailbox is provided (mbox <=
* FW_PCIE_FW_MASTER_MASK).
* PCIE_FW_MASTER_M).
*
* This is generally used in order for the host to safely manipulate the
* adapter without fear of conflicting with whatever the firmware might
@ -2955,13 +2955,13 @@ static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
* If a legitimate mailbox is provided, issue a RESET command
* with a HALT indication.
*/
if (mbox <= FW_PCIE_FW_MASTER_MASK) {
if (mbox <= PCIE_FW_MASTER_M) {
struct fw_reset_cmd c;
memset(&c, 0, sizeof(c));
INIT_CMD(c, RESET, WRITE);
c.val = htonl(PIORST | PIORSTMODE);
c.halt_pkd = htonl(FW_RESET_CMD_HALT(1U));
c.halt_pkd = htonl(FW_RESET_CMD_HALT_F);
ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
}
@ -2980,8 +2980,8 @@ static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
*/
if (ret == 0 || force) {
t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);
t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT,
FW_PCIE_FW_HALT);
t4_set_reg_field(adap, PCIE_FW, PCIE_FW_HALT_F,
PCIE_FW_HALT_F);
}
/*
@ -3020,7 +3020,7 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
* doing it automatically, we need to clear the PCIE_FW.HALT
* bit.
*/
t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT, 0);
t4_set_reg_field(adap, PCIE_FW, PCIE_FW_HALT_F, 0);
/*
* If we've been given a valid mailbox, first try to get the
@ -3029,7 +3029,7 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
* valid mailbox or the RESET command failed, fall back to
* hitting the chip with a hammer.
*/
if (mbox <= FW_PCIE_FW_MASTER_MASK) {
if (mbox <= PCIE_FW_MASTER_M) {
t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
msleep(100);
if (t4_fw_reset(adap, mbox,
@ -3044,7 +3044,7 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
if (!(t4_read_reg(adap, PCIE_FW) & FW_PCIE_FW_HALT))
if (!(t4_read_reg(adap, PCIE_FW) & PCIE_FW_HALT_F))
return 0;
msleep(100);
ms += 100;
@ -3252,8 +3252,8 @@ int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_PARAMS_CMD) | FW_CMD_REQUEST_F |
FW_CMD_READ_F | FW_PARAMS_CMD_PFN(pf) |
FW_PARAMS_CMD_VFN(vf));
FW_CMD_READ_F | FW_PARAMS_CMD_PFN_V(pf) |
FW_PARAMS_CMD_VFN_V(vf));
c.retval_len16 = htonl(FW_LEN16(c));
for (i = 0; i < nparams; i++, p += 2)
*p = htonl(*params++);
@ -3293,8 +3293,8 @@ int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox,
memset(&c, 0, sizeof(c));
c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
FW_PARAMS_CMD_PFN(pf) |
FW_PARAMS_CMD_VFN(vf));
FW_PARAMS_CMD_PFN_V(pf) |
FW_PARAMS_CMD_VFN_V(vf));
c.retval_len16 = cpu_to_be32(FW_LEN16(c));
while (nparams--) {
@ -3330,8 +3330,8 @@ int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_PARAMS_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_PARAMS_CMD_PFN(pf) |
FW_PARAMS_CMD_VFN(vf));
FW_CMD_WRITE_F | FW_PARAMS_CMD_PFN_V(pf) |
FW_PARAMS_CMD_VFN_V(vf));
c.retval_len16 = htonl(FW_LEN16(c));
while (nparams--) {
*p++ = htonl(*params++);
@ -3372,19 +3372,19 @@ int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_PFVF_CMD_PFN(pf) |
FW_PFVF_CMD_VFN(vf));
FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
FW_PFVF_CMD_VFN_V(vf));
c.retval_len16 = htonl(FW_LEN16(c));
c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) |
FW_PFVF_CMD_NIQ(rxq));
c.type_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) |
FW_PFVF_CMD_PMASK(pmask) |
FW_PFVF_CMD_NEQ(txq));
c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) |
FW_PFVF_CMD_NEXACTF(nexact));
c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS(rcaps) |
FW_PFVF_CMD_WX_CAPS(wxcaps) |
FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
FW_PFVF_CMD_NIQ_V(rxq));
c.type_to_neq = htonl(FW_PFVF_CMD_CMASK_V(cmask) |
FW_PFVF_CMD_PMASK_V(pmask) |
FW_PFVF_CMD_NEQ_V(txq));
c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC_V(tc) | FW_PFVF_CMD_NVI_V(vi) |
FW_PFVF_CMD_NEXACTF_V(nexact));
c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS_V(rcaps) |
FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
}
@ -3415,9 +3415,9 @@ int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_CMD_EXEC_F |
FW_VI_CMD_PFN(pf) | FW_VI_CMD_VFN(vf));
c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC | FW_LEN16(c));
c.portid_pkd = FW_VI_CMD_PORTID(port);
FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
c.portid_pkd = FW_VI_CMD_PORTID_V(port);
c.nmac = nmac - 1;
ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
@ -3438,8 +3438,8 @@ int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
}
}
if (rss_size)
*rss_size = FW_VI_CMD_RSSSIZE_GET(ntohs(c.rsssize_pkd));
return FW_VI_CMD_VIID_GET(ntohs(c.type_viid));
*rss_size = FW_VI_CMD_RSSSIZE_G(ntohs(c.rsssize_pkd));
return FW_VI_CMD_VIID_G(ntohs(c.type_viid));
}
/**
@ -3466,23 +3466,23 @@ int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
if (mtu < 0)
mtu = FW_RXMODE_MTU_NO_CHG;
if (promisc < 0)
promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK;
promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
if (all_multi < 0)
all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK;
all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
if (bcast < 0)
bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK;
bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
if (vlanex < 0)
vlanex = FW_VI_RXMODE_CMD_VLANEXEN_MASK;
vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
memset(&c, 0, sizeof(c));
c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_VI_RXMODE_CMD_VIID(viid));
FW_CMD_WRITE_F | FW_VI_RXMODE_CMD_VIID_V(viid));
c.retval_len16 = htonl(FW_LEN16(c));
c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU(mtu) |
FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU_V(mtu) |
FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
}
@ -3525,13 +3525,13 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
memset(&c, 0, sizeof(c));
c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_MAC_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | (free ? FW_CMD_EXEC_F : 0) |
FW_VI_MAC_CMD_VIID(viid));
c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS(free) |
FW_VI_MAC_CMD_VIID_V(viid));
c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS_V(free) |
FW_CMD_LEN16_V((naddr + 2) / 2));
for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID_F |
FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
memcpy(p->macaddr, addr[i], sizeof(p->macaddr));
}
@ -3540,7 +3540,7 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
return ret;
for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
u16 index = FW_VI_MAC_CMD_IDX_G(ntohs(p->valid_to_idx));
if (idx)
idx[i] = index >= max_naddr ? 0xffff : index;
@ -3587,16 +3587,16 @@ int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
memset(&c, 0, sizeof(c));
c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_MAC_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_VI_MAC_CMD_VIID(viid));
FW_CMD_WRITE_F | FW_VI_MAC_CMD_VIID_V(viid));
c.freemacs_to_len16 = htonl(FW_CMD_LEN16_V(1));
p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
FW_VI_MAC_CMD_SMAC_RESULT(mode) |
FW_VI_MAC_CMD_IDX(idx));
p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID_F |
FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
FW_VI_MAC_CMD_IDX_V(idx));
memcpy(p->macaddr, addr, sizeof(p->macaddr));
ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
if (ret == 0) {
ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
ret = FW_VI_MAC_CMD_IDX_G(ntohs(p->valid_to_idx));
if (ret >= max_mac_addr)
ret = -ENOMEM;
}
@ -3621,9 +3621,9 @@ int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
memset(&c, 0, sizeof(c));
c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_MAC_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE_F | FW_VI_ENABLE_CMD_VIID(viid));
c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN |
FW_VI_MAC_CMD_HASHUNIEN(ucast) |
FW_CMD_WRITE_F | FW_VI_ENABLE_CMD_VIID_V(viid));
c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN_F |
FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
FW_CMD_LEN16_V(1));
c.u.hash.hashvec = cpu_to_be64(vec);
return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
@ -3648,11 +3648,11 @@ int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
memset(&c, 0, sizeof(c));
c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST_F |
FW_CMD_EXEC_F | FW_VI_ENABLE_CMD_VIID(viid));
FW_CMD_EXEC_F | FW_VI_ENABLE_CMD_VIID_V(viid));
c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN(rx_en) |
FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c) |
FW_VI_ENABLE_CMD_DCB_INFO(dcb_en));
c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
FW_VI_ENABLE_CMD_EEN_V(tx_en) | FW_LEN16(c) |
FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en));
return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
}
@ -3688,8 +3688,8 @@ int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
memset(&c, 0, sizeof(c));
c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST_F |
FW_CMD_EXEC_F | FW_VI_ENABLE_CMD_VIID(viid));
c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
FW_CMD_EXEC_F | FW_VI_ENABLE_CMD_VIID_V(viid));
c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
c.blinkdur = htons(nblinks);
return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
}
@ -3715,10 +3715,10 @@ int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
FW_CMD_EXEC_F | FW_IQ_CMD_PFN(pf) |
FW_IQ_CMD_VFN(vf));
c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE | FW_LEN16(c));
c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iqtype));
FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
FW_IQ_CMD_VFN_V(vf));
c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE_F | FW_LEN16(c));
c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(iqtype));
c.iqid = htons(iqid);
c.fl0id = htons(fl0id);
c.fl1id = htons(fl1id);
@ -3742,10 +3742,10 @@ int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F |
FW_CMD_EXEC_F | FW_EQ_ETH_CMD_PFN(pf) |
FW_EQ_ETH_CMD_VFN(vf));
c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID(eqid));
FW_CMD_EXEC_F | FW_EQ_ETH_CMD_PFN_V(pf) |
FW_EQ_ETH_CMD_VFN_V(vf));
c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID_V(eqid));
return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
}
@ -3766,10 +3766,10 @@ int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F |
FW_CMD_EXEC_F | FW_EQ_CTRL_CMD_PFN(pf) |
FW_EQ_CTRL_CMD_VFN(vf));
c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID(eqid));
FW_CMD_EXEC_F | FW_EQ_CTRL_CMD_PFN_V(pf) |
FW_EQ_CTRL_CMD_VFN_V(vf));
c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID_V(eqid));
return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
}
@ -3790,10 +3790,10 @@ int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F |
FW_CMD_EXEC_F | FW_EQ_OFLD_CMD_PFN(pf) |
FW_EQ_OFLD_CMD_VFN(vf));
c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eqid));
FW_CMD_EXEC_F | FW_EQ_OFLD_CMD_PFN_V(pf) |
FW_EQ_OFLD_CMD_VFN_V(vf));
c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID_V(eqid));
return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
}
@ -3811,25 +3811,25 @@ int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
if (opcode == FW_PORT_CMD) { /* link/module state change message */
int speed = 0, fc = 0;
const struct fw_port_cmd *p = (void *)rpl;
int chan = FW_PORT_CMD_PORTID_GET(ntohl(p->op_to_portid));
int chan = FW_PORT_CMD_PORTID_G(ntohl(p->op_to_portid));
int port = adap->chan_map[chan];
struct port_info *pi = adap2pinfo(adap, port);
struct link_config *lc = &pi->link_cfg;
u32 stat = ntohl(p->u.info.lstatus_to_modtype);
int link_ok = (stat & FW_PORT_CMD_LSTATUS) != 0;
u32 mod = FW_PORT_CMD_MODTYPE_GET(stat);
int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
if (stat & FW_PORT_CMD_RXPAUSE)
if (stat & FW_PORT_CMD_RXPAUSE_F)
fc |= PAUSE_RX;
if (stat & FW_PORT_CMD_TXPAUSE)
if (stat & FW_PORT_CMD_TXPAUSE_F)
fc |= PAUSE_TX;
if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
speed = 100;
else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
speed = 1000;
else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
speed = 10000;
else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
speed = 40000;
if (link_ok != lc->link_ok || speed != lc->speed ||
@ -4124,9 +4124,9 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
c.op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) |
FW_CMD_REQUEST_F | FW_CMD_READ_F |
FW_PORT_CMD_PORTID(j));
FW_PORT_CMD_PORTID_V(j));
c.action_to_len16 = htonl(
FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
FW_LEN16(c));
ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
if (ret)
@ -4144,9 +4144,9 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
adap->port[i]->dev_port = j;
ret = ntohl(c.u.info.lstatus_to_modtype);
p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP) ?
FW_PORT_CMD_MDIOADDR_GET(ret) : -1;
p->port_type = FW_PORT_CMD_PTYPE_GET(ret);
p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
FW_PORT_CMD_MDIOADDR_G(ret) : -1;
p->port_type = FW_PORT_CMD_PTYPE_G(ret);
p->mod_type = FW_PORT_MOD_TYPE_NA;
rvc.op_to_viid = htonl(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |

1963
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
View File

File diff suppressed because it is too large Load Diff

26
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
View File

@ -1030,10 +1030,10 @@ static int set_rxq_intr_params(struct adapter *adapter, struct sge_rspq *rspq,
pktcnt_idx = closest_thres(&adapter->sge, cnt);
if (rspq->desc && rspq->pktcnt_idx != pktcnt_idx) {
v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
FW_PARAMS_PARAM_X(
v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
FW_PARAMS_PARAM_X_V(
FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
FW_PARAMS_PARAM_YZ(rspq->cntxt_id);
FW_PARAMS_PARAM_YZ_V(rspq->cntxt_id);
err = t4vf_set_params(adapter, 1, &v, &pktcnt_idx);
if (err)
return err;
@ -1230,14 +1230,14 @@ static void cxgb4vf_get_drvinfo(struct net_device *dev,
sizeof(drvinfo->bus_info));
snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
"%u.%u.%u.%u, TP %u.%u.%u.%u",
FW_HDR_FW_VER_MAJOR_GET(adapter->params.dev.fwrev),
FW_HDR_FW_VER_MINOR_GET(adapter->params.dev.fwrev),
FW_HDR_FW_VER_MICRO_GET(adapter->params.dev.fwrev),
FW_HDR_FW_VER_BUILD_GET(adapter->params.dev.fwrev),
FW_HDR_FW_VER_MAJOR_GET(adapter->params.dev.tprev),
FW_HDR_FW_VER_MINOR_GET(adapter->params.dev.tprev),
FW_HDR_FW_VER_MICRO_GET(adapter->params.dev.tprev),
FW_HDR_FW_VER_BUILD_GET(adapter->params.dev.tprev));
FW_HDR_FW_VER_MAJOR_G(adapter->params.dev.fwrev),
FW_HDR_FW_VER_MINOR_G(adapter->params.dev.fwrev),
FW_HDR_FW_VER_MICRO_G(adapter->params.dev.fwrev),
FW_HDR_FW_VER_BUILD_G(adapter->params.dev.fwrev),
FW_HDR_FW_VER_MAJOR_G(adapter->params.dev.tprev),
FW_HDR_FW_VER_MINOR_G(adapter->params.dev.tprev),
FW_HDR_FW_VER_MICRO_G(adapter->params.dev.tprev),
FW_HDR_FW_VER_BUILD_G(adapter->params.dev.tprev));
}
/*
@ -2184,8 +2184,8 @@ static int adap_init0(struct adapter *adapter)
* firmware won't understand this and we'll just get
* unencapsulated messages ...
*/
param = FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP);
param = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP);
val = 1;
(void) t4vf_set_params(adapter, 1, &param, &val);

63
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
View File

@ -2092,22 +2092,22 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
FW_CMD_REQUEST_F |
FW_CMD_WRITE_F |
FW_CMD_EXEC_F);
cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_ALLOC |
FW_IQ_CMD_IQSTART(1) |
cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_ALLOC_F |
FW_IQ_CMD_IQSTART_F |
FW_LEN16(cmd));
cmd.type_to_iqandstindex =
cpu_to_be32(FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
FW_IQ_CMD_IQASYNCH(iqasynch) |
FW_IQ_CMD_VIID(pi->viid) |
FW_IQ_CMD_IQANDST(iqandst) |
FW_IQ_CMD_IQANUS(1) |
FW_IQ_CMD_IQANUD(SGE_UPDATEDEL_INTR) |
FW_IQ_CMD_IQANDSTINDEX(intr_dest));
cpu_to_be32(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) |
FW_IQ_CMD_IQASYNCH_V(iqasynch) |
FW_IQ_CMD_VIID_V(pi->viid) |
FW_IQ_CMD_IQANDST_V(iqandst) |
FW_IQ_CMD_IQANUS_V(1) |
FW_IQ_CMD_IQANUD_V(SGE_UPDATEDEL_INTR) |
FW_IQ_CMD_IQANDSTINDEX_V(intr_dest));
cmd.iqdroprss_to_iqesize =
cpu_to_be16(FW_IQ_CMD_IQPCIECH(pi->port_id) |
FW_IQ_CMD_IQGTSMODE |
FW_IQ_CMD_IQINTCNTTHRESH(rspq->pktcnt_idx) |
FW_IQ_CMD_IQESIZE(ilog2(rspq->iqe_len) - 4));
cpu_to_be16(FW_IQ_CMD_IQPCIECH_V(pi->port_id) |
FW_IQ_CMD_IQGTSMODE_F |
FW_IQ_CMD_IQINTCNTTHRESH_V(rspq->pktcnt_idx) |
FW_IQ_CMD_IQESIZE_V(ilog2(rspq->iqe_len) - 4));
cmd.iqsize = cpu_to_be16(rspq->size);
cmd.iqaddr = cpu_to_be64(rspq->phys_addr);
@ -2141,13 +2141,13 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
*/
cmd.iqns_to_fl0congen =
cpu_to_be32(
FW_IQ_CMD_FL0HOSTFCMODE(SGE_HOSTFCMODE_NONE) |
FW_IQ_CMD_FL0PACKEN(1) |
FW_IQ_CMD_FL0PADEN(1));
FW_IQ_CMD_FL0HOSTFCMODE_V(SGE_HOSTFCMODE_NONE) |
FW_IQ_CMD_FL0PACKEN_F |
FW_IQ_CMD_FL0PADEN_F);
cmd.fl0dcaen_to_fl0cidxfthresh =
cpu_to_be16(
FW_IQ_CMD_FL0FBMIN(SGE_FETCHBURSTMIN_64B) |
FW_IQ_CMD_FL0FBMAX(SGE_FETCHBURSTMAX_512B));
FW_IQ_CMD_FL0FBMIN_V(SGE_FETCHBURSTMIN_64B) |
FW_IQ_CMD_FL0FBMAX_V(SGE_FETCHBURSTMAX_512B));
cmd.fl0size = cpu_to_be16(flsz);
cmd.fl0addr = cpu_to_be64(fl->addr);
}
@ -2255,20 +2255,21 @@ int t4vf_sge_alloc_eth_txq(struct adapter *adapter, struct sge_eth_txq *txq,
FW_CMD_REQUEST_F |
FW_CMD_WRITE_F |
FW_CMD_EXEC_F);
cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_ALLOC |
FW_EQ_ETH_CMD_EQSTART |
cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_ALLOC_F |
FW_EQ_ETH_CMD_EQSTART_F |
FW_LEN16(cmd));
cmd.viid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_AUTOEQUEQE |
FW_EQ_ETH_CMD_VIID(pi->viid));
cmd.viid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_AUTOEQUEQE_F |
FW_EQ_ETH_CMD_VIID_V(pi->viid));
cmd.fetchszm_to_iqid =
cpu_to_be32(FW_EQ_ETH_CMD_HOSTFCMODE(SGE_HOSTFCMODE_STPG) |
FW_EQ_ETH_CMD_PCIECHN(pi->port_id) |
FW_EQ_ETH_CMD_IQID(iqid));
cpu_to_be32(FW_EQ_ETH_CMD_HOSTFCMODE_V(SGE_HOSTFCMODE_STPG) |
FW_EQ_ETH_CMD_PCIECHN_V(pi->port_id) |
FW_EQ_ETH_CMD_IQID_V(iqid));
cmd.dcaen_to_eqsize =
cpu_to_be32(FW_EQ_ETH_CMD_FBMIN(SGE_FETCHBURSTMIN_64B) |
FW_EQ_ETH_CMD_FBMAX(SGE_FETCHBURSTMAX_512B) |
FW_EQ_ETH_CMD_CIDXFTHRESH(SGE_CIDXFLUSHTHRESH_32) |
FW_EQ_ETH_CMD_EQSIZE(nentries));
cpu_to_be32(FW_EQ_ETH_CMD_FBMIN_V(SGE_FETCHBURSTMIN_64B) |
FW_EQ_ETH_CMD_FBMAX_V(SGE_FETCHBURSTMAX_512B) |
FW_EQ_ETH_CMD_CIDXFTHRESH_V(
SGE_CIDXFLUSHTHRESH_32) |
FW_EQ_ETH_CMD_EQSIZE_V(nentries));
cmd.eqaddr = cpu_to_be64(txq->q.phys_addr);
/*
@ -2294,9 +2295,9 @@ int t4vf_sge_alloc_eth_txq(struct adapter *adapter, struct sge_eth_txq *txq,
txq->q.cidx = 0;
txq->q.pidx = 0;
txq->q.stat = (void *)&txq->q.desc[txq->q.size];
txq->q.cntxt_id = FW_EQ_ETH_CMD_EQID_GET(be32_to_cpu(rpl.eqid_pkd));
txq->q.cntxt_id = FW_EQ_ETH_CMD_EQID_G(be32_to_cpu(rpl.eqid_pkd));
txq->q.abs_id =
FW_EQ_ETH_CMD_PHYSEQID_GET(be32_to_cpu(rpl.physeqid_pkd));
FW_EQ_ETH_CMD_PHYSEQID_G(be32_to_cpu(rpl.physeqid_pkd));
txq->txq = devq;
txq->tso = 0;
txq->tx_cso = 0;

232
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
View File

@ -291,13 +291,13 @@ int t4vf_port_init(struct adapter *adapter, int pidx)
FW_CMD_REQUEST_F |
FW_CMD_READ_F);
vi_cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(vi_cmd));
vi_cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID(pi->viid));
vi_cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(pi->viid));
v = t4vf_wr_mbox(adapter, &vi_cmd, sizeof(vi_cmd), &vi_rpl);
if (v)
return v;
BUG_ON(pi->port_id != FW_VI_CMD_PORTID_GET(vi_rpl.portid_pkd));
pi->rss_size = FW_VI_CMD_RSSSIZE_GET(be16_to_cpu(vi_rpl.rsssize_pkd));
BUG_ON(pi->port_id != FW_VI_CMD_PORTID_G(vi_rpl.portid_pkd));
pi->rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(vi_rpl.rsssize_pkd));
t4_os_set_hw_addr(adapter, pidx, vi_rpl.mac);
/*
@ -311,9 +311,9 @@ int t4vf_port_init(struct adapter *adapter, int pidx)
port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_READ_F |
FW_PORT_CMD_PORTID(pi->port_id));
FW_PORT_CMD_PORTID_V(pi->port_id));
port_cmd.action_to_len16 =
cpu_to_be32(FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
FW_LEN16(port_cmd));
v = t4vf_wr_mbox(adapter, &port_cmd, sizeof(port_cmd), &port_rpl);
if (v)
@ -443,20 +443,20 @@ int t4vf_get_sge_params(struct adapter *adapter)
u32 params[7], vals[7];
int v;
params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ(SGE_CONTROL));
params[1] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ(SGE_HOST_PAGE_SIZE));
params[2] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ(SGE_FL_BUFFER_SIZE0));
params[3] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ(SGE_FL_BUFFER_SIZE1));
params[4] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ(SGE_TIMER_VALUE_0_AND_1));
params[5] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ(SGE_TIMER_VALUE_2_AND_3));
params[6] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ(SGE_TIMER_VALUE_4_AND_5));
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_CONTROL));
params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_HOST_PAGE_SIZE));
params[2] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE0));
params[3] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE1));
params[4] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_0_AND_1));
params[5] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_2_AND_3));
params[6] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_4_AND_5));
v = t4vf_query_params(adapter, 7, params, vals);
if (v)
return v;
@ -479,8 +479,8 @@ int t4vf_get_sge_params(struct adapter *adapter)
* right value.
*/
if (!is_t4(adapter->params.chip)) {
params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ(SGE_CONTROL2_A));
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_CONTROL2_A));
v = t4vf_query_params(adapter, 1, params, vals);
if (v != FW_SUCCESS) {
dev_err(adapter->pdev_dev,
@ -491,10 +491,10 @@ int t4vf_get_sge_params(struct adapter *adapter)
sge_params->sge_control2 = vals[0];
}
params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ(SGE_INGRESS_RX_THRESHOLD));
params[1] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ(SGE_CONM_CTRL));
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_INGRESS_RX_THRESHOLD));
params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_CONM_CTRL));
v = t4vf_query_params(adapter, 2, params, vals);
if (v)
return v;
@ -517,8 +517,8 @@ int t4vf_get_vpd_params(struct adapter *adapter)
u32 params[7], vals[7];
int v;
params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
v = t4vf_query_params(adapter, 1, params, vals);
if (v)
return v;
@ -540,10 +540,10 @@ int t4vf_get_dev_params(struct adapter *adapter)
u32 params[7], vals[7];
int v;
params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWREV));
params[1] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPREV));
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWREV));
params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPREV));
v = t4vf_query_params(adapter, 2, params, vals);
if (v)
return v;
@ -585,7 +585,7 @@ int t4vf_get_rss_glb_config(struct adapter *adapter)
* filtering at this point to weed out modes which don't support
* VF Drivers ...
*/
rss->mode = FW_RSS_GLB_CONFIG_CMD_MODE_GET(
rss->mode = FW_RSS_GLB_CONFIG_CMD_MODE_G(
be32_to_cpu(rpl.u.manual.mode_pkd));
switch (rss->mode) {
case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
@ -593,26 +593,26 @@ int t4vf_get_rss_glb_config(struct adapter *adapter)
rpl.u.basicvirtual.synmapen_to_hashtoeplitz);
rss->u.basicvirtual.synmapen =
((word & FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) != 0);
((word & FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F) != 0);
rss->u.basicvirtual.syn4tupenipv6 =
((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) != 0);
((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F) != 0);
rss->u.basicvirtual.syn2tupenipv6 =
((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) != 0);
((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F) != 0);
rss->u.basicvirtual.syn4tupenipv4 =
((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) != 0);
((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F) != 0);
rss->u.basicvirtual.syn2tupenipv4 =
((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) != 0);
((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F) != 0);
rss->u.basicvirtual.ofdmapen =
((word & FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) != 0);
((word & FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F) != 0);
rss->u.basicvirtual.tnlmapen =
((word & FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) != 0);
((word & FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F) != 0);
rss->u.basicvirtual.tnlalllookup =
((word & FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) != 0);
((word & FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F) != 0);
rss->u.basicvirtual.hashtoeplitz =
((word & FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) != 0);
((word & FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F) != 0);
/* we need at least Tunnel Map Enable to be set */
if (!rss->u.basicvirtual.tnlmapen)
@ -659,22 +659,22 @@ int t4vf_get_vfres(struct adapter *adapter)
* Extract VF resource limits and return success.
*/
word = be32_to_cpu(rpl.niqflint_niq);
vfres->niqflint = FW_PFVF_CMD_NIQFLINT_GET(word);
vfres->niq = FW_PFVF_CMD_NIQ_GET(word);
vfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
vfres->niq = FW_PFVF_CMD_NIQ_G(word);
word = be32_to_cpu(rpl.type_to_neq);
vfres->neq = FW_PFVF_CMD_NEQ_GET(word);
vfres->pmask = FW_PFVF_CMD_PMASK_GET(word);
vfres->neq = FW_PFVF_CMD_NEQ_G(word);
vfres->pmask = FW_PFVF_CMD_PMASK_G(word);
word = be32_to_cpu(rpl.tc_to_nexactf);
vfres->tc = FW_PFVF_CMD_TC_GET(word);
vfres->nvi = FW_PFVF_CMD_NVI_GET(word);
vfres->nexactf = FW_PFVF_CMD_NEXACTF_GET(word);
vfres->tc = FW_PFVF_CMD_TC_G(word);
vfres->nvi = FW_PFVF_CMD_NVI_G(word);
vfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
word = be32_to_cpu(rpl.r_caps_to_nethctrl);
vfres->r_caps = FW_PFVF_CMD_R_CAPS_GET(word);
vfres->wx_caps = FW_PFVF_CMD_WX_CAPS_GET(word);
vfres->nethctrl = FW_PFVF_CMD_NETHCTRL_GET(word);
vfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
vfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
vfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
return 0;
}
@ -709,17 +709,17 @@ int t4vf_read_rss_vi_config(struct adapter *adapter, unsigned int viid,
u32 word = be32_to_cpu(rpl.u.basicvirtual.defaultq_to_udpen);
config->basicvirtual.ip6fourtupen =
((word & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) != 0);
((word & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) != 0);
config->basicvirtual.ip6twotupen =
((word & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) != 0);
((word & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F) != 0);
config->basicvirtual.ip4fourtupen =
((word & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) != 0);
((word & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) != 0);
config->basicvirtual.ip4twotupen =
((word & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) != 0);
((word & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F) != 0);
config->basicvirtual.udpen =
((word & FW_RSS_VI_CONFIG_CMD_UDPEN) != 0);
((word & FW_RSS_VI_CONFIG_CMD_UDPEN_F) != 0);
config->basicvirtual.defaultq =
FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(word);
FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(word);
break;
}
@ -755,16 +755,16 @@ int t4vf_write_rss_vi_config(struct adapter *adapter, unsigned int viid,
u32 word = 0;
if (config->basicvirtual.ip6fourtupen)
word |= FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
word |= FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F;
if (config->basicvirtual.ip6twotupen)
word |= FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
word |= FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F;
if (config->basicvirtual.ip4fourtupen)
word |= FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
word |= FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F;
if (config->basicvirtual.ip4twotupen)
word |= FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
word |= FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F;
if (config->basicvirtual.udpen)
word |= FW_RSS_VI_CONFIG_CMD_UDPEN;
word |= FW_RSS_VI_CONFIG_CMD_DEFAULTQ(
word |= FW_RSS_VI_CONFIG_CMD_UDPEN_F;
word |= FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(
config->basicvirtual.defaultq);
cmd.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(word);
break;
@ -806,7 +806,7 @@ int t4vf_config_rss_range(struct adapter *adapter, unsigned int viid,
cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_WRITE_F |
FW_RSS_IND_TBL_CMD_VIID(viid));
FW_RSS_IND_TBL_CMD_VIID_V(viid));
cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
/*
@ -857,9 +857,9 @@ int t4vf_config_rss_range(struct adapter *adapter, unsigned int viid,
if (rsp >= rsp_end)
rsp = rspq;
}
*qp++ = cpu_to_be32(FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
*qp++ = cpu_to_be32(FW_RSS_IND_TBL_CMD_IQ0_V(qbuf[0]) |
FW_RSS_IND_TBL_CMD_IQ1_V(qbuf[1]) |
FW_RSS_IND_TBL_CMD_IQ2_V(qbuf[2]));
}
/*
@ -897,13 +897,13 @@ int t4vf_alloc_vi(struct adapter *adapter, int port_id)
FW_CMD_WRITE_F |
FW_CMD_EXEC_F);
cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
FW_VI_CMD_ALLOC);
cmd.portid_pkd = FW_VI_CMD_PORTID(port_id);
FW_VI_CMD_ALLOC_F);
cmd.portid_pkd = FW_VI_CMD_PORTID_V(port_id);
v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
if (v)
return v;
return FW_VI_CMD_VIID_GET(be16_to_cpu(rpl.type_viid));
return FW_VI_CMD_VIID_G(be16_to_cpu(rpl.type_viid));
}
/**
@ -926,8 +926,8 @@ int t4vf_free_vi(struct adapter *adapter, int viid)
FW_CMD_REQUEST_F |
FW_CMD_EXEC_F);
cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
FW_VI_CMD_FREE);
cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID(viid));
FW_VI_CMD_FREE_F);
cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
}
@ -949,9 +949,9 @@ int t4vf_enable_vi(struct adapter *adapter, unsigned int viid,
cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_EXEC_F |
FW_VI_ENABLE_CMD_VIID(viid));
cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN(rx_en) |
FW_VI_ENABLE_CMD_EEN(tx_en) |
FW_VI_ENABLE_CMD_VIID_V(viid));
cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
FW_VI_ENABLE_CMD_EEN_V(tx_en) |
FW_LEN16(cmd));
return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
}
@ -973,8 +973,8 @@ int t4vf_identify_port(struct adapter *adapter, unsigned int viid,
cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_EXEC_F |
FW_VI_ENABLE_CMD_VIID(viid));
cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED |
FW_VI_ENABLE_CMD_VIID_V(viid));
cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F |
FW_LEN16(cmd));
cmd.blinkdur = cpu_to_be16(nblinks);
return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
@ -1001,28 +1001,28 @@ int t4vf_set_rxmode(struct adapter *adapter, unsigned int viid,
/* convert to FW values */
if (mtu < 0)
mtu = FW_VI_RXMODE_CMD_MTU_MASK;
mtu = FW_VI_RXMODE_CMD_MTU_M;
if (promisc < 0)
promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK;
promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
if (all_multi < 0)
all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK;
all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
if (bcast < 0)
bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK;
bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
if (vlanex < 0)
vlanex = FW_VI_RXMODE_CMD_VLANEXEN_MASK;
vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
memset(&cmd, 0, sizeof(cmd));
cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_WRITE_F |
FW_VI_RXMODE_CMD_VIID(viid));
FW_VI_RXMODE_CMD_VIID_V(viid));
cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
cmd.mtu_to_vlanexen =
cpu_to_be32(FW_VI_RXMODE_CMD_MTU(mtu) |
FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
return t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), NULL, sleep_ok);
}
@ -1076,15 +1076,15 @@ int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
FW_CMD_REQUEST_F |
FW_CMD_WRITE_F |
(free ? FW_CMD_EXEC_F : 0) |
FW_VI_MAC_CMD_VIID(viid));
FW_VI_MAC_CMD_VIID_V(viid));
cmd.freemacs_to_len16 =
cpu_to_be32(FW_VI_MAC_CMD_FREEMACS(free) |
cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
FW_CMD_LEN16_V(len16));
for (i = 0, p = cmd.u.exact; i < fw_naddr; i++, p++) {
p->valid_to_idx = cpu_to_be16(
FW_VI_MAC_CMD_VALID |
FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
FW_VI_MAC_CMD_VALID_F |
FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
}
@ -1095,7 +1095,7 @@ int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
break;
for (i = 0, p = rpl.u.exact; i < fw_naddr; i++, p++) {
u16 index = FW_VI_MAC_CMD_IDX_GET(
u16 index = FW_VI_MAC_CMD_IDX_G(
be16_to_cpu(p->valid_to_idx));
if (idx)
@ -1164,16 +1164,16 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_WRITE_F |
FW_VI_MAC_CMD_VIID(viid));
FW_VI_MAC_CMD_VIID_V(viid));
cmd.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID |
FW_VI_MAC_CMD_IDX(idx));
p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
FW_VI_MAC_CMD_IDX_V(idx));
memcpy(p->macaddr, addr, sizeof(p->macaddr));
ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
if (ret == 0) {
p = &rpl.u.exact[0];
ret = FW_VI_MAC_CMD_IDX_GET(be16_to_cpu(p->valid_to_idx));
ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
if (ret >= max_naddr)
ret = -ENOMEM;
}
@ -1201,9 +1201,9 @@ int t4vf_set_addr_hash(struct adapter *adapter, unsigned int viid,
cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_WRITE_F |
FW_VI_ENABLE_CMD_VIID(viid));
cmd.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN |
FW_VI_MAC_CMD_HASHUNIEN(ucast) |
FW_VI_ENABLE_CMD_VIID_V(viid));
cmd.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
FW_CMD_LEN16_V(len16));
cmd.u.hash.hashvec = cpu_to_be64(vec);
return t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), NULL, sleep_ok);
@ -1241,13 +1241,13 @@ int t4vf_get_port_stats(struct adapter *adapter, int pidx,
memset(&cmd, 0, sizeof(cmd));
cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_STATS_CMD) |
FW_VI_STATS_CMD_VIID(pi->viid) |
FW_VI_STATS_CMD_VIID_V(pi->viid) |
FW_CMD_REQUEST_F |
FW_CMD_READ_F);
cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
cmd.u.ctl.nstats_ix =
cpu_to_be16(FW_VI_STATS_CMD_IX(ix) |
FW_VI_STATS_CMD_NSTATS(nstats));
cpu_to_be16(FW_VI_STATS_CMD_IX_V(ix) |
FW_VI_STATS_CMD_NSTATS_V(nstats));
ret = t4vf_wr_mbox_ns(adapter, &cmd, len, &rpl);
if (ret)
return ret;
@ -1302,10 +1302,10 @@ int t4vf_iq_free(struct adapter *adapter, unsigned int iqtype,
cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_EXEC_F);
cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE |
cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F |
FW_LEN16(cmd));
cmd.type_to_iqandstindex =
cpu_to_be32(FW_IQ_CMD_TYPE(iqtype));
cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
cmd.iqid = cpu_to_be16(iqid);
cmd.fl0id = cpu_to_be16(fl0id);
@ -1328,9 +1328,9 @@ int t4vf_eth_eq_free(struct adapter *adapter, unsigned int eqid)
cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_EXEC_F);
cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE |
cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F |
FW_LEN16(cmd));
cmd.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID(eqid));
cmd.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
}
@ -1359,7 +1359,7 @@ int t4vf_handle_fw_rpl(struct adapter *adapter, const __be64 *rpl)
/*
* Extract various fields from port status change message.
*/
action = FW_PORT_CMD_ACTION_GET(
action = FW_PORT_CMD_ACTION_G(
be32_to_cpu(port_cmd->action_to_len16));
if (action != FW_PORT_ACTION_GET_PORT_INFO) {
dev_err(adapter->pdev_dev,
@ -1368,24 +1368,24 @@ int t4vf_handle_fw_rpl(struct adapter *adapter, const __be64 *rpl)
break;
}
port_id = FW_PORT_CMD_PORTID_GET(
port_id = FW_PORT_CMD_PORTID_G(
be32_to_cpu(port_cmd->op_to_portid));
word = be32_to_cpu(port_cmd->u.info.lstatus_to_modtype);
link_ok = (word & FW_PORT_CMD_LSTATUS) != 0;
link_ok = (word & FW_PORT_CMD_LSTATUS_F) != 0;
speed = 0;
fc = 0;
if (word & FW_PORT_CMD_RXPAUSE)
if (word & FW_PORT_CMD_RXPAUSE_F)
fc |= PAUSE_RX;
if (word & FW_PORT_CMD_TXPAUSE)
if (word & FW_PORT_CMD_TXPAUSE_F)
fc |= PAUSE_TX;
if (word & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
if (word & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
speed = 100;
else if (word & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
else if (word & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
speed = 1000;
else if (word & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
else if (word & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
speed = 10000;
else if (word & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
else if (word & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
speed = 40000;
/*

38
drivers/scsi/csiostor/csio_hw.c
View File

@ -650,10 +650,10 @@ static void
csio_hw_print_fw_version(struct csio_hw *hw, char *str)
{
csio_info(hw, "%s: %u.%u.%u.%u\n", str,
FW_HDR_FW_VER_MAJOR_GET(hw->fwrev),
FW_HDR_FW_VER_MINOR_GET(hw->fwrev),
FW_HDR_FW_VER_MICRO_GET(hw->fwrev),
FW_HDR_FW_VER_BUILD_GET(hw->fwrev));
FW_HDR_FW_VER_MAJOR_G(hw->fwrev),
FW_HDR_FW_VER_MINOR_G(hw->fwrev),
FW_HDR_FW_VER_MICRO_G(hw->fwrev),
FW_HDR_FW_VER_BUILD_G(hw->fwrev));
}
/*
@ -706,9 +706,9 @@ csio_hw_check_fw_version(struct csio_hw *hw)
if (ret)
return ret;
major = FW_HDR_FW_VER_MAJOR_GET(hw->fwrev);
minor = FW_HDR_FW_VER_MINOR_GET(hw->fwrev);
micro = FW_HDR_FW_VER_MICRO_GET(hw->fwrev);
major = FW_HDR_FW_VER_MAJOR_G(hw->fwrev);
minor = FW_HDR_FW_VER_MINOR_G(hw->fwrev);
micro = FW_HDR_FW_VER_MICRO_G(hw->fwrev);
if (major != FW_VERSION_MAJOR(hw)) { /* major mismatch - fail */
csio_err(hw, "card FW has major version %u, driver wants %u\n",
@ -1170,7 +1170,7 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
}
csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
PIORSTMODE | PIORST, FW_RESET_CMD_HALT(1),
PIORSTMODE | PIORST, FW_RESET_CMD_HALT_F,
NULL);
if (csio_mb_issue(hw, mbp)) {
@ -1374,9 +1374,9 @@ csio_hw_fw_config_file(struct csio_hw *hw,
FW_CMD_REQUEST_F |
FW_CMD_READ_F);
caps_cmd->cfvalid_to_len16 =
htonl(FW_CAPS_CONFIG_CMD_CFVALID |
FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
FW_LEN16(*caps_cmd));
if (csio_mb_issue(hw, mbp)) {
@ -1723,8 +1723,8 @@ csio_hw_check_fwconfig(struct csio_hw *hw, u32 *param)
* Find out whether we're dealing with a version of
* the firmware which has configuration file support.
*/
_param[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
_param[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0,
ARRAY_SIZE(_param), _param, NULL, false, NULL);
@ -1781,8 +1781,8 @@ csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path)
goto leave;
}
mtype = FW_PARAMS_PARAM_Y_GET(*fw_cfg_param);
maddr = FW_PARAMS_PARAM_Z_GET(*fw_cfg_param) << 16;
mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param);
maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16;
ret = csio_memory_write(hw, mtype, maddr,
cf->size + value_to_add, cfg_data);
@ -1871,8 +1871,8 @@ csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param)
goto bye;
}
} else {
mtype = FW_PARAMS_PARAM_Y_GET(*fw_cfg_param);
maddr = FW_PARAMS_PARAM_Z_GET(*fw_cfg_param) << 16;
mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param);
maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16;
using_flash = 0;
}
@ -1998,13 +1998,13 @@ csio_hw_flash_fw(struct csio_hw *hw)
hdr = (const struct fw_hdr *)fw->data;
fw_ver = ntohl(hdr->fw_ver);
if (FW_HDR_FW_VER_MAJOR_GET(fw_ver) != FW_VERSION_MAJOR(hw))
if (FW_HDR_FW_VER_MAJOR_G(fw_ver) != FW_VERSION_MAJOR(hw))
return -EINVAL; /* wrong major version, won't do */
/*
* If the flash FW is unusable or we found something newer, load it.
*/
if (FW_HDR_FW_VER_MAJOR_GET(hw->fwrev) != FW_VERSION_MAJOR(hw) ||
if (FW_HDR_FW_VER_MAJOR_G(hw->fwrev) != FW_VERSION_MAJOR(hw) ||
fw_ver > hw->fwrev) {
ret = csio_hw_fw_upgrade(hw, hw->pfn, fw->data, fw->size,
/*force=*/false);

8
drivers/scsi/csiostor/csio_init.c
View File

@ -974,10 +974,10 @@ static int csio_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
}
sprintf(hw->fwrev_str, "%u.%u.%u.%u\n",
FW_HDR_FW_VER_MAJOR_GET(hw->fwrev),
FW_HDR_FW_VER_MINOR_GET(hw->fwrev),
FW_HDR_FW_VER_MICRO_GET(hw->fwrev),
FW_HDR_FW_VER_BUILD_GET(hw->fwrev));
FW_HDR_FW_VER_MAJOR_G(hw->fwrev),
FW_HDR_FW_VER_MINOR_G(hw->fwrev),
FW_HDR_FW_VER_MICRO_G(hw->fwrev),
FW_HDR_FW_VER_BUILD_G(hw->fwrev));
for (i = 0; i < hw->num_pports; i++) {
ln = csio_shost_init(hw, &pdev->dev, true, NULL);

171
drivers/scsi/csiostor/csio_mb.c
View File

@ -85,13 +85,13 @@ csio_mb_hello(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo,
FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16));
cmdp->err_to_clearinit = htonl(
FW_HELLO_CMD_MASTERDIS(master == CSIO_MASTER_CANT) |
FW_HELLO_CMD_MASTERFORCE(master == CSIO_MASTER_MUST) |
FW_HELLO_CMD_MBMASTER(master == CSIO_MASTER_MUST ?
m_mbox : FW_HELLO_CMD_MBMASTER_MASK) |
FW_HELLO_CMD_MBASYNCNOT(a_mbox) |
FW_HELLO_CMD_STAGE(fw_hello_cmd_stage_os) |
FW_HELLO_CMD_CLEARINIT);
FW_HELLO_CMD_MASTERDIS_V(master == CSIO_MASTER_CANT) |
FW_HELLO_CMD_MASTERFORCE_V(master == CSIO_MASTER_MUST) |
FW_HELLO_CMD_MBMASTER_V(master == CSIO_MASTER_MUST ?
m_mbox : FW_HELLO_CMD_MBMASTER_M) |
FW_HELLO_CMD_MBASYNCNOT_V(a_mbox) |
FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
FW_HELLO_CMD_CLEARINIT_F);
}
@ -118,11 +118,11 @@ csio_mb_process_hello_rsp(struct csio_hw *hw, struct csio_mb *mbp,
hw->fwrev = ntohl(rsp->fwrev);
value = ntohl(rsp->err_to_clearinit);
*mpfn = FW_HELLO_CMD_MBMASTER_GET(value);
*mpfn = FW_HELLO_CMD_MBMASTER_G(value);
if (value & FW_HELLO_CMD_INIT)
if (value & FW_HELLO_CMD_INIT_F)
*state = CSIO_DEV_STATE_INIT;
else if (value & FW_HELLO_CMD_ERR)
else if (value & FW_HELLO_CMD_ERR_F)
*state = CSIO_DEV_STATE_ERR;
else
*state = CSIO_DEV_STATE_UNINIT;
@ -205,8 +205,8 @@ csio_mb_params(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo,
cmdp->op_to_vfn = htonl(FW_CMD_OP_V(FW_PARAMS_CMD) |
FW_CMD_REQUEST_F |
(wr ? FW_CMD_WRITE_F : FW_CMD_READ_F) |
FW_PARAMS_CMD_PFN(pf) |
FW_PARAMS_CMD_VFN(vf));
FW_PARAMS_CMD_PFN_V(pf) |
FW_PARAMS_CMD_VFN_V(vf));
cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16));
/* Write Params */
@ -274,11 +274,11 @@ csio_mb_ldst(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, int reg)
htonl(FW_CMD_OP_V(FW_LDST_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_READ_F |
FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE));
ldst_cmd->cycles_to_len16 = htonl(FW_LEN16(struct fw_ldst_cmd));
ldst_cmd->u.pcie.select_naccess = FW_LDST_CMD_NACCESS(1);
ldst_cmd->u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
ldst_cmd->u.pcie.ctrl_to_fn =
(FW_LDST_CMD_LC | FW_LDST_CMD_FN(hw->pfn));
(FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(hw->pfn));
ldst_cmd->u.pcie.r = (uint8_t)reg;
}
@ -347,24 +347,24 @@ csio_mb_port(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo,
void (*cbfn) (struct csio_hw *, struct csio_mb *))
{
struct fw_port_cmd *cmdp = (struct fw_port_cmd *)(mbp->mb);
unsigned int lfc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO);
unsigned int lfc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
CSIO_INIT_MBP(mbp, cmdp, tmo, hw, cbfn, 1);
cmdp->op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) |
FW_CMD_REQUEST_F |
(wr ? FW_CMD_EXEC_F : FW_CMD_READ_F) |
FW_PORT_CMD_PORTID(portid));
FW_PORT_CMD_PORTID_V(portid));
if (!wr) {
cmdp->action_to_len16 = htonl(
FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
FW_CMD_LEN16_V(sizeof(*cmdp) / 16));
return;
}
/* Set port */
cmdp->action_to_len16 = htonl(
FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
FW_CMD_LEN16_V(sizeof(*cmdp) / 16));
if (fc & PAUSE_RX)
@ -445,16 +445,16 @@ csio_mb_iq_alloc(struct csio_hw *hw, struct csio_mb *mbp, void *priv,
cmdp->op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) |
FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
FW_IQ_CMD_PFN(iq_params->pfn) |
FW_IQ_CMD_VFN(iq_params->vfn));
FW_IQ_CMD_PFN_V(iq_params->pfn) |
FW_IQ_CMD_VFN_V(iq_params->vfn));
cmdp->alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC |
cmdp->alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F |
FW_CMD_LEN16_V(sizeof(*cmdp) / 16));
cmdp->type_to_iqandstindex = htonl(
FW_IQ_CMD_VIID(iq_params->viid) |
FW_IQ_CMD_TYPE(iq_params->type) |
FW_IQ_CMD_IQASYNCH(iq_params->iqasynch));
FW_IQ_CMD_VIID_V(iq_params->viid) |
FW_IQ_CMD_TYPE_V(iq_params->type) |
FW_IQ_CMD_IQASYNCH_V(iq_params->iqasynch));
cmdp->fl0size = htons(iq_params->fl0size);
cmdp->fl0size = htons(iq_params->fl1size);
@ -488,8 +488,8 @@ csio_mb_iq_write(struct csio_hw *hw, struct csio_mb *mbp, void *priv,
struct fw_iq_cmd *cmdp = (struct fw_iq_cmd *)(mbp->mb);
uint32_t iq_start_stop = (iq_params->iq_start) ?
FW_IQ_CMD_IQSTART(1) :
FW_IQ_CMD_IQSTOP(1);
FW_IQ_CMD_IQSTART_F :
FW_IQ_CMD_IQSTOP_F;
/*
* If this IQ write is cascaded with IQ alloc request, do not
@ -501,49 +501,49 @@ csio_mb_iq_write(struct csio_hw *hw, struct csio_mb *mbp, void *priv,
cmdp->op_to_vfn |= htonl(FW_CMD_OP_V(FW_IQ_CMD) |
FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
FW_IQ_CMD_PFN(iq_params->pfn) |
FW_IQ_CMD_VFN(iq_params->vfn));
FW_IQ_CMD_PFN_V(iq_params->pfn) |
FW_IQ_CMD_VFN_V(iq_params->vfn));
cmdp->alloc_to_len16 |= htonl(iq_start_stop |
FW_CMD_LEN16_V(sizeof(*cmdp) / 16));
cmdp->iqid |= htons(iq_params->iqid);
cmdp->fl0id |= htons(iq_params->fl0id);
cmdp->fl1id |= htons(iq_params->fl1id);
cmdp->type_to_iqandstindex |= htonl(
FW_IQ_CMD_IQANDST(iq_params->iqandst) |
FW_IQ_CMD_IQANUS(iq_params->iqanus) |
FW_IQ_CMD_IQANUD(iq_params->iqanud) |
FW_IQ_CMD_IQANDSTINDEX(iq_params->iqandstindex));
FW_IQ_CMD_IQANDST_V(iq_params->iqandst) |
FW_IQ_CMD_IQANUS_V(iq_params->iqanus) |
FW_IQ_CMD_IQANUD_V(iq_params->iqanud) |
FW_IQ_CMD_IQANDSTINDEX_V(iq_params->iqandstindex));
cmdp->iqdroprss_to_iqesize |= htons(
FW_IQ_CMD_IQPCIECH(iq_params->iqpciech) |
FW_IQ_CMD_IQDCAEN(iq_params->iqdcaen) |
FW_IQ_CMD_IQDCACPU(iq_params->iqdcacpu) |
FW_IQ_CMD_IQINTCNTTHRESH(iq_params->iqintcntthresh) |
FW_IQ_CMD_IQCPRIO(iq_params->iqcprio) |
FW_IQ_CMD_IQESIZE(iq_params->iqesize));
FW_IQ_CMD_IQPCIECH_V(iq_params->iqpciech) |
FW_IQ_CMD_IQDCAEN_V(iq_params->iqdcaen) |
FW_IQ_CMD_IQDCACPU_V(iq_params->iqdcacpu) |
FW_IQ_CMD_IQINTCNTTHRESH_V(iq_params->iqintcntthresh) |
FW_IQ_CMD_IQCPRIO_V(iq_params->iqcprio) |
FW_IQ_CMD_IQESIZE_V(iq_params->iqesize));
cmdp->iqsize |= htons(iq_params->iqsize);
cmdp->iqaddr |= cpu_to_be64(iq_params->iqaddr);
if (iq_params->type == 0) {
cmdp->iqns_to_fl0congen |= htonl(
FW_IQ_CMD_IQFLINTIQHSEN(iq_params->iqflintiqhsen)|
FW_IQ_CMD_IQFLINTCONGEN(iq_params->iqflintcongen));
FW_IQ_CMD_IQFLINTIQHSEN_V(iq_params->iqflintiqhsen)|
FW_IQ_CMD_IQFLINTCONGEN_V(iq_params->iqflintcongen));
}
if (iq_params->fl0size && iq_params->fl0addr &&
(iq_params->fl0id != 0xFFFF)) {
cmdp->iqns_to_fl0congen |= htonl(
FW_IQ_CMD_FL0HOSTFCMODE(iq_params->fl0hostfcmode)|
FW_IQ_CMD_FL0CPRIO(iq_params->fl0cprio) |
FW_IQ_CMD_FL0PADEN(iq_params->fl0paden) |
FW_IQ_CMD_FL0PACKEN(iq_params->fl0packen));
FW_IQ_CMD_FL0HOSTFCMODE_V(iq_params->fl0hostfcmode)|
FW_IQ_CMD_FL0CPRIO_V(iq_params->fl0cprio) |
FW_IQ_CMD_FL0PADEN_V(iq_params->fl0paden) |
FW_IQ_CMD_FL0PACKEN_V(iq_params->fl0packen));
cmdp->fl0dcaen_to_fl0cidxfthresh |= htons(
FW_IQ_CMD_FL0DCAEN(iq_params->fl0dcaen) |
FW_IQ_CMD_FL0DCACPU(iq_params->fl0dcacpu) |
FW_IQ_CMD_FL0FBMIN(iq_params->fl0fbmin) |
FW_IQ_CMD_FL0FBMAX(iq_params->fl0fbmax) |
FW_IQ_CMD_FL0CIDXFTHRESH(iq_params->fl0cidxfthresh));
FW_IQ_CMD_FL0DCAEN_V(iq_params->fl0dcaen) |
FW_IQ_CMD_FL0DCACPU_V(iq_params->fl0dcacpu) |
FW_IQ_CMD_FL0FBMIN_V(iq_params->fl0fbmin) |
FW_IQ_CMD_FL0FBMAX_V(iq_params->fl0fbmax) |
FW_IQ_CMD_FL0CIDXFTHRESH_V(iq_params->fl0cidxfthresh));
cmdp->fl0size |= htons(iq_params->fl0size);
cmdp->fl0addr |= cpu_to_be64(iq_params->fl0addr);
}
@ -624,11 +624,11 @@ csio_mb_iq_free(struct csio_hw *hw, struct csio_mb *mbp, void *priv,
cmdp->op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) |
FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
FW_IQ_CMD_PFN(iq_params->pfn) |
FW_IQ_CMD_VFN(iq_params->vfn));
cmdp->alloc_to_len16 = htonl(FW_IQ_CMD_FREE |
FW_IQ_CMD_PFN_V(iq_params->pfn) |
FW_IQ_CMD_VFN_V(iq_params->vfn));
cmdp->alloc_to_len16 = htonl(FW_IQ_CMD_FREE_F |
FW_CMD_LEN16_V(sizeof(*cmdp) / 16));
cmdp->type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iq_params->type));
cmdp->type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(iq_params->type));
cmdp->iqid = htons(iq_params->iqid);
cmdp->fl0id = htons(iq_params->fl0id);
@ -659,9 +659,9 @@ csio_mb_eq_ofld_alloc(struct csio_hw *hw, struct csio_mb *mbp, void *priv,
CSIO_INIT_MBP(mbp, cmdp, mb_tmo, priv, cbfn, 1);
cmdp->op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
FW_EQ_OFLD_CMD_PFN(eq_ofld_params->pfn) |
FW_EQ_OFLD_CMD_VFN(eq_ofld_params->vfn));
cmdp->alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC |
FW_EQ_OFLD_CMD_PFN_V(eq_ofld_params->pfn) |
FW_EQ_OFLD_CMD_VFN_V(eq_ofld_params->vfn));
cmdp->alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F |
FW_CMD_LEN16_V(sizeof(*cmdp) / 16));
} /* csio_mb_eq_ofld_alloc */
@ -694,7 +694,8 @@ csio_mb_eq_ofld_write(struct csio_hw *hw, struct csio_mb *mbp, void *priv,
struct fw_eq_ofld_cmd *cmdp = (struct fw_eq_ofld_cmd *)(mbp->mb);
uint32_t eq_start_stop = (eq_ofld_params->eqstart) ?
FW_EQ_OFLD_CMD_EQSTART : FW_EQ_OFLD_CMD_EQSTOP;
FW_EQ_OFLD_CMD_EQSTART_F :
FW_EQ_OFLD_CMD_EQSTOP_F;
/*
* If this EQ write is cascaded with EQ alloc request, do not
@ -706,27 +707,27 @@ csio_mb_eq_ofld_write(struct csio_hw *hw, struct csio_mb *mbp, void *priv,
cmdp->op_to_vfn |= htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
FW_EQ_OFLD_CMD_PFN(eq_ofld_params->pfn) |
FW_EQ_OFLD_CMD_VFN(eq_ofld_params->vfn));
FW_EQ_OFLD_CMD_PFN_V(eq_ofld_params->pfn) |
FW_EQ_OFLD_CMD_VFN_V(eq_ofld_params->vfn));
cmdp->alloc_to_len16 |= htonl(eq_start_stop |
FW_CMD_LEN16_V(sizeof(*cmdp) / 16));
cmdp->eqid_pkd |= htonl(FW_EQ_OFLD_CMD_EQID(eq_ofld_params->eqid));
cmdp->eqid_pkd |= htonl(FW_EQ_OFLD_CMD_EQID_V(eq_ofld_params->eqid));
cmdp->fetchszm_to_iqid |= htonl(
FW_EQ_OFLD_CMD_HOSTFCMODE(eq_ofld_params->hostfcmode) |
FW_EQ_OFLD_CMD_CPRIO(eq_ofld_params->cprio) |
FW_EQ_OFLD_CMD_PCIECHN(eq_ofld_params->pciechn) |
FW_EQ_OFLD_CMD_IQID(eq_ofld_params->iqid));
FW_EQ_OFLD_CMD_HOSTFCMODE_V(eq_ofld_params->hostfcmode) |
FW_EQ_OFLD_CMD_CPRIO_V(eq_ofld_params->cprio) |
FW_EQ_OFLD_CMD_PCIECHN_V(eq_ofld_params->pciechn) |
FW_EQ_OFLD_CMD_IQID_V(eq_ofld_params->iqid));
cmdp->dcaen_to_eqsize |= htonl(
FW_EQ_OFLD_CMD_DCAEN(eq_ofld_params->dcaen) |
FW_EQ_OFLD_CMD_DCACPU(eq_ofld_params->dcacpu) |
FW_EQ_OFLD_CMD_FBMIN(eq_ofld_params->fbmin) |
FW_EQ_OFLD_CMD_FBMAX(eq_ofld_params->fbmax) |
FW_EQ_OFLD_CMD_CIDXFTHRESHO(eq_ofld_params->cidxfthresho) |
FW_EQ_OFLD_CMD_CIDXFTHRESH(eq_ofld_params->cidxfthresh) |
FW_EQ_OFLD_CMD_EQSIZE(eq_ofld_params->eqsize));
FW_EQ_OFLD_CMD_DCAEN_V(eq_ofld_params->dcaen) |
FW_EQ_OFLD_CMD_DCACPU_V(eq_ofld_params->dcacpu) |
FW_EQ_OFLD_CMD_FBMIN_V(eq_ofld_params->fbmin) |
FW_EQ_OFLD_CMD_FBMAX_V(eq_ofld_params->fbmax) |
FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(eq_ofld_params->cidxfthresho) |
FW_EQ_OFLD_CMD_CIDXFTHRESH_V(eq_ofld_params->cidxfthresh) |
FW_EQ_OFLD_CMD_EQSIZE_V(eq_ofld_params->eqsize));
cmdp->eqaddr |= cpu_to_be64(eq_ofld_params->eqaddr);
@ -776,9 +777,9 @@ csio_mb_eq_ofld_alloc_write_rsp(struct csio_hw *hw,
*ret_val = FW_CMD_RETVAL_G(ntohl(rsp->alloc_to_len16));
if (*ret_val == FW_SUCCESS) {
eq_ofld_params->eqid = FW_EQ_OFLD_CMD_EQID_GET(
eq_ofld_params->eqid = FW_EQ_OFLD_CMD_EQID_G(
ntohl(rsp->eqid_pkd));
eq_ofld_params->physeqid = FW_EQ_OFLD_CMD_PHYSEQID_GET(
eq_ofld_params->physeqid = FW_EQ_OFLD_CMD_PHYSEQID_G(
ntohl(rsp->physeqid_pkd));
} else
eq_ofld_params->eqid = 0;
@ -809,11 +810,11 @@ csio_mb_eq_ofld_free(struct csio_hw *hw, struct csio_mb *mbp, void *priv,
cmdp->op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
FW_EQ_OFLD_CMD_PFN(eq_ofld_params->pfn) |
FW_EQ_OFLD_CMD_VFN(eq_ofld_params->vfn));
cmdp->alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE |
FW_EQ_OFLD_CMD_PFN_V(eq_ofld_params->pfn) |
FW_EQ_OFLD_CMD_VFN_V(eq_ofld_params->vfn));
cmdp->alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE_F |
FW_CMD_LEN16_V(sizeof(*cmdp) / 16));
cmdp->eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eq_ofld_params->eqid));
cmdp->eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID_V(eq_ofld_params->eqid));
} /* csio_mb_eq_ofld_free */
@ -1125,7 +1126,7 @@ csio_mb_dump_fw_dbg(struct csio_hw *hw, __be64 *cmd)
{
struct fw_debug_cmd *dbg = (struct fw_debug_cmd *)cmd;
if ((FW_DEBUG_CMD_TYPE_GET(ntohl(dbg->op_type))) == 1) {
if ((FW_DEBUG_CMD_TYPE_G(ntohl(dbg->op_type))) == 1) {
csio_info(hw, "FW print message:\n");
csio_info(hw, "\tdebug->dprtstridx = %d\n",
ntohs(dbg->u.prt.dprtstridx));
@ -1406,9 +1407,9 @@ csio_mb_fwevt_handler(struct csio_hw *hw, __be64 *cmd)
if (opcode == FW_PORT_CMD) {
pcmd = (struct fw_port_cmd *)cmd;
port_id = FW_PORT_CMD_PORTID_GET(
port_id = FW_PORT_CMD_PORTID_G(
ntohl(pcmd->op_to_portid));
action = FW_PORT_CMD_ACTION_GET(
action = FW_PORT_CMD_ACTION_G(
ntohl(pcmd->action_to_len16));
if (action != FW_PORT_ACTION_GET_PORT_INFO) {
csio_err(hw, "Unhandled FW_PORT_CMD action: %u\n",
@ -1417,15 +1418,15 @@ csio_mb_fwevt_handler(struct csio_hw *hw, __be64 *cmd)
}
link_status = ntohl(pcmd->u.info.lstatus_to_modtype);
mod_type = FW_PORT_CMD_MODTYPE_GET(link_status);
mod_type = FW_PORT_CMD_MODTYPE_G(link_status);
hw->pport[port_id].link_status =
FW_PORT_CMD_LSTATUS_GET(link_status);
FW_PORT_CMD_LSTATUS_G(link_status);
hw->pport[port_id].link_speed =
FW_PORT_CMD_LSPEED_GET(link_status);
FW_PORT_CMD_LSPEED_G(link_status);
csio_info(hw, "Port:%x - LINK %s\n", port_id,
FW_PORT_CMD_LSTATUS_GET(link_status) ? "UP" : "DOWN");
FW_PORT_CMD_LSTATUS_G(link_status) ? "UP" : "DOWN");
if (mod_type != hw->pport[port_id].mod_type) {
hw->pport[port_id].mod_type = mod_type;

12
drivers/scsi/csiostor/csio_mb.h
View File

@ -79,14 +79,14 @@ enum csio_dev_state {
};
#define FW_PARAM_DEV(param) \
(FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
#define FW_PARAM_PFVF(param) \
(FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)| \
FW_PARAMS_PARAM_Y(0) | \
FW_PARAMS_PARAM_Z(0))
(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
FW_PARAMS_PARAM_Y_V(0) | \
FW_PARAMS_PARAM_Z_V(0))
enum {
PAUSE_RX = 1 << 0,