[ARM] gic: Fix gic cascade irq handling
No need for the cascade irq function to have a "fastcall" annotation. Fix the range checking for valid IRQ numbers - comparing the value returned by the GIC with NR_IRQS is meaningless since we translate the GIC irq number to a Linux IRQ number afterwards. Check the GIC returned IRQ number is within limits first, then add the IRQ offset, and only then compare with NR_IRQS. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -125,12 +125,11 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
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}
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#endif
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static void fastcall gic_handle_cascade_irq(unsigned int irq,
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struct irq_desc *desc)
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static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct gic_chip_data *chip_data = get_irq_data(irq);
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struct irq_chip *chip = get_irq_chip(irq);
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unsigned int cascade_irq;
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unsigned int cascade_irq, gic_irq;
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unsigned long status;
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/* primary controller ack'ing */
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@ -140,16 +139,15 @@ static void fastcall gic_handle_cascade_irq(unsigned int irq,
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status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
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spin_unlock(&irq_controller_lock);
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cascade_irq = (status & 0x3ff);
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if (cascade_irq > 1020)
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gic_irq = (status & 0x3ff);
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if (gic_irq == 1023)
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goto out;
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if (cascade_irq < 32 || cascade_irq >= NR_IRQS) {
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do_bad_IRQ(cascade_irq, desc);
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goto out;
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}
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cascade_irq += chip_data->irq_offset;
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generic_handle_irq(cascade_irq);
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cascade_irq = gic_irq + chip_data->irq_offset;
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if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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/* primary controller unmasking */
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