spi: meson-spicc: adapt burst handling for G12A support
The G12A SPICC controller variant has a different FIFO size and doesn't handle the RX Half interrupt the same way as GXL & AXG variants. Thus simplify the burst management and take in account a variable FIFO size. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200312133131.26430-8-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Neil Armstrong
Mark Brown
parent
f27bff479e
commit
0eb707ac7d
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@ -141,12 +141,10 @@
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#define writel_bits_relaxed(mask, val, addr) \
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writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
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#define SPICC_BURST_MAX 16
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#define SPICC_FIFO_HALF 10
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struct meson_spicc_data {
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unsigned int max_speed_hz;
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unsigned int min_speed_hz;
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unsigned int fifo_size;
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bool has_oen;
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bool has_enhance_clk_div;
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};
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@ -166,8 +164,6 @@ struct meson_spicc_device {
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unsigned long tx_remain;
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unsigned long rx_remain;
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unsigned long xfer_remain;
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bool is_burst_end;
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bool is_last_burst;
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};
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static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
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@ -191,7 +187,7 @@ static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
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static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
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{
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return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF_EN,
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return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
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readl_relaxed(spicc->base + SPICC_STATREG));
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}
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@ -246,34 +242,22 @@ static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
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spicc->base + SPICC_TXDATA);
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}
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static inline u32 meson_spicc_setup_rx_irq(struct meson_spicc_device *spicc,
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u32 irq_ctrl)
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static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
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{
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if (spicc->rx_remain > SPICC_FIFO_HALF)
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irq_ctrl |= SPICC_RH_EN;
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else
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irq_ctrl |= SPICC_RR_EN;
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return irq_ctrl;
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}
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static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc,
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unsigned int burst_len)
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{
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unsigned int burst_len = min_t(unsigned int,
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spicc->xfer_remain /
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spicc->bytes_per_word,
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spicc->data->fifo_size);
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/* Setup Xfer variables */
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spicc->tx_remain = burst_len;
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spicc->rx_remain = burst_len;
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spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
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spicc->is_burst_end = false;
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if (burst_len < SPICC_BURST_MAX || !spicc->xfer_remain)
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spicc->is_last_burst = true;
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else
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spicc->is_last_burst = false;
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/* Setup burst length */
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writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
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FIELD_PREP(SPICC_BURSTLENGTH_MASK,
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burst_len),
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burst_len - 1),
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spicc->base + SPICC_CONREG);
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/* Fill TX FIFO */
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@ -283,61 +267,26 @@ static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc,
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static irqreturn_t meson_spicc_irq(int irq, void *data)
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{
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struct meson_spicc_device *spicc = (void *) data;
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u32 ctrl = readl_relaxed(spicc->base + SPICC_INTREG);
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u32 stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl;
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ctrl &= ~(SPICC_RH_EN | SPICC_RR_EN);
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writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
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/* Empty RX FIFO */
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meson_spicc_rx(spicc);
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/* Enable TC interrupt since we transferred everything */
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if (!spicc->tx_remain && !spicc->rx_remain) {
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spicc->is_burst_end = true;
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if (!spicc->xfer_remain) {
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/* Disable all IRQs */
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writel(0, spicc->base + SPICC_INTREG);
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/* Enable TC interrupt */
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ctrl |= SPICC_TC_EN;
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spi_finalize_current_transfer(spicc->master);
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/* Reload IRQ status */
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stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl;
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return IRQ_HANDLED;
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}
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/* Check transfer complete */
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if ((stat & SPICC_TC) && spicc->is_burst_end) {
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unsigned int burst_len;
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/* Setup burst */
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meson_spicc_setup_burst(spicc);
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/* Clear TC bit */
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writel_relaxed(SPICC_TC, spicc->base + SPICC_STATREG);
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/* Disable TC interrupt */
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ctrl &= ~SPICC_TC_EN;
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if (spicc->is_last_burst) {
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/* Disable all IRQs */
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writel(0, spicc->base + SPICC_INTREG);
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spi_finalize_current_transfer(spicc->master);
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return IRQ_HANDLED;
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}
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burst_len = min_t(unsigned int,
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spicc->xfer_remain / spicc->bytes_per_word,
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SPICC_BURST_MAX);
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/* Setup burst */
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meson_spicc_setup_burst(spicc, burst_len);
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/* Restart burst */
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writel_bits_relaxed(SPICC_XCH, SPICC_XCH,
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spicc->base + SPICC_CONREG);
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}
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/* Setup RX interrupt trigger */
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ctrl = meson_spicc_setup_rx_irq(spicc, ctrl);
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/* Reconfigure interrupts */
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writel(ctrl, spicc->base + SPICC_INTREG);
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/* Start burst */
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writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
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return IRQ_HANDLED;
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}
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@ -405,6 +354,28 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
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clk_set_rate(spicc->clk, xfer->speed_hz);
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meson_spicc_auto_io_delay(spicc);
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writel_relaxed(0, spicc->base + SPICC_DMAREG);
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}
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static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
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{
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u32 data;
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if (spicc->data->has_oen)
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writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
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SPICC_ENH_MAIN_CLK_AO,
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spicc->base + SPICC_ENH_CTL0);
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writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
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spicc->base + SPICC_TESTREG);
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while (meson_spicc_rxready(spicc))
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data = readl_relaxed(spicc->base + SPICC_RXDATA);
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if (spicc->data->has_oen)
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writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
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spicc->base + SPICC_ENH_CTL0);
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}
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static int meson_spicc_transfer_one(struct spi_master *master,
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@ -412,8 +383,6 @@ static int meson_spicc_transfer_one(struct spi_master *master,
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struct spi_transfer *xfer)
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{
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struct meson_spicc_device *spicc = spi_master_get_devdata(master);
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unsigned int burst_len;
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u32 irq = 0;
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/* Store current transfer */
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spicc->xfer = xfer;
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@ -427,22 +396,22 @@ static int meson_spicc_transfer_one(struct spi_master *master,
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spicc->bytes_per_word =
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DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
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if (xfer->len % spicc->bytes_per_word)
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return -EINVAL;
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/* Setup transfer parameters */
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meson_spicc_setup_xfer(spicc, xfer);
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burst_len = min_t(unsigned int,
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spicc->xfer_remain / spicc->bytes_per_word,
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SPICC_BURST_MAX);
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meson_spicc_reset_fifo(spicc);
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meson_spicc_setup_burst(spicc, burst_len);
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irq = meson_spicc_setup_rx_irq(spicc, irq);
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/* Setup burst */
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meson_spicc_setup_burst(spicc);
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/* Start burst */
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writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
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/* Enable interrupts */
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writel_relaxed(irq, spicc->base + SPICC_INTREG);
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writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
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return 1;
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}
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@ -499,7 +468,7 @@ static int meson_spicc_prepare_message(struct spi_master *master,
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/* Setup no wait cycles by default */
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writel_relaxed(0, spicc->base + SPICC_PERIODREG);
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writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG);
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writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
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return 0;
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}
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@ -797,11 +766,13 @@ static int meson_spicc_remove(struct platform_device *pdev)
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static const struct meson_spicc_data meson_spicc_gx_data = {
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.max_speed_hz = 30000000,
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.min_speed_hz = 325000,
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.fifo_size = 16,
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};
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static const struct meson_spicc_data meson_spicc_axg_data = {
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.max_speed_hz = 80000000,
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.min_speed_hz = 325000,
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.fifo_size = 16,
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.has_oen = true,
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.has_enhance_clk_div = true,
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};
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