Merge branch 'remotes/lorenzo/pci/iproc'
- Add more devices to Broadcom PAXC quirk (Ray Jui)
- Work around corrupted Broadcom PAXC config space to enable SMMU and
GICv3 ITS (Ray Jui)
- Disable MSI parsing to work around broken Broadcom PAXC logic in some
devices (Ray Jui)
- Hide unconfigured functions to work around a Broadcom PAXC defect (Ray
Jui)
- Lower iproc log level to reduce console output during boot (Ray Jui)
* remotes/lorenzo/pci/iproc:
PCI: iproc: Reduce inbound/outbound mapping print level
PCI: iproc: Reject unconfigured physical functions from PAXC
PCI: iproc: Disable MSI parsing in certain PAXC blocks
PCI: iproc: Fix up corrupted PAXC root complex config registers
PCI: iproc: Activate PAXC bridge quirk for more devices
This commit is contained in:
Bjorn Helgaas
commit
0ea77d2b20
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@ -85,6 +85,8 @@
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#define IMAP_VALID_SHIFT 0
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#define IMAP_VALID BIT(IMAP_VALID_SHIFT)
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#define IPROC_PCI_PM_CAP 0x48
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#define IPROC_PCI_PM_CAP_MASK 0xffff
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#define IPROC_PCI_EXP_CAP 0xac
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#define IPROC_PCIE_REG_INVALID 0xffff
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@ -375,6 +377,17 @@ static const u16 iproc_pcie_reg_paxc_v2[] = {
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[IPROC_PCIE_CFG_DATA] = 0x1fc,
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};
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/*
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* List of device IDs of controllers that have corrupted capability list that
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* require SW fixup
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*/
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static const u16 iproc_pcie_corrupt_cap_did[] = {
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0x16cd,
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0x16f0,
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0xd802,
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0xd804
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};
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static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
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{
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struct iproc_pcie *pcie = bus->sysdata;
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@ -495,6 +508,49 @@ static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)
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return data;
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}
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static void iproc_pcie_fix_cap(struct iproc_pcie *pcie, int where, u32 *val)
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{
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u32 i, dev_id;
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switch (where & ~0x3) {
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case PCI_VENDOR_ID:
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dev_id = *val >> 16;
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/*
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* Activate fixup for those controllers that have corrupted
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* capability list registers
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*/
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for (i = 0; i < ARRAY_SIZE(iproc_pcie_corrupt_cap_did); i++)
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if (dev_id == iproc_pcie_corrupt_cap_did[i])
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pcie->fix_paxc_cap = true;
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break;
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case IPROC_PCI_PM_CAP:
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if (pcie->fix_paxc_cap) {
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/* advertise PM, force next capability to PCIe */
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*val &= ~IPROC_PCI_PM_CAP_MASK;
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*val |= IPROC_PCI_EXP_CAP << 8 | PCI_CAP_ID_PM;
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}
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break;
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case IPROC_PCI_EXP_CAP:
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if (pcie->fix_paxc_cap) {
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/* advertise root port, version 2, terminate here */
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*val = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2) << 16 |
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PCI_CAP_ID_EXP;
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}
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break;
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case IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL:
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/* Don't advertise CRS SV support */
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*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
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break;
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default:
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break;
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}
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}
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static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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@ -509,13 +565,10 @@ static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
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/* root complex access */
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if (busno == 0) {
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ret = pci_generic_config_read32(bus, devfn, where, size, val);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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if (ret == PCIBIOS_SUCCESSFUL)
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iproc_pcie_fix_cap(pcie, where, val);
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/* Don't advertise CRS SV support */
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if ((where & ~0x3) == IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL)
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*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
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return PCIBIOS_SUCCESSFUL;
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return ret;
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}
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cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);
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@ -529,6 +582,25 @@ static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
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if (size <= 2)
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*val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
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/*
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* For PAXC and PAXCv2, the total number of PFs that one can enumerate
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* depends on the firmware configuration. Unfortunately, due to an ASIC
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* bug, unconfigured PFs cannot be properly hidden from the root
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* complex. As a result, write access to these PFs will cause bus lock
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* up on the embedded processor
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*
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* Since all unconfigured PFs are left with an incorrect, staled device
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* ID of 0x168e (PCI_DEVICE_ID_NX2_57810), we try to catch those access
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* early here and reject them all
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*/
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#define DEVICE_ID_MASK 0xffff0000
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#define DEVICE_ID_SHIFT 16
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if (pcie->rej_unconfig_pf &&
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(where & CFG_ADDR_REG_NUM_MASK) == PCI_VENDOR_ID)
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if ((*val & DEVICE_ID_MASK) ==
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(PCI_DEVICE_ID_NX2_57810 << DEVICE_ID_SHIFT))
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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return PCIBIOS_SUCCESSFUL;
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}
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@ -628,7 +700,7 @@ static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
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struct iproc_pcie *pcie = iproc_data(bus);
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iproc_pcie_apb_err_disable(bus, true);
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if (pcie->type == IPROC_PCIE_PAXB_V2)
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if (pcie->iproc_cfg_read)
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ret = iproc_pcie_config_read(bus, devfn, where, size, val);
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else
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ret = pci_generic_config_read32(bus, devfn, where, size, val);
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@ -808,14 +880,14 @@ static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx,
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writel(lower_32_bits(pci_addr), pcie->base + omap_offset);
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writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4);
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dev_info(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n",
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window_idx, oarr_offset, &axi_addr, &pci_addr);
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dev_info(dev, "oarr lo 0x%x oarr hi 0x%x\n",
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readl(pcie->base + oarr_offset),
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readl(pcie->base + oarr_offset + 4));
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dev_info(dev, "omap lo 0x%x omap hi 0x%x\n",
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readl(pcie->base + omap_offset),
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readl(pcie->base + omap_offset + 4));
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dev_dbg(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n",
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window_idx, oarr_offset, &axi_addr, &pci_addr);
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dev_dbg(dev, "oarr lo 0x%x oarr hi 0x%x\n",
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readl(pcie->base + oarr_offset),
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readl(pcie->base + oarr_offset + 4));
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dev_dbg(dev, "omap lo 0x%x omap hi 0x%x\n",
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readl(pcie->base + omap_offset),
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readl(pcie->base + omap_offset + 4));
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return 0;
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}
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@ -982,8 +1054,8 @@ static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
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iproc_pcie_reg_is_invalid(imap_offset))
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return -EINVAL;
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dev_info(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n",
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region_idx, iarr_offset, &axi_addr, &pci_addr);
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dev_dbg(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n",
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region_idx, iarr_offset, &axi_addr, &pci_addr);
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/*
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* Program the IARR registers. The upper 32-bit IARR register is
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@ -993,9 +1065,9 @@ static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
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pcie->base + iarr_offset);
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writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4);
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dev_info(dev, "iarr lo 0x%x iarr hi 0x%x\n",
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readl(pcie->base + iarr_offset),
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readl(pcie->base + iarr_offset + 4));
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dev_dbg(dev, "iarr lo 0x%x iarr hi 0x%x\n",
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readl(pcie->base + iarr_offset),
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readl(pcie->base + iarr_offset + 4));
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/*
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* Now program the IMAP registers. Each IARR region may have one or
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@ -1009,10 +1081,10 @@ static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
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writel(upper_32_bits(axi_addr),
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pcie->base + imap_offset + ib_map->imap_addr_offset);
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dev_info(dev, "imap window [%d] lo 0x%x hi 0x%x\n",
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window_idx, readl(pcie->base + imap_offset),
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readl(pcie->base + imap_offset +
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ib_map->imap_addr_offset));
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dev_dbg(dev, "imap window [%d] lo 0x%x hi 0x%x\n",
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window_idx, readl(pcie->base + imap_offset),
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readl(pcie->base + imap_offset +
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ib_map->imap_addr_offset));
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imap_offset += ib_map->imap_window_offset;
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axi_addr += size;
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@ -1144,10 +1216,22 @@ static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
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return ret;
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}
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static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
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static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr,
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bool enable)
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{
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u32 val;
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if (!enable) {
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/*
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* Disable PAXC MSI steering. All write transfers will be
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* treated as non-MSI transfers
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*/
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val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG);
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val &= ~MSI_ENABLE_CFG;
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iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val);
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return;
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}
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/*
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* Program bits [43:13] of address of GITS_TRANSLATER register into
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* bits [30:0] of the MSI base address register. In fact, in all iProc
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@ -1201,7 +1285,7 @@ static int iproc_pcie_msi_steer(struct iproc_pcie *pcie,
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return ret;
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break;
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case IPROC_PCIE_PAXC_V2:
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iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr);
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iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr, true);
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break;
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default:
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return -EINVAL;
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@ -1271,6 +1355,7 @@ static int iproc_pcie_rev_init(struct iproc_pcie *pcie)
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break;
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case IPROC_PCIE_PAXB:
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regs = iproc_pcie_reg_paxb;
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pcie->iproc_cfg_read = true;
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pcie->has_apb_err_disable = true;
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if (pcie->need_ob_cfg) {
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pcie->ob_map = paxb_ob_map;
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@ -1293,10 +1378,14 @@ static int iproc_pcie_rev_init(struct iproc_pcie *pcie)
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case IPROC_PCIE_PAXC:
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regs = iproc_pcie_reg_paxc;
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pcie->ep_is_internal = true;
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pcie->iproc_cfg_read = true;
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pcie->rej_unconfig_pf = true;
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break;
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case IPROC_PCIE_PAXC_V2:
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regs = iproc_pcie_reg_paxc_v2;
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pcie->ep_is_internal = true;
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pcie->iproc_cfg_read = true;
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pcie->rej_unconfig_pf = true;
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pcie->need_msi_steer = true;
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break;
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default:
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@ -1427,6 +1516,24 @@ int iproc_pcie_remove(struct iproc_pcie *pcie)
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}
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EXPORT_SYMBOL(iproc_pcie_remove);
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/*
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* The MSI parsing logic in certain revisions of Broadcom PAXC based root
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* complex does not work and needs to be disabled
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*/
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static void quirk_paxc_disable_msi_parsing(struct pci_dev *pdev)
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{
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struct iproc_pcie *pcie = iproc_data(pdev->bus);
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if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
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iproc_pcie_paxc_v2_msi_steer(pcie, 0, false);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0,
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quirk_paxc_disable_msi_parsing);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802,
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quirk_paxc_disable_msi_parsing);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804,
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quirk_paxc_disable_msi_parsing);
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MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
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MODULE_LICENSE("GPL v2");
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@ -58,8 +58,13 @@ struct iproc_msi;
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* @phy: optional PHY device that controls the Serdes
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* @map_irq: function callback to map interrupts
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* @ep_is_internal: indicates an internal emulated endpoint device is connected
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* @iproc_cfg_read: indicates the iProc config read function should be used
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* @rej_unconfig_pf: indicates the root complex needs to detect and reject
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* enumeration against unconfigured physical functions emulated in the ASIC
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* @has_apb_err_disable: indicates the controller can be configured to prevent
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* unsupported request from being forwarded as an APB bus error
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* @fix_paxc_cap: indicates the controller has corrupted capability list in its
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* config space registers and requires SW based fixup
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*
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* @need_ob_cfg: indicates SW needs to configure the outbound mapping window
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* @ob: outbound mapping related parameters
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@ -84,7 +89,10 @@ struct iproc_pcie {
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struct phy *phy;
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int (*map_irq)(const struct pci_dev *, u8, u8);
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bool ep_is_internal;
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bool iproc_cfg_read;
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bool rej_unconfig_pf;
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bool has_apb_err_disable;
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bool fix_paxc_cap;
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bool need_ob_cfg;
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struct iproc_pcie_ob ob;
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@ -2356,6 +2356,9 @@ static void quirk_paxc_bridge(struct pci_dev *pdev)
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
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#endif
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/*
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Loading…
Reference in New Issue