Qualcomm ARM64 Updates for v4.19
* Add support for PM8005/PM8998 and related nodes * Add/fix nodes on SDM845 for I2c, SPI, UART, and RPMH * Fix BT LED trigger on DB410c * Drop legacy clock names on MSM8916 * Add gpio line names on DB820c -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbU6V8AAoJEFKiBbHx2RXVEWQP/iqEdooNqTqHwxTFzVrTjMrH k4tWuXjKNIkyoxuMwOVjeDtSoHchITIe5/b3pEQqsP20kjS/ouY0moazjZkOatx/ fSNsempJkO5j3vVDMJ6veIYZqjBrzvW7FX2PzF8OI3LzSRIssZLJvhtxRZ4KgWWk zzPpbRJPww18P+eMjtiei0W1mJnbvs0T7bgJImPkfn9G4GOxGTKx8Wd8zshbH7Bn P1x9Ylr7ZV9G6B+t8j+tmJc1QzHAkgH0DMg8K0BeSo/kZ3o6kPGu+Yx1NtHRZo1W 3qY21AiDu0cQhtxvm31SfDrau0Mk3sysCAF3DL6L1o/REyxphZp/PtNuE0JRxaCE RjTjmNBD02sQZHcVeI84JDlv2x+mLIOENQeRTDz0CKDinweWkY7A9bsE8Zf+dxM1 5BLVvZbKW5jF84lUHsZsxeAwp7q2rqjT5wv+kwmyOfrMGIOz8JKYpjf7W7+wncT3 +CbRDY40XyeRMF+WkxC9Ir2fJlY4uZu4dXo/5q0PASayRl3fmF7RBPijl2qwTfw/ /sqhqtEhPCl6LUS4u1tEae2/04SwnTal/1/mfawguz+nXSuM4WuZuic8Ee1nqWTX zg3Tw8YOlBOEYggCy9WVzwI+5X3V9QHKQmsL8HjLpP7D1TY/wm5hf1/ph02TlHFG 69g8nL/ZVh49yi3Nfj70 =DQjU -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-4.19' into arm64-for-4.19-2 Qualcomm ARM64 Updates for v4.19 * Add support for PM8005/PM8998 and related nodes * Add/fix nodes on SDM845 for I2c, SPI, UART, and RPMH * Fix BT LED trigger on DB410c * Drop legacy clock names on MSM8916 * Add gpio line names on DB820c
This commit is contained in:
Andy Gross
commit
0e8f31d789
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@ -338,7 +338,7 @@
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led@6 {
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label = "apq8016-sbc:blue:bt";
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gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "bt";
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linux,default-trigger = "bluetooth-power";
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default-state = "off";
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};
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};
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@ -19,6 +19,33 @@
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/*
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* GPIO name legend: proper name = the GPIO line is used as GPIO
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* NC = not connected (pin out but not routed from the chip to
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* anything the board)
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* "[PER]" = pin is muxed for [peripheral] (not GPIO)
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* LSEC = Low Speed External Connector
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* P HSEC = Primary High Speed External Connector
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* S HSEC = Secondary High Speed External Connector
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* J14 = Camera Connector
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* TP = Test Points
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*
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* Line names are taken from the schematic "DragonBoard 820c",
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* drawing no: LM25-P2751-1
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*
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* For the lines routed to the external connectors the
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* lines are named after the 96Boards CE Specification 1.0,
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* Appendix "Expansion Connector Signal Description".
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*
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* When the 96Board naming of a line and the schematic name of
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* the same line are in conflict, the 96Board specification
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* takes precedence, which means that the external UART on the
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* LSEC is named UART0 while the schematic and SoC names this
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* UART3. This is only for the informational lines i.e. "[FOO]",
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* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
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* ones actually used for GPIO.
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*/
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/ {
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aliases {
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serial0 = &blsp2_uart1;
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@ -130,6 +157,218 @@
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status = "okay";
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};
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pinctrl@1010000 {
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gpio-line-names =
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"[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
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"[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
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"[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */
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"[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */
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"[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */
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"[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */
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"[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */
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"[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */
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"GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */
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"TP93", /* GPIO_9 */
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"GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */
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"[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
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"NC", /* GPIO_12 */
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"[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */
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"[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
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"[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */
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"TP99", /* GPIO_16 */
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"[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */
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"[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */
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"[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
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"[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
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"FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
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"FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
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"GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
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"GPIO-D", /* GPIO_24, LSEC pin 26 */
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"GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
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"GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */
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"BLSP6_I2C_SDA", /* GPIO_27 */
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"BLSP6_I2C_SCL", /* GPIO_28 */
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"GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */
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"GPIO30", /* GPIO_30, S HSEC pin 4 */
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"HDMI_CEC", /* GPIO_31 */
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"HDMI_DDC_CLOCK", /* GPIO_32 */
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"HDMI_DDC_DATA", /* GPIO_33 */
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"HDMI_HOT_PLUG_DETECT", /* GPIO_34 */
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"PCIE0_RST_N", /* GPIO_35 */
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"PCIE0_CLKREQ_N", /* GPIO_36 */
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"PCIE0_WAKE", /* GPIO_37 */
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"SD_CARD_DET_N", /* GPIO_38 */
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"TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */
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"W_DISABLE_N", /* GPIO_40 */
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"[BLSP9_UART_TX]", /* GPIO_41 */
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"[BLSP9_UART_RX]", /* GPIO_42 */
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"[BLSP2_UART_CTS_N]", /* GPIO_43 */
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"[BLSP2_UART_RFR_N]", /* GPIO_44 */
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"[BLSP3_UART_TX]", /* GPIO_45 */
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"[BLSP3_UART_RX]", /* GPIO_46 */
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"[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */
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"[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */
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"[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */
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"[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */
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"[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */
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"[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */
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"[CODEC_INT1_N]", /* GPIO_53 */
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"[CODEC_INT2_N]", /* GPIO_54 */
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"[BLSP7_I2C_SDA]", /* GPIO_55 */
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"[BLSP7_I2C_SCL]", /* GPIO_56 */
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"MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */
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"[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */
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"[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */
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"[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */
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"[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */
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"GPIO-E", /* GPIO_62, LSEC pin 27 */
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"TP87", /* GPIO_63 */
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"[CODEC_RST_N]", /* GPIO_64 */
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"[PCM1_CLK]", /* GPIO_65 */
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"[PCM1_SYNC]", /* GPIO_66 */
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"[PCM1_DIN]", /* GPIO_67 */
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"[PCM1_DOUT]", /* GPIO_68 */
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"AUDIO_REF_CLK", /* GPIO_69 */
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"SLIMBUS_CLK", /* GPIO_70 */
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"SLIMBUS_DATA0", /* GPIO_71 */
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"SLIMBUS_DATA1", /* GPIO_72 */
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"NC", /* GPIO_73 */
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"NC", /* GPIO_74 */
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"NC", /* GPIO_75 */
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"NC", /* GPIO_76 */
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"TP94", /* GPIO_77 */
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"NC", /* GPIO_78 */
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"TP95", /* GPIO_79 */
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"GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */
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"TP88", /* GPIO_81 */
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"TP89", /* GPIO_82 */
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"TP90", /* GPIO_83 */
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"TP91", /* GPIO_84 */
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"[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */
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"[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */
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"[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */
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"[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */
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"TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */
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"TSIF1_EN", /* GPIO_90, S HSEC pin 46 */
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"TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */
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"NC", /* GPIO_92 */
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"TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */
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"TSIF2_EN", /* GPIO_94, S HSEC pin 56 */
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"TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */
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"TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */
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"NC", /* GPIO_97 */
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"CAM1_STANDBY_N", /* GPIO_98 */
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"NC", /* GPIO_99 */
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"NC", /* GPIO_100 */
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"[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */
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"BOOT_CONFIG1", /* GPIO_102 */
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"USB_HUB_RESET", /* GPIO_103 */
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"CAM1_RST_N", /* GPIO_104 */
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"NC", /* GPIO_105 */
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"NC", /* GPIO_106 */
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"NC", /* GPIO_107 */
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"NC", /* GPIO_108 */
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"NC", /* GPIO_109 */
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"NC", /* GPIO_110 */
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"NC", /* GPIO_111 */
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"NC", /* GPIO_112 */
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"PMI8994_BUA", /* GPIO_113 */
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"PCIE2_RST_N", /* GPIO_114 */
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"PCIE2_CLKREQ_N", /* GPIO_115 */
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"PCIE2_WAKE", /* GPIO_116 */
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"SSC_IRQ_0", /* GPIO_117 */
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"SSC_IRQ_1", /* GPIO_118 */
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"SSC_IRQ_2", /* GPIO_119 */
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"NC", /* GPIO_120 */
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"GPIO121", /* GPIO_121, S HSEC pin 2 */
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"NC", /* GPIO_122 */
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"SSC_IRQ_6", /* GPIO_123 */
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"SSC_IRQ_7", /* GPIO_124 */
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"GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */
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"BOOT_CONFIG5", /* GPIO_126 */
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"NC", /* GPIO_127 */
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"NC", /* GPIO_128 */
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"BOOT_CONFIG7", /* GPIO_129 */
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"PCIE1_RST_N", /* GPIO_130 */
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"PCIE1_CLKREQ_N", /* GPIO_131 */
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"PCIE1_WAKE", /* GPIO_132 */
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"GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */
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"NC", /* GPIO_134 */
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"NC", /* GPIO_135 */
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"BOOT_CONFIG8", /* GPIO_136 */
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"NC", /* GPIO_137 */
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"NC", /* GPIO_138 */
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"GPS_SSBI2", /* GPIO_139 */
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"GPS_SSBI1", /* GPIO_140 */
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"NC", /* GPIO_141 */
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"NC", /* GPIO_142 */
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"NC", /* GPIO_143 */
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"BOOT_CONFIG6", /* GPIO_144 */
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"NC", /* GPIO_145 */
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"NC", /* GPIO_146 */
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"NC", /* GPIO_147 */
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"NC", /* GPIO_148 */
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"NC"; /* GPIO_149 */
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};
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qcom,spmi@400f000 {
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pmic@0 {
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gpios@c000 {
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gpio-line-names =
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"NC",
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"KEY_VOLP_N",
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"NC",
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"BL1_PWM",
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"GPIO-F", /* BL0_PWM, LSEC pin 28 */
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"BL1_EN",
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"NC",
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"WLAN_EN",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"DIVCLK1",
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"DIVCLK2",
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"DIVCLK3",
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"DIVCLK4",
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"BT_EN",
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"PMIC_SLB",
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"PMIC_BUA",
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"USB_VBUS_DET";
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};
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mpps@a000 {
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gpio-line-names =
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"VDDPX_BIAS",
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"WIFI_LED",
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"NC",
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"BT_LED",
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"PM_MPP05",
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"PM_MPP06",
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"PM_MPP07",
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"NC";
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};
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};
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pmic@2 {
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gpios@c000 {
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gpio-line-names =
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"NC",
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"SPKR_AMP_EN1",
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"SPKR_AMP_EN2",
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"TP61",
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"NC",
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"USB2_VBUS_DET",
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"NC",
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"NC",
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"NC",
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"NC";
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};
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};
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};
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phy@34000 {
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status = "okay";
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};
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@ -858,9 +858,9 @@
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface_clk",
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"bus_clk",
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"vsync_clk";
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clock-names = "iface",
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"bus",
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"vsync";
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interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
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@ -883,10 +883,10 @@
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_MDP_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface_clk",
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"bus_clk",
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"core_clk",
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"vsync_clk";
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clock-names = "iface",
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"bus",
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"core",
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"vsync";
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iommus = <&apps_iommu 4>;
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@ -922,12 +922,12 @@
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<&gcc GCC_MDSS_BYTE0_CLK>,
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<&gcc GCC_MDSS_PCLK0_CLK>,
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<&gcc GCC_MDSS_ESC0_CLK>;
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clock-names = "mdp_core_clk",
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"iface_clk",
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"bus_clk",
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"byte_clk",
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"pixel_clk",
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"core_clk";
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clock-names = "mdp_core",
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"iface",
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"bus",
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"byte",
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"pixel",
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"core";
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phys = <&dsi_phy0>;
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phy-names = "dsi-phy";
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|
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@ -963,7 +963,7 @@
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#phy-cells = <0>;
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|
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clocks = <&gcc GCC_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-names = "iface";
|
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};
|
||||
};
|
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|
||||
|
|
|
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|
|
@ -0,0 +1,33 @@
|
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/* Copyright 2018 Google LLC. */
|
||||
|
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#include <dt-bindings/spmi/spmi.h>
|
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#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
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&spmi_bus {
|
||||
pm8005_lsid0: pmic@4 {
|
||||
compatible = "qcom,pm8005", "qcom,spmi-pmic";
|
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reg = <0x4 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm8005_gpio: gpios@c000 {
|
||||
compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio";
|
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reg = <0xc000>;
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||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc1 0 IRQ_TYPE_NONE>,
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<0 0xc2 0 IRQ_TYPE_NONE>,
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<0 0xc3 0 IRQ_TYPE_NONE>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pm8005_lsid1: pmic@5 {
|
||||
compatible = "qcom,pm8005", "qcom,spmi-pmic";
|
||||
reg = <0x5 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/* Copyright 2018 Google LLC. */
|
||||
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
&spmi_bus {
|
||||
pm8998_lsid0: pmic@0 {
|
||||
compatible = "qcom,pm8998", "qcom,spmi-pmic";
|
||||
reg = <0x0 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm8998_gpio: gpios@c000 {
|
||||
compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
|
||||
reg = <0xc000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc1 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc2 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc3 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc4 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc5 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc6 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc7 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc8 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc9 0 IRQ_TYPE_NONE>,
|
||||
<0 0xca 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcb 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcc 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcd 0 IRQ_TYPE_NONE>,
|
||||
<0 0xce 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcf 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd0 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd1 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd2 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd3 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd4 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd5 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd6 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd7 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd8 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd9 0 IRQ_TYPE_NONE>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pm8998_lsid1: pmic@1 {
|
||||
compatible = "qcom,pm8998", "qcom,spmi-pmic";
|
||||
reg = <0x1 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -12,4 +12,49 @@
|
|||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SDM845 MTP";
|
||||
compatible = "qcom,sdm845-mtp";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart9;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart9 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
|
||||
|
||||
&qup_i2c10_default {
|
||||
pinconf {
|
||||
pins = "gpio55", "gpio56";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_uart9_default {
|
||||
pinconf-tx {
|
||||
pins = "gpio4";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinconf-rx {
|
||||
pins = "gpio5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,7 +5,10 @@
|
|||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
|
|
@ -13,6 +16,41 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c7;
|
||||
i2c8 = &i2c8;
|
||||
i2c9 = &i2c9;
|
||||
i2c10 = &i2c10;
|
||||
i2c11 = &i2c11;
|
||||
i2c12 = &i2c12;
|
||||
i2c13 = &i2c13;
|
||||
i2c14 = &i2c14;
|
||||
i2c15 = &i2c15;
|
||||
spi0 = &spi0;
|
||||
spi1 = &spi1;
|
||||
spi2 = &spi2;
|
||||
spi3 = &spi3;
|
||||
spi4 = &spi4;
|
||||
spi5 = &spi5;
|
||||
spi6 = &spi6;
|
||||
spi7 = &spi7;
|
||||
spi8 = &spi8;
|
||||
spi9 = &spi9;
|
||||
spi10 = &spi10;
|
||||
spi11 = &spi11;
|
||||
spi12 = &spi12;
|
||||
spi13 = &spi13;
|
||||
spi14 = &spi14;
|
||||
spi15 = &spi15;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
||||
memory@80000000 {
|
||||
|
|
@ -152,6 +190,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
|
||||
|
|
@ -206,6 +249,457 @@
|
|||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
qupv3_id_0: geniqup@8c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x8c0000 0x6000>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
i2c0: i2c@880000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x880000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c0_default>;
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@880000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0x880000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi0_default>;
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@884000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x884000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c1_default>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@884000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0x884000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi1_default>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@888000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x888000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c2_default>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@888000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0x888000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi2_default>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@88c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x88c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c3_default>;
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@88c000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0x88c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi3_default>;
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@890000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x890000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c4_default>;
|
||||
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@890000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0x890000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi4_default>;
|
||||
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@894000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x894000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c5_default>;
|
||||
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi5: spi@894000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0x894000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi5_default>;
|
||||
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@898000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x898000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c6_default>;
|
||||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi6: spi@898000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0x898000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi6_default>;
|
||||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@89c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x89c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c7_default>;
|
||||
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi7: spi@89c000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0x89c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi7_default>;
|
||||
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_id_1: geniqup@ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0xac0000 0x6000>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
i2c8: i2c@a80000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa80000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c8_default>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi8: spi@a80000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0xa80000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi8_default>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c9: i2c@a84000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa84000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c9_default>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi9: spi@a84000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0xa84000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi9_default>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart9: serial@a84000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0xa84000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart9_default>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c10: i2c@a88000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa88000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c10_default>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi10: spi@a88000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0xa88000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi10_default>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c11: i2c@a8c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c11_default>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi11: spi@a8c000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi11_default>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c12: i2c@a90000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa90000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c12_default>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi12: spi@a90000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0xa90000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi12_default>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c13: i2c@a94000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa94000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c13_default>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi13: spi@a94000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0xa94000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi13_default>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c14: i2c@a98000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa98000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c14_default>;
|
||||
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi14: spi@a98000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0xa98000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi14_default>;
|
||||
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c15: i2c@a9c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa9c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c15_default>;
|
||||
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi15: spi@a9c000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0xa9c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi15_default>;
|
||||
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
tcsr_mutex_regs: syscon@1f40000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1f40000 0x40000>;
|
||||
|
|
@ -219,6 +713,253 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
qup_i2c0_default: qup-i2c0-default {
|
||||
pinmux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "qup0";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c1_default: qup-i2c1-default {
|
||||
pinmux {
|
||||
pins = "gpio17", "gpio18";
|
||||
function = "qup1";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c2_default: qup-i2c2-default {
|
||||
pinmux {
|
||||
pins = "gpio27", "gpio28";
|
||||
function = "qup2";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c3_default: qup-i2c3-default {
|
||||
pinmux {
|
||||
pins = "gpio41", "gpio42";
|
||||
function = "qup3";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c4_default: qup-i2c4-default {
|
||||
pinmux {
|
||||
pins = "gpio89", "gpio90";
|
||||
function = "qup4";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c5_default: qup-i2c5-default {
|
||||
pinmux {
|
||||
pins = "gpio85", "gpio86";
|
||||
function = "qup5";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c6_default: qup-i2c6-default {
|
||||
pinmux {
|
||||
pins = "gpio45", "gpio46";
|
||||
function = "qup6";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c7_default: qup-i2c7-default {
|
||||
pinmux {
|
||||
pins = "gpio93", "gpio94";
|
||||
function = "qup7";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c8_default: qup-i2c8-default {
|
||||
pinmux {
|
||||
pins = "gpio65", "gpio66";
|
||||
function = "qup8";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c9_default: qup-i2c9-default {
|
||||
pinmux {
|
||||
pins = "gpio6", "gpio7";
|
||||
function = "qup9";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c10_default: qup-i2c10-default {
|
||||
pinmux {
|
||||
pins = "gpio55", "gpio56";
|
||||
function = "qup10";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c11_default: qup-i2c11-default {
|
||||
pinmux {
|
||||
pins = "gpio31", "gpio32";
|
||||
function = "qup11";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c12_default: qup-i2c12-default {
|
||||
pinmux {
|
||||
pins = "gpio49", "gpio50";
|
||||
function = "qup12";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c13_default: qup-i2c13-default {
|
||||
pinmux {
|
||||
pins = "gpio105", "gpio106";
|
||||
function = "qup13";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c14_default: qup-i2c14-default {
|
||||
pinmux {
|
||||
pins = "gpio33", "gpio34";
|
||||
function = "qup14";
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c15_default: qup-i2c15-default {
|
||||
pinmux {
|
||||
pins = "gpio81", "gpio82";
|
||||
function = "qup15";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi0_default: qup-spi0-default {
|
||||
pinmux {
|
||||
pins = "gpio0", "gpio1",
|
||||
"gpio2", "gpio3";
|
||||
function = "qup0";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi1_default: qup-spi1-default {
|
||||
pinmux {
|
||||
pins = "gpio17", "gpio18",
|
||||
"gpio19", "gpio20";
|
||||
function = "qup1";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi2_default: qup-spi2-default {
|
||||
pinmux {
|
||||
pins = "gpio27", "gpio28",
|
||||
"gpio29", "gpio30";
|
||||
function = "qup2";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi3_default: qup-spi3-default {
|
||||
pinmux {
|
||||
pins = "gpio41", "gpio42",
|
||||
"gpio43", "gpio44";
|
||||
function = "qup3";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi4_default: qup-spi4-default {
|
||||
pinmux {
|
||||
pins = "gpio89", "gpio90",
|
||||
"gpio91", "gpio92";
|
||||
function = "qup4";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi5_default: qup-spi5-default {
|
||||
pinmux {
|
||||
pins = "gpio85", "gpio86",
|
||||
"gpio87", "gpio88";
|
||||
function = "qup5";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi6_default: qup-spi6-default {
|
||||
pinmux {
|
||||
pins = "gpio45", "gpio46",
|
||||
"gpio47", "gpio48";
|
||||
function = "qup6";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi7_default: qup-spi7-default {
|
||||
pinmux {
|
||||
pins = "gpio93", "gpio94",
|
||||
"gpio95", "gpio96";
|
||||
function = "qup7";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi8_default: qup-spi8-default {
|
||||
pinmux {
|
||||
pins = "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
function = "qup8";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi9_default: qup-spi9-default {
|
||||
pinmux {
|
||||
pins = "gpio6", "gpio7",
|
||||
"gpio4", "gpio5";
|
||||
function = "qup9";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi10_default: qup-spi10-default {
|
||||
pinmux {
|
||||
pins = "gpio55", "gpio56",
|
||||
"gpio53", "gpio54";
|
||||
function = "qup10";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi11_default: qup-spi11-default {
|
||||
pinmux {
|
||||
pins = "gpio31", "gpio32",
|
||||
"gpio33", "gpio34";
|
||||
function = "qup11";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi12_default: qup-spi12-default {
|
||||
pinmux {
|
||||
pins = "gpio49", "gpio50",
|
||||
"gpio51", "gpio52";
|
||||
function = "qup12";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi13_default: qup-spi13-default {
|
||||
pinmux {
|
||||
pins = "gpio105", "gpio106",
|
||||
"gpio107", "gpio108";
|
||||
function = "qup13";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi14_default: qup-spi14-default {
|
||||
pinmux {
|
||||
pins = "gpio33", "gpio34",
|
||||
"gpio31", "gpio32";
|
||||
function = "qup14";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi15_default: qup-spi15-default {
|
||||
pinmux {
|
||||
pins = "gpio81", "gpio82",
|
||||
"gpio83", "gpio84";
|
||||
function = "qup15";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart9_default: qup-uart9-default {
|
||||
pinmux {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "qup9";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spmi_bus: spmi@c440000 {
|
||||
|
|
@ -246,6 +987,29 @@
|
|||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
apps_rsc: rsc@179c0000 {
|
||||
label = "apps_rsc";
|
||||
compatible = "qcom,rpmh-rsc";
|
||||
reg = <0x179c0000 0x10000>,
|
||||
<0x179d0000 0x10000>,
|
||||
<0x179e0000 0x10000>;
|
||||
reg-names = "drv-0", "drv-1", "drv-2";
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,tcs-offset = <0xd00>;
|
||||
qcom,drv-id = <2>;
|
||||
qcom,tcs-config = <ACTIVE_TCS 2>,
|
||||
<SLEEP_TCS 3>,
|
||||
<WAKE_TCS 3>,
|
||||
<CONTROL_TCS 1>;
|
||||
|
||||
rpmhcc: clock-controller {
|
||||
compatible = "qcom,sdm845-rpmh-clk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@17a00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue