clocksource: tcb_clksrc: Replace clk_enable/disable with clk_prepare_enable/disable_unprepare
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to avoid common clk framework warnings. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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@ -100,7 +100,7 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
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|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
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__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
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__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
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clk_disable(tcd->clk);
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clk_disable_unprepare(tcd->clk);
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}
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switch (m) {
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@ -109,7 +109,7 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
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* of oneshot, we get lower overhead and improved accuracy.
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*/
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case CLOCK_EVT_MODE_PERIODIC:
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clk_enable(tcd->clk);
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clk_prepare_enable(tcd->clk);
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/* slow clock, count up to RC, then irq and restart */
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__raw_writel(timer_clock
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@ -126,7 +126,7 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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clk_enable(tcd->clk);
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clk_prepare_enable(tcd->clk);
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/* slow clock, count up to RC, then irq and stop */
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__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
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@ -265,6 +265,7 @@ static int __init tcb_clksrc_init(void)
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int best_divisor_idx = -1;
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int clk32k_divisor_idx = -1;
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int i;
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int ret;
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tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
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if (!tc) {
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@ -275,7 +276,11 @@ static int __init tcb_clksrc_init(void)
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pdev = tc->pdev;
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t0_clk = tc->clk[0];
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clk_enable(t0_clk);
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ret = clk_prepare_enable(t0_clk);
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if (ret) {
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pr_debug("can't enable T0 clk\n");
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goto err_free_tc;
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}
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/* How fast will we be counting? Pick something over 5 MHz. */
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rate = (u32) clk_get_rate(t0_clk);
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@ -313,7 +318,11 @@ static int __init tcb_clksrc_init(void)
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/* tclib will give us three clocks no matter what the
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* underlying platform supports.
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*/
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clk_enable(tc->clk[1]);
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ret = clk_prepare_enable(tc->clk[1]);
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if (ret) {
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pr_debug("can't enable T1 clk\n");
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goto err_disable_t0;
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}
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/* setup both channel 0 & 1 */
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tcb_setup_dual_chan(tc, best_divisor_idx);
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}
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@ -325,5 +334,12 @@ static int __init tcb_clksrc_init(void)
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setup_clkevents(tc, clk32k_divisor_idx);
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return 0;
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err_disable_t0:
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clk_disable_unprepare(t0_clk);
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err_free_tc:
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atmel_tc_free(tc);
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return ret;
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}
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arch_initcall(tcb_clksrc_init);
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