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net: stmmac: Fix for mismatched host/device DMA address width 

[ Upstream commit 070246e467 ]

Currently DMA address width is either read from a RO device register
or force set from the platform data. This breaks DMA when the host DMA
address width is <=32it but the device is >32bit.

Right now the driver may decide to use a 2nd DMA descriptor for
another buffer (happens in case of TSO xmit) assuming that 32bit
addressing is used due to platform configuration but the device will
still use both descriptor addresses as one address.

This can be observed with the Intel EHL platform driver that sets
32bit for addr64 but the MAC reports 40bit. The TX queue gets stuck in
case of TCP with iptables NAT configuration on TSO packets.

The logic should be like this: Whatever we do on the host side (memory
allocation GFP flags) should happen with the host DMA width, whenever
we decide how to set addresses on the device registers we must use the
device DMA address width.

This patch renames the platform address width field from addr64 (term
used in device datasheet) to host_addr and uses this value exclusively
for host side operations while all chip operations consider the device
DMA width as read from the device register.

Fixes: 7cfc4486e7 ("stmmac: intel: Configure EHL PSE0 GbE and PSE1 GbE to 32 bits DMA addressing")
Signed-off-by: Jochen Henneberg <jh@henneberg-systemdesign.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Jochen Henneberg 2023-03-17 09:08:17 +01:00 committed by Greg Kroah-Hartman
parent 77800daf75
commit 0e60f30e65
6 changed files with 22 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/net/ethernet/stmicro/stmmac/common.h
View File

@ -418,6 +418,7 @@ struct dma_features {
unsigned int frpbs;
unsigned int frpes;
unsigned int addr64;
unsigned int host_dma_width;
unsigned int rssen;
unsigned int vlhash;
unsigned int sphen;

2
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
View File

@ -251,7 +251,7 @@ static int imx_dwmac_probe(struct platform_device *pdev)
goto err_parse_dt;
}
plat_dat->addr64 = dwmac->ops->addr_width;
plat_dat->host_dma_width = dwmac->ops->addr_width;
plat_dat->init = imx_dwmac_init;
plat_dat->exit = imx_dwmac_exit;
plat_dat->clks_config = imx_dwmac_clks_config;

4
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
View File

@ -684,7 +684,7 @@ static int ehl_pse0_common_data(struct pci_dev *pdev,
intel_priv->is_pse = true;
plat->bus_id = 2;
plat->addr64 = 32;
plat->host_dma_width = 32;
plat->clk_ptp_rate = 200000000;
@ -725,7 +725,7 @@ static int ehl_pse1_common_data(struct pci_dev *pdev,
intel_priv->is_pse = true;
plat->bus_id = 3;
plat->addr64 = 32;
plat->host_dma_width = 32;
plat->clk_ptp_rate = 200000000;

2
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
View File

@ -591,7 +591,7 @@ static int mediatek_dwmac_common_data(struct platform_device *pdev,
plat->use_phy_wol = priv_plat->mac_wol ? 0 : 1;
plat->riwt_off = 1;
plat->maxmtu = ETH_DATA_LEN;
plat->addr64 = priv_plat->variant->dma_bit_mask;
plat->host_dma_width = priv_plat->variant->dma_bit_mask;
plat->bsp_priv = priv_plat;
plat->init = mediatek_dwmac_init;
plat->clks_config = mediatek_dwmac_clks_config;

30
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
View File

@ -1429,7 +1429,7 @@ static int stmmac_init_rx_buffers(struct stmmac_priv *priv,
struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
if (priv->dma_cap.addr64 <= 32)
if (priv->dma_cap.host_dma_width <= 32)
gfp |= GFP_DMA32;
if (!buf->page) {
@ -4585,7 +4585,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
unsigned int entry = rx_q->dirty_rx;
gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
if (priv->dma_cap.addr64 <= 32)
if (priv->dma_cap.host_dma_width <= 32)
gfp |= GFP_DMA32;
while (dirty-- > 0) {
@ -6201,7 +6201,7 @@ static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
seq_printf(seq, "\tFlexible RX Parser: %s\n",
priv->dma_cap.frpsel ? "Y" : "N");
seq_printf(seq, "\tEnhanced Addressing: %d\n",
priv->dma_cap.addr64);
priv->dma_cap.host_dma_width);
seq_printf(seq, "\tReceive Side Scaling: %s\n",
priv->dma_cap.rssen ? "Y" : "N");
seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
@ -7171,20 +7171,22 @@ int stmmac_dvr_probe(struct device *device,
dev_info(priv->device, "SPH feature enabled\n");
}
/* The current IP register MAC_HW_Feature1[ADDR64] only define
* 32/40/64 bit width, but some SOC support others like i.MX8MP
* support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64].
* So overwrite dma_cap.addr64 according to HW real design.
/* Ideally our host DMA address width is the same as for the
* device. However, it may differ and then we have to use our
* host DMA width for allocation and the device DMA width for
* register handling.
*/
if (priv->plat->addr64)
priv->dma_cap.addr64 = priv->plat->addr64;
if (priv->plat->host_dma_width)
priv->dma_cap.host_dma_width = priv->plat->host_dma_width;
else
priv->dma_cap.host_dma_width = priv->dma_cap.addr64;
if (priv->dma_cap.addr64) {
if (priv->dma_cap.host_dma_width) {
ret = dma_set_mask_and_coherent(device,
DMA_BIT_MASK(priv->dma_cap.addr64));
DMA_BIT_MASK(priv->dma_cap.host_dma_width));
if (!ret) {
dev_info(priv->device, "Using %d bits DMA width\n",
priv->dma_cap.addr64);
dev_info(priv->device, "Using %d/%d bits DMA host/device width\n",
priv->dma_cap.host_dma_width, priv->dma_cap.addr64);
/*
* If more than 32 bits can be addressed, make sure to
@ -7199,7 +7201,7 @@ int stmmac_dvr_probe(struct device *device,
goto error_hw_init;
}
priv->dma_cap.addr64 = 32;
priv->dma_cap.host_dma_width = 32;
}
}

2
include/linux/stmmac.h
View File

@ -215,7 +215,7 @@ struct plat_stmmacenet_data {
int unicast_filter_entries;
int tx_fifo_size;
int rx_fifo_size;
u32 addr64;
u32 host_dma_width;
u32 rx_queues_to_use;
u32 tx_queues_to_use;
u8 rx_sched_algorithm;