Merge branch 'rmobile-latest' of git://github.com/pmundt/linux-sh
* 'rmobile-latest' of git://github.com/pmundt/linux-sh: (21 commits) ARM: mach-shmobile: ag5evm needs CONFIG_I2C ARM: mach-shmobile: sh73a0 and AG5EVM PINT support ARM: mach-shmobile: Add support for PINT though INTC macros ARM: mach-shmobile: SDHI0 GPIO hotplug for AG5EVM ARM: mach-shmobile: Use common INTC IRQ code on sh73a0 ARM: mach-shmobile: Use common INTC IRQ code on sh7372 ARM: mach-shmobile: Use common INTC IRQ code on sh7377 ARM: mach-shmobile: Use common INTC IRQ code on sh7367 ARM: mach-shmobile: sh73a0 GPIO IRQ support ARM: sh7372 ap4evb NOR Flash USB boot fix ARM: mach-shmobile: sh7372 Mackerel NOR Flash USB boot fix sh: intc: Allow triggering on both edges for ARM SoCs ARM: mach-shmobile: Break out INTC IRQ code ARM: mach-shmobile: Kota2 SDHI0 and SDHI1 support ARM: mach-shmobile: Kota2 SCIFA4 and SCIFB support ARM: mach-shmobile: Kota2 MMCIF support ARM: mach-shmobile: Kota2 GPIO LEDs support ARM: mach-shmobile: Kota2 GPIO Keys support ARM: mach-shmobile: Kota2 KEYSC support ARM: mach-shmobile: Kota2 SCIFA2 and SMSC911X support ...
This commit is contained in:
Linus Torvalds
commit
0e4c9dc2f2
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@ -26,6 +26,7 @@ config ARCH_SH73A0
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select SH_CLK_CPG
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select ARM_GIC
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select I2C
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comment "SH-Mobile Board Type"
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@ -69,6 +70,11 @@ config MACH_MACKEREL
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depends on ARCH_SH7372
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select ARCH_REQUIRE_GPIOLIB
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config MACH_KOTA2
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bool "KOTA2 board"
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select ARCH_REQUIRE_GPIOLIB
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depends on ARCH_SH73A0
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comment "SH-Mobile System Configuration"
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menu "Memory configuration"
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@ -78,6 +84,7 @@ config MEMORY_START
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default "0x50000000" if MACH_G3EVM
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default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
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MACH_MACKEREL
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default "0x41000000" if MACH_KOTA2
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default "0x00000000"
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---help---
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Tweak this only when porting to a new machine which does not
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@ -89,6 +96,7 @@ config MEMORY_SIZE
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default "0x08000000" if MACH_G3EVM
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default "0x08000000" if MACH_G4EVM
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default "0x20000000" if MACH_AG5EVM
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default "0x1e000000" if MACH_KOTA2
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default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
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default "0x04000000"
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help
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@ -41,6 +41,7 @@ obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o
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obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
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obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
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obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
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obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
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# Framework support
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obj-$(CONFIG_SMP) += $(smp-y)
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@ -59,7 +59,7 @@ static struct resource smsc9220_resources[] = {
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gic_spi(33), /* PINT1 */
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.start = SH73A0_PINT0_IRQ(2), /* PINTA2 */
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.flags = IORESOURCE_IRQ,
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},
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};
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@ -339,6 +339,18 @@ static struct platform_device mipidsi0_device = {
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},
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};
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/* SDHI0 */
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static irqreturn_t ag5evm_sdhi0_gpio_cd(int irq, void *arg)
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{
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struct device *dev = arg;
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struct sh_mobile_sdhi_info *info = dev->platform_data;
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struct tmio_mmc_data *pdata = info->pdata;
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tmio_mmc_cd_wakeup(pdata);
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return IRQ_HANDLED;
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}
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static struct sh_mobile_sdhi_info sdhi0_info = {
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.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
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.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
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@ -462,19 +474,6 @@ static void __init ag5evm_map_io(void)
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shmobile_setup_console();
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}
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#define PINTC_ADDR 0xe6900000
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#define PINTER0A (PINTC_ADDR + 0xa0)
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#define PINTCR0A (PINTC_ADDR + 0xb0)
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void __init ag5evm_init_irq(void)
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{
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sh73a0_init_irq();
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/* setup PINT: enable PINTA2 as active low */
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__raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A);
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__raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
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}
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#define DSI0PHYCR 0xe615006c
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static void __init ag5evm_init(void)
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@ -570,6 +569,13 @@ static void __init ag5evm_init(void)
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gpio_request(GPIO_FN_SDHID0_1, NULL);
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gpio_request(GPIO_FN_SDHID0_0, NULL);
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if (!request_irq(intcs_evt2irq(0x3c0), ag5evm_sdhi0_gpio_cd,
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IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
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"sdhi0 cd", &sdhi0_device.dev))
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sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD;
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else
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pr_warn("Unable to setup SDHI0 GPIO IRQ\n");
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/* enable SDHI1 on CN4 [WLAN I/F] */
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gpio_request(GPIO_FN_SDHICLK1, NULL);
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gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
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@ -601,7 +607,7 @@ struct sys_timer ag5evm_timer = {
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MACHINE_START(AG5EVM, "ag5evm")
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.map_io = ag5evm_map_io,
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.init_irq = ag5evm_init_irq,
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.init_irq = sh73a0_init_irq,
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.handle_irq = shmobile_handle_irq_gic,
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.init_machine = ag5evm_init,
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.timer = &ag5evm_timer,
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@ -200,8 +200,8 @@ static struct physmap_flash_data nor_flash_data = {
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static struct resource nor_flash_resources[] = {
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[0] = {
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.start = 0x00000000,
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.end = 0x08000000 - 1,
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.start = 0x20000000, /* CS0 shadow instead of regular CS0 */
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.end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
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.flags = IORESOURCE_MEM,
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}
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};
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@ -0,0 +1,447 @@
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/*
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* kota2 board support
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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* Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com>
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* Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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||||
* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/smsc911x.h>
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#include <linux/gpio.h>
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#include <linux/input.h>
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#include <linux/input/sh_keysc.h>
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#include <linux/gpio_keys.h>
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#include <linux/leds.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sh_mmcif.h>
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#include <linux/mfd/tmio.h>
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#include <linux/mmc/sh_mobile_sdhi.h>
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#include <mach/hardware.h>
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#include <mach/sh73a0.h>
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#include <mach/common.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/traps.h>
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static struct resource smsc9220_resources[] = {
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[0] = {
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.start = 0x14000000, /* CS5A */
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.end = 0x140000ff, /* A1->A7 */
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gic_spi(33), /* PINTA2 @ PORT144 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct smsc911x_platform_config smsc9220_platdata = {
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.flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
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.phy_interface = PHY_INTERFACE_MODE_MII,
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
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};
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static struct platform_device eth_device = {
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.name = "smsc911x",
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.id = 0,
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.dev = {
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.platform_data = &smsc9220_platdata,
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},
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.resource = smsc9220_resources,
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.num_resources = ARRAY_SIZE(smsc9220_resources),
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};
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static struct sh_keysc_info keysc_platdata = {
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.mode = SH_KEYSC_MODE_6,
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.scan_timing = 3,
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.delay = 100,
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.keycodes = {
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KEY_NUMERIC_STAR, KEY_NUMERIC_0, KEY_NUMERIC_POUND,
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0, 0, 0, 0, 0,
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KEY_NUMERIC_7, KEY_NUMERIC_8, KEY_NUMERIC_9,
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0, KEY_DOWN, 0, 0, 0,
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KEY_NUMERIC_4, KEY_NUMERIC_5, KEY_NUMERIC_6,
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KEY_LEFT, KEY_ENTER, KEY_RIGHT, 0, 0,
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KEY_NUMERIC_1, KEY_NUMERIC_2, KEY_NUMERIC_3,
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0, KEY_UP, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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},
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};
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static struct resource keysc_resources[] = {
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[0] = {
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.name = "KEYSC",
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.start = 0xe61b0000,
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.end = 0xe61b0098 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gic_spi(71),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device keysc_device = {
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.name = "sh_keysc",
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.id = 0,
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.num_resources = ARRAY_SIZE(keysc_resources),
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.resource = keysc_resources,
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.dev = {
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.platform_data = &keysc_platdata,
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},
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};
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#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
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static struct gpio_keys_button gpio_buttons[] = {
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GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */
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GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */
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GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */
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||||
GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */
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||||
GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */
|
||||
GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */
|
||||
GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */
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||||
GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */
|
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/* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */
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||||
GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */
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||||
/* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */
|
||||
};
|
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||||
static struct gpio_keys_platform_data gpio_key_info = {
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||||
.buttons = gpio_buttons,
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||||
.nbuttons = ARRAY_SIZE(gpio_buttons),
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||||
.poll_interval = 250, /* polled for now */
|
||||
};
|
||||
|
||||
static struct platform_device gpio_keys_device = {
|
||||
.name = "gpio-keys-polled", /* polled for now */
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &gpio_key_info,
|
||||
},
|
||||
};
|
||||
|
||||
#define GPIO_LED(n, g) { .name = n, .gpio = g }
|
||||
|
||||
static struct gpio_led gpio_leds[] = {
|
||||
GPIO_LED("V2513", GPIO_PORT153), /* PORT153 [TPU1T02] -> V2513 */
|
||||
GPIO_LED("V2514", GPIO_PORT199), /* PORT199 [TPU4TO1] -> V2514 */
|
||||
GPIO_LED("V2515", GPIO_PORT197), /* PORT197 [TPU2TO1] -> V2515 */
|
||||
GPIO_LED("KEYLED", GPIO_PORT163), /* PORT163 [TPU3TO0] -> KEYLED */
|
||||
GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */
|
||||
GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */
|
||||
GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data gpio_leds_info = {
|
||||
.leds = gpio_leds,
|
||||
.num_leds = ARRAY_SIZE(gpio_leds),
|
||||
};
|
||||
|
||||
static struct platform_device gpio_leds_device = {
|
||||
.name = "leds-gpio",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &gpio_leds_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource mmcif_resources[] = {
|
||||
[0] = {
|
||||
.name = "MMCIF",
|
||||
.start = 0xe6bd0000,
|
||||
.end = 0xe6bd00ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(140),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = gic_spi(141),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_mmcif_plat_data mmcif_info = {
|
||||
.ocr = MMC_VDD_165_195,
|
||||
.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
|
||||
};
|
||||
|
||||
static struct platform_device mmcif_device = {
|
||||
.name = "sh_mmcif",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &mmcif_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(mmcif_resources),
|
||||
.resource = mmcif_resources,
|
||||
};
|
||||
|
||||
static struct sh_mobile_sdhi_info sdhi0_info = {
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
|
||||
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
|
||||
};
|
||||
|
||||
static struct resource sdhi0_resources[] = {
|
||||
[0] = {
|
||||
.name = "SDHI0",
|
||||
.start = 0xee100000,
|
||||
.end = 0xee1000ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(83),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = gic_spi(84),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
.start = gic_spi(85),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device sdhi0_device = {
|
||||
.name = "sh_mobile_sdhi",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(sdhi0_resources),
|
||||
.resource = sdhi0_resources,
|
||||
.dev = {
|
||||
.platform_data = &sdhi0_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_mobile_sdhi_info sdhi1_info = {
|
||||
.tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
|
||||
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
|
||||
};
|
||||
|
||||
static struct resource sdhi1_resources[] = {
|
||||
[0] = {
|
||||
.name = "SDHI1",
|
||||
.start = 0xee120000,
|
||||
.end = 0xee1200ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(87),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = gic_spi(88),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
.start = gic_spi(89),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device sdhi1_device = {
|
||||
.name = "sh_mobile_sdhi",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(sdhi1_resources),
|
||||
.resource = sdhi1_resources,
|
||||
.dev = {
|
||||
.platform_data = &sdhi1_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *kota2_devices[] __initdata = {
|
||||
ð_device,
|
||||
&keysc_device,
|
||||
&gpio_keys_device,
|
||||
&gpio_leds_device,
|
||||
&mmcif_device,
|
||||
&sdhi0_device,
|
||||
&sdhi1_device,
|
||||
};
|
||||
|
||||
static struct map_desc kota2_io_desc[] __initdata = {
|
||||
/* create a 1:1 entity map for 0xe6xxxxxx
|
||||
* used by CPGA, INTC and PFC.
|
||||
*/
|
||||
{
|
||||
.virtual = 0xe6000000,
|
||||
.pfn = __phys_to_pfn(0xe6000000),
|
||||
.length = 256 << 20,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
},
|
||||
};
|
||||
|
||||
static void __init kota2_map_io(void)
|
||||
{
|
||||
iotable_init(kota2_io_desc, ARRAY_SIZE(kota2_io_desc));
|
||||
|
||||
/* setup early devices and console here as well */
|
||||
sh73a0_add_early_devices();
|
||||
shmobile_setup_console();
|
||||
}
|
||||
|
||||
#define PINTER0A 0xe69000a0
|
||||
#define PINTCR0A 0xe69000b0
|
||||
|
||||
void __init kota2_init_irq(void)
|
||||
{
|
||||
sh73a0_init_irq();
|
||||
|
||||
/* setup PINT: enable PINTA2 as active low */
|
||||
__raw_writel(1 << 29, PINTER0A);
|
||||
__raw_writew(2 << 10, PINTCR0A);
|
||||
}
|
||||
|
||||
static void __init kota2_init(void)
|
||||
{
|
||||
sh73a0_pinmux_init();
|
||||
|
||||
/* SCIFA2 (UART2) */
|
||||
gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
|
||||
|
||||
/* SCIFA4 (UART1) */
|
||||
gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
|
||||
|
||||
/* SMSC911X */
|
||||
gpio_request(GPIO_FN_D0_NAF0, NULL);
|
||||
gpio_request(GPIO_FN_D1_NAF1, NULL);
|
||||
gpio_request(GPIO_FN_D2_NAF2, NULL);
|
||||
gpio_request(GPIO_FN_D3_NAF3, NULL);
|
||||
gpio_request(GPIO_FN_D4_NAF4, NULL);
|
||||
gpio_request(GPIO_FN_D5_NAF5, NULL);
|
||||
gpio_request(GPIO_FN_D6_NAF6, NULL);
|
||||
gpio_request(GPIO_FN_D7_NAF7, NULL);
|
||||
gpio_request(GPIO_FN_D8_NAF8, NULL);
|
||||
gpio_request(GPIO_FN_D9_NAF9, NULL);
|
||||
gpio_request(GPIO_FN_D10_NAF10, NULL);
|
||||
gpio_request(GPIO_FN_D11_NAF11, NULL);
|
||||
gpio_request(GPIO_FN_D12_NAF12, NULL);
|
||||
gpio_request(GPIO_FN_D13_NAF13, NULL);
|
||||
gpio_request(GPIO_FN_D14_NAF14, NULL);
|
||||
gpio_request(GPIO_FN_D15_NAF15, NULL);
|
||||
gpio_request(GPIO_FN_CS5A_, NULL);
|
||||
gpio_request(GPIO_FN_WE0__FWE, NULL);
|
||||
gpio_request(GPIO_PORT144, NULL); /* PINTA2 */
|
||||
gpio_direction_input(GPIO_PORT144);
|
||||
gpio_request(GPIO_PORT145, NULL); /* RESET */
|
||||
gpio_direction_output(GPIO_PORT145, 1);
|
||||
|
||||
/* KEYSC */
|
||||
gpio_request(GPIO_FN_KEYIN0_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN1_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN2_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN3_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN4_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN5_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN6_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN7_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT0, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT1, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT2, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT3, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT4, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT5, NULL);
|
||||
gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
|
||||
gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT8, NULL);
|
||||
|
||||
/* MMCIF */
|
||||
gpio_request(GPIO_FN_MMCCLK0, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_0, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_1, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_2, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_3, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_4, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_5, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_6, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_7, NULL);
|
||||
gpio_request(GPIO_FN_MMCCMD0, NULL);
|
||||
gpio_request(GPIO_PORT208, NULL); /* Reset */
|
||||
gpio_direction_output(GPIO_PORT208, 1);
|
||||
|
||||
/* SDHI0 (microSD) */
|
||||
gpio_request(GPIO_FN_SDHICD0_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD0_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK0, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_3_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_2_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
|
||||
|
||||
/* SCIFB (BT) */
|
||||
gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL);
|
||||
gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL);
|
||||
gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL);
|
||||
gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL);
|
||||
gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL);
|
||||
|
||||
/* SDHI1 (BCM4330) */
|
||||
gpio_request(GPIO_FN_SDHICLK1, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
|
||||
l2x0_init(__io(0xf0100000), 0x40460000, 0x82000fff);
|
||||
#endif
|
||||
sh73a0_add_standard_devices();
|
||||
platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
|
||||
}
|
||||
|
||||
static void __init kota2_timer_init(void)
|
||||
{
|
||||
sh73a0_clock_init();
|
||||
shmobile_timer.init();
|
||||
return;
|
||||
}
|
||||
|
||||
struct sys_timer kota2_timer = {
|
||||
.init = kota2_timer_init,
|
||||
};
|
||||
|
||||
MACHINE_START(KOTA2, "kota2")
|
||||
.map_io = kota2_map_io,
|
||||
.init_irq = kota2_init_irq,
|
||||
.handle_irq = shmobile_handle_irq_gic,
|
||||
.init_machine = kota2_init,
|
||||
.timer = &kota2_timer,
|
||||
MACHINE_END
|
||||
|
|
@ -273,8 +273,8 @@ static struct physmap_flash_data nor_flash_data = {
|
|||
|
||||
static struct resource nor_flash_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x00000000,
|
||||
.end = 0x08000000 - 1,
|
||||
.start = 0x20000000, /* CS0 shadow instead of regular CS0 */
|
||||
.end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,246 @@
|
|||
#ifndef __ASM_MACH_INTC_H
|
||||
#define __ASM_MACH_INTC_H
|
||||
#include <linux/sh_intc.h>
|
||||
|
||||
#define INTC_IRQ_PINS_ENUM_16L(p) \
|
||||
p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
|
||||
p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7, \
|
||||
p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
|
||||
p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15
|
||||
|
||||
#define INTC_IRQ_PINS_ENUM_16H(p) \
|
||||
p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
|
||||
p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23, \
|
||||
p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
|
||||
p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31
|
||||
|
||||
#define INTC_IRQ_PINS_VECT_16L(p, vect) \
|
||||
vect(p ## _IRQ0, 0x0200), vect(p ## _IRQ1, 0x0220), \
|
||||
vect(p ## _IRQ2, 0x0240), vect(p ## _IRQ3, 0x0260), \
|
||||
vect(p ## _IRQ4, 0x0280), vect(p ## _IRQ5, 0x02a0), \
|
||||
vect(p ## _IRQ6, 0x02c0), vect(p ## _IRQ7, 0x02e0), \
|
||||
vect(p ## _IRQ8, 0x0300), vect(p ## _IRQ9, 0x0320), \
|
||||
vect(p ## _IRQ10, 0x0340), vect(p ## _IRQ11, 0x0360), \
|
||||
vect(p ## _IRQ12, 0x0380), vect(p ## _IRQ13, 0x03a0), \
|
||||
vect(p ## _IRQ14, 0x03c0), vect(p ## _IRQ15, 0x03e0)
|
||||
|
||||
#define INTC_IRQ_PINS_VECT_16H(p, vect) \
|
||||
vect(p ## _IRQ16, 0x3200), vect(p ## _IRQ17, 0x3220), \
|
||||
vect(p ## _IRQ18, 0x3240), vect(p ## _IRQ19, 0x3260), \
|
||||
vect(p ## _IRQ20, 0x3280), vect(p ## _IRQ21, 0x32a0), \
|
||||
vect(p ## _IRQ22, 0x32c0), vect(p ## _IRQ23, 0x32e0), \
|
||||
vect(p ## _IRQ24, 0x3300), vect(p ## _IRQ25, 0x3320), \
|
||||
vect(p ## _IRQ26, 0x3340), vect(p ## _IRQ27, 0x3360), \
|
||||
vect(p ## _IRQ28, 0x3380), vect(p ## _IRQ29, 0x33a0), \
|
||||
vect(p ## _IRQ30, 0x33c0), vect(p ## _IRQ31, 0x33e0)
|
||||
|
||||
#define INTC_IRQ_PINS_MASK_16L(p, base) \
|
||||
{ base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A */ \
|
||||
{ p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
|
||||
p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
|
||||
{ base + 0x44, base + 0x64, 8, /* INTMSK10A / INTMSKCLR10A */ \
|
||||
{ p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
|
||||
p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
|
||||
|
||||
#define INTC_IRQ_PINS_MASK_16H(p, base) \
|
||||
{ base + 0x48, base + 0x68, 8, /* INTMSK20A / INTMSKCLR20A */ \
|
||||
{ p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
|
||||
p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
|
||||
{ base + 0x4c, base + 0x6c, 8, /* INTMSK30A / INTMSKCLR30A */ \
|
||||
{ p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
|
||||
p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
|
||||
|
||||
#define INTC_IRQ_PINS_PRIO_16L(p, base) \
|
||||
{ base + 0x10, 0, 32, 4, /* INTPRI00A */ \
|
||||
{ p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
|
||||
p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
|
||||
{ base + 0x14, 0, 32, 4, /* INTPRI10A */ \
|
||||
{ p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
|
||||
p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
|
||||
|
||||
#define INTC_IRQ_PINS_PRIO_16H(p, base) \
|
||||
{ base + 0x18, 0, 32, 4, /* INTPRI20A */ \
|
||||
{ p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
|
||||
p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
|
||||
{ base + 0x1c, 0, 32, 4, /* INTPRI30A */ \
|
||||
{ p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
|
||||
p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
|
||||
|
||||
#define INTC_IRQ_PINS_SENSE_16L(p, base) \
|
||||
{ base + 0x00, 32, 4, /* ICR1A */ \
|
||||
{ p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
|
||||
p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
|
||||
{ base + 0x04, 32, 4, /* ICR2A */ \
|
||||
{ p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
|
||||
p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
|
||||
|
||||
#define INTC_IRQ_PINS_SENSE_16H(p, base) \
|
||||
{ base + 0x08, 32, 4, /* ICR3A */ \
|
||||
{ p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
|
||||
p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
|
||||
{ base + 0x0c, 32, 4, /* ICR4A */ \
|
||||
{ p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
|
||||
p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
|
||||
|
||||
#define INTC_IRQ_PINS_ACK_16L(p, base) \
|
||||
{ base + 0x20, 0, 8, /* INTREQ00A */ \
|
||||
{ p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
|
||||
p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
|
||||
{ base + 0x24, 0, 8, /* INTREQ10A */ \
|
||||
{ p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
|
||||
p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
|
||||
|
||||
#define INTC_IRQ_PINS_ACK_16H(p, base) \
|
||||
{ base + 0x28, 0, 8, /* INTREQ20A */ \
|
||||
{ p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
|
||||
p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
|
||||
{ base + 0x2c, 0, 8, /* INTREQ30A */ \
|
||||
{ p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
|
||||
p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
|
||||
|
||||
#define INTC_IRQ_PINS_16(p, base, vect, str) \
|
||||
\
|
||||
static struct resource p ## _resources[] __initdata = { \
|
||||
[0] = { \
|
||||
.start = base, \
|
||||
.end = base + 0x64, \
|
||||
.flags = IORESOURCE_MEM, \
|
||||
}, \
|
||||
}; \
|
||||
\
|
||||
enum { \
|
||||
p ## _UNUSED = 0, \
|
||||
INTC_IRQ_PINS_ENUM_16L(p), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_vect p ## _vectors[] __initdata = { \
|
||||
INTC_IRQ_PINS_VECT_16L(p, vect), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
|
||||
INTC_IRQ_PINS_MASK_16L(p, base), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
|
||||
INTC_IRQ_PINS_PRIO_16L(p, base), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
|
||||
INTC_IRQ_PINS_SENSE_16L(p, base), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
|
||||
INTC_IRQ_PINS_ACK_16L(p, base), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_desc p ## _desc __initdata = { \
|
||||
.name = str, \
|
||||
.resource = p ## _resources, \
|
||||
.num_resources = ARRAY_SIZE(p ## _resources), \
|
||||
.hw = INTC_HW_DESC(p ## _vectors, NULL, \
|
||||
p ## _mask_registers, p ## _prio_registers, \
|
||||
p ## _sense_registers, p ## _ack_registers) \
|
||||
}
|
||||
|
||||
#define INTC_IRQ_PINS_32(p, base, vect, str) \
|
||||
\
|
||||
static struct resource p ## _resources[] __initdata = { \
|
||||
[0] = { \
|
||||
.start = base, \
|
||||
.end = base + 0x6c, \
|
||||
.flags = IORESOURCE_MEM, \
|
||||
}, \
|
||||
}; \
|
||||
\
|
||||
enum { \
|
||||
p ## _UNUSED = 0, \
|
||||
INTC_IRQ_PINS_ENUM_16L(p), \
|
||||
INTC_IRQ_PINS_ENUM_16H(p), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_vect p ## _vectors[] __initdata = { \
|
||||
INTC_IRQ_PINS_VECT_16L(p, vect), \
|
||||
INTC_IRQ_PINS_VECT_16H(p, vect), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
|
||||
INTC_IRQ_PINS_MASK_16L(p, base), \
|
||||
INTC_IRQ_PINS_MASK_16H(p, base), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
|
||||
INTC_IRQ_PINS_PRIO_16L(p, base), \
|
||||
INTC_IRQ_PINS_PRIO_16H(p, base), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
|
||||
INTC_IRQ_PINS_SENSE_16L(p, base), \
|
||||
INTC_IRQ_PINS_SENSE_16H(p, base), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
|
||||
INTC_IRQ_PINS_ACK_16L(p, base), \
|
||||
INTC_IRQ_PINS_ACK_16H(p, base), \
|
||||
}; \
|
||||
\
|
||||
static struct intc_desc p ## _desc __initdata = { \
|
||||
.name = str, \
|
||||
.resource = p ## _resources, \
|
||||
.num_resources = ARRAY_SIZE(p ## _resources), \
|
||||
.hw = INTC_HW_DESC(p ## _vectors, NULL, \
|
||||
p ## _mask_registers, p ## _prio_registers, \
|
||||
p ## _sense_registers, p ## _ack_registers) \
|
||||
}
|
||||
|
||||
#define INTC_PINT_E_EMPTY
|
||||
#define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
#define INTC_PINT_E(p) \
|
||||
PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \
|
||||
PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7,
|
||||
|
||||
#define INTC_PINT_V_NONE
|
||||
#define INTC_PINT_V(p, vect) \
|
||||
vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1), \
|
||||
vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3), \
|
||||
vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5), \
|
||||
vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7),
|
||||
|
||||
#define INTC_PINT(p, mask_reg, sense_base, str, \
|
||||
enums_1, enums_2, enums_3, enums_4, \
|
||||
vect_1, vect_2, vect_3, vect_4, \
|
||||
mask_a, mask_b, mask_c, mask_d, \
|
||||
sense_a, sense_b, sense_c, sense_d) \
|
||||
\
|
||||
enum { \
|
||||
PINT ## p ## _UNUSED = 0, \
|
||||
enums_1 enums_2 enums_3 enums_4 \
|
||||
}; \
|
||||
\
|
||||
static struct intc_vect p ## _vectors[] __initdata = { \
|
||||
vect_1 vect_2 vect_3 vect_4 \
|
||||
}; \
|
||||
\
|
||||
static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
|
||||
{ mask_reg, 0, 32, /* PINTER */ \
|
||||
{ mask_a mask_b mask_c mask_d } } \
|
||||
}; \
|
||||
\
|
||||
static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
|
||||
{ sense_base + 0x00, 16, 2, /* PINTCR */ \
|
||||
{ sense_a } }, \
|
||||
{ sense_base + 0x04, 16, 2, /* PINTCR */ \
|
||||
{ sense_b } }, \
|
||||
{ sense_base + 0x08, 16, 2, /* PINTCR */ \
|
||||
{ sense_c } }, \
|
||||
{ sense_base + 0x0c, 16, 2, /* PINTCR */ \
|
||||
{ sense_d } }, \
|
||||
}; \
|
||||
\
|
||||
static struct intc_desc p ## _desc __initdata = { \
|
||||
.name = str, \
|
||||
.hw = INTC_HW_DESC(p ## _vectors, NULL, \
|
||||
p ## _mask_registers, NULL, \
|
||||
p ## _sense_registers, NULL), \
|
||||
}
|
||||
|
||||
#endif /* __ASM_MACH_INTC_H */
|
||||
|
|
@ -451,11 +451,23 @@ enum {
|
|||
GPIO_FN_KEYIN5_PU,
|
||||
GPIO_FN_KEYIN6_PU,
|
||||
GPIO_FN_KEYIN7_PU,
|
||||
GPIO_FN_SDHICD0_PU,
|
||||
GPIO_FN_SDHID0_0_PU,
|
||||
GPIO_FN_SDHID0_1_PU,
|
||||
GPIO_FN_SDHID0_2_PU,
|
||||
GPIO_FN_SDHID0_3_PU,
|
||||
GPIO_FN_SDHICMD0_PU,
|
||||
GPIO_FN_SDHIWP0_PU,
|
||||
GPIO_FN_SDHID1_0_PU,
|
||||
GPIO_FN_SDHID1_1_PU,
|
||||
GPIO_FN_SDHID1_2_PU,
|
||||
GPIO_FN_SDHID1_3_PU,
|
||||
GPIO_FN_SDHICMD1_PU,
|
||||
GPIO_FN_SDHID2_0_PU,
|
||||
GPIO_FN_SDHID2_1_PU,
|
||||
GPIO_FN_SDHID2_2_PU,
|
||||
GPIO_FN_SDHID2_3_PU,
|
||||
GPIO_FN_SDHICMD2_PU,
|
||||
GPIO_FN_MMCCMD0_PU,
|
||||
GPIO_FN_MMCCMD1_PU,
|
||||
GPIO_FN_FSIACK_PU,
|
||||
|
|
@ -463,6 +475,7 @@ enum {
|
|||
GPIO_FN_FSIAIBT_PU,
|
||||
GPIO_FN_FSIAISLD_PU,
|
||||
};
|
||||
|
||||
/* DMA slave IDs */
|
||||
enum {
|
||||
SHDMA_SLAVE_INVALID,
|
||||
|
|
@ -494,4 +507,8 @@ enum {
|
|||
SHDMA_SLAVE_MMCIF_RX,
|
||||
};
|
||||
|
||||
/* PINT interrupts are located at Linux IRQ 768 and up */
|
||||
#define SH73A0_PINT0_IRQ(irq) ((irq) + 768)
|
||||
#define SH73A0_PINT1_IRQ(irq) ((irq) + 800)
|
||||
|
||||
#endif /* __ASM_SH73A0_H__ */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <mach/intc.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
|
|
@ -31,8 +32,6 @@ enum {
|
|||
DISABLED,
|
||||
|
||||
/* interrupt sources INTCA */
|
||||
IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
|
||||
IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
|
||||
DIRC,
|
||||
CRYPT1_ERR, CRYPT2_STD,
|
||||
IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
|
||||
|
|
@ -76,14 +75,6 @@ enum {
|
|||
};
|
||||
|
||||
static struct intc_vect intca_vectors[] __initdata = {
|
||||
INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
|
||||
INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
|
||||
INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
|
||||
INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
|
||||
INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
|
||||
INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
|
||||
INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
|
||||
INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
|
||||
INTC_VECT(DIRC, 0x0560),
|
||||
INTC_VECT(CRYPT1_ERR, 0x05e0),
|
||||
INTC_VECT(CRYPT2_STD, 0x0700),
|
||||
|
|
@ -163,10 +154,6 @@ static struct intc_group intca_groups[] __initdata = {
|
|||
};
|
||||
|
||||
static struct intc_mask_reg intca_mask_registers[] __initdata = {
|
||||
{ 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
{ 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
|
||||
{ DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
|
||||
ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
|
||||
|
|
@ -212,11 +199,6 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
|
|||
};
|
||||
|
||||
static struct intc_prio_reg intca_prio_registers[] __initdata = {
|
||||
{ 0xe6900010, 0, 32, 4, /* INTPRI00A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900014, 0, 32, 4, /* INTPRI10A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
|
||||
{ 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
|
||||
{ 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
|
||||
{ 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
|
||||
|
|
@ -240,29 +222,18 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
|
|||
{ 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
|
||||
};
|
||||
|
||||
static struct intc_sense_reg intca_sense_registers[] __initdata = {
|
||||
{ 0xe6900000, 16, 2, /* ICR1A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900004, 16, 2, /* ICR2A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg intca_ack_registers[] __initdata = {
|
||||
{ 0xe6900020, 0, 8, /* INTREQ00A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900024, 0, 8, /* INTREQ10A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
};
|
||||
|
||||
static struct intc_desc intca_desc __initdata = {
|
||||
.name = "sh7367-intca",
|
||||
.force_enable = ENABLED,
|
||||
.force_disable = DISABLED,
|
||||
.hw = INTC_HW_DESC(intca_vectors, intca_groups,
|
||||
intca_mask_registers, intca_prio_registers,
|
||||
intca_sense_registers, intca_ack_registers),
|
||||
NULL, NULL),
|
||||
};
|
||||
|
||||
INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000,
|
||||
INTC_VECT, "sh7367-intca-irq-pins");
|
||||
|
||||
enum {
|
||||
UNUSED_INTCS = 0,
|
||||
|
||||
|
|
@ -432,6 +403,7 @@ void __init sh7367_init_irq(void)
|
|||
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
|
||||
|
||||
register_intc_controller(&intca_desc);
|
||||
register_intc_controller(&intca_irq_pins_desc);
|
||||
register_intc_controller(&intcs_desc);
|
||||
|
||||
/* demux using INTEVTSA */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <mach/intc.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
|
|
@ -29,10 +30,6 @@ enum {
|
|||
UNUSED_INTCA = 0,
|
||||
|
||||
/* interrupt sources INTCA */
|
||||
IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
|
||||
IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
|
||||
IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
|
||||
IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
|
||||
DIRC,
|
||||
CRYPT_STD,
|
||||
IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
|
||||
|
|
@ -86,22 +83,6 @@ enum {
|
|||
};
|
||||
|
||||
static struct intc_vect intca_vectors[] __initdata = {
|
||||
INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
|
||||
INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
|
||||
INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
|
||||
INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
|
||||
INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
|
||||
INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
|
||||
INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
|
||||
INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
|
||||
INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
|
||||
INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
|
||||
INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ21A, 0x32a0),
|
||||
INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
|
||||
INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
|
||||
INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
|
||||
INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
|
||||
INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
|
||||
INTC_VECT(DIRC, 0x0560),
|
||||
INTC_VECT(CRYPT_STD, 0x0700),
|
||||
INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
|
||||
|
|
@ -203,15 +184,6 @@ static struct intc_group intca_groups[] __initdata = {
|
|||
};
|
||||
|
||||
static struct intc_mask_reg intca_mask_registers[] __initdata = {
|
||||
{ 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
{ 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
|
||||
{ IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
|
||||
{ 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
|
||||
{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
|
||||
|
||||
{ 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
|
||||
{ DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
|
||||
AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
|
||||
|
|
@ -282,15 +254,6 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
|
|||
};
|
||||
|
||||
static struct intc_prio_reg intca_prio_registers[] __initdata = {
|
||||
{ 0xe6900010, 0, 32, 4, /* INTPRI00A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900014, 0, 32, 4, /* INTPRI10A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
{ 0xe6900018, 0, 32, 4, /* INTPRI20A */
|
||||
{ IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
|
||||
{ 0xe690001c, 0, 32, 4, /* INTPRI30A */
|
||||
{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
|
||||
|
||||
{ 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
|
||||
{ 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
|
||||
{ 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
|
||||
|
|
@ -336,33 +299,13 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
|
|||
{ 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static struct intc_sense_reg intca_sense_registers[] __initdata = {
|
||||
{ 0xe6900000, 32, 4, /* ICR1A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900004, 32, 4, /* ICR2A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
{ 0xe6900008, 32, 4, /* ICR3A */
|
||||
{ IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
|
||||
{ 0xe690000c, 32, 4, /* ICR4A */
|
||||
{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg intca_ack_registers[] __initdata = {
|
||||
{ 0xe6900020, 0, 8, /* INTREQ00A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900024, 0, 8, /* INTREQ10A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
{ 0xe6900028, 0, 8, /* INTREQ20A */
|
||||
{ IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
|
||||
{ 0xe690002c, 0, 8, /* INTREQ30A */
|
||||
{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
|
||||
intca_vectors, intca_groups,
|
||||
intca_mask_registers, intca_prio_registers,
|
||||
intca_sense_registers, intca_ack_registers);
|
||||
static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
|
||||
intca_vectors, intca_groups,
|
||||
intca_mask_registers, intca_prio_registers,
|
||||
NULL);
|
||||
|
||||
INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
|
||||
INTC_VECT, "sh7372-intca-irq-pins");
|
||||
enum {
|
||||
UNUSED_INTCS = 0,
|
||||
ENABLED_INTCS,
|
||||
|
|
@ -618,6 +561,7 @@ void __init sh7372_init_irq(void)
|
|||
intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
|
||||
|
||||
register_intc_controller(&intca_desc);
|
||||
register_intc_controller(&intca_irq_pins_desc);
|
||||
register_intc_controller(&intcs_desc);
|
||||
|
||||
/* demux using INTEVTSA */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <mach/intc.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
|
|
@ -31,10 +32,6 @@ enum {
|
|||
DISABLED,
|
||||
|
||||
/* interrupt sources INTCA */
|
||||
IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
|
||||
IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
|
||||
IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
|
||||
IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
|
||||
DIRC,
|
||||
_2DG,
|
||||
CRYPT_STD,
|
||||
|
|
@ -91,22 +88,6 @@ enum {
|
|||
};
|
||||
|
||||
static struct intc_vect intca_vectors[] __initdata = {
|
||||
INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
|
||||
INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
|
||||
INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
|
||||
INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
|
||||
INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
|
||||
INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
|
||||
INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
|
||||
INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
|
||||
INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
|
||||
INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
|
||||
INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0),
|
||||
INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
|
||||
INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
|
||||
INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
|
||||
INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
|
||||
INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
|
||||
INTC_VECT(DIRC, 0x0560),
|
||||
INTC_VECT(_2DG, 0x05e0),
|
||||
INTC_VECT(CRYPT_STD, 0x0700),
|
||||
|
|
@ -203,15 +184,6 @@ static struct intc_group intca_groups[] __initdata = {
|
|||
};
|
||||
|
||||
static struct intc_mask_reg intca_mask_registers[] __initdata = {
|
||||
{ 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
{ 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
|
||||
{ IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
|
||||
{ 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
|
||||
{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
|
||||
|
||||
{ 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
|
||||
{ DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
|
||||
AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
|
||||
|
|
@ -273,15 +245,6 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
|
|||
};
|
||||
|
||||
static struct intc_prio_reg intca_prio_registers[] __initdata = {
|
||||
{ 0xe6900010, 0, 32, 4, /* INTPRI00A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900014, 0, 32, 4, /* INTPRI10A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
{ 0xe6900018, 0, 32, 4, /* INTPRI10A */
|
||||
{ IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
|
||||
{ 0xe690001c, 0, 32, 4, /* INTPRI30A */
|
||||
{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
|
||||
|
||||
{ 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
|
||||
{ 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
|
||||
{ 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD,
|
||||
|
|
@ -315,37 +278,18 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
|
|||
{ 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static struct intc_sense_reg intca_sense_registers[] __initdata = {
|
||||
{ 0xe6900000, 16, 2, /* ICR1A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900004, 16, 2, /* ICR2A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
{ 0xe6900008, 16, 2, /* ICR3A */
|
||||
{ IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
|
||||
{ 0xe690000c, 16, 2, /* ICR4A */
|
||||
{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg intca_ack_registers[] __initdata = {
|
||||
{ 0xe6900020, 0, 8, /* INTREQ00A */
|
||||
{ IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
|
||||
{ 0xe6900024, 0, 8, /* INTREQ10A */
|
||||
{ IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
|
||||
{ 0xe6900028, 0, 8, /* INTREQ20A */
|
||||
{ IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
|
||||
{ 0xe690002c, 0, 8, /* INTREQ30A */
|
||||
{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
|
||||
};
|
||||
|
||||
static struct intc_desc intca_desc __initdata = {
|
||||
.name = "sh7377-intca",
|
||||
.force_enable = ENABLED,
|
||||
.force_disable = DISABLED,
|
||||
.hw = INTC_HW_DESC(intca_vectors, intca_groups,
|
||||
intca_mask_registers, intca_prio_registers,
|
||||
intca_sense_registers, intca_ack_registers),
|
||||
NULL, NULL),
|
||||
};
|
||||
|
||||
INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
|
||||
INTC_VECT, "sh7377-intca-irq-pins");
|
||||
|
||||
/* this macro ignore entry which is also in INTCA */
|
||||
#define __IGNORE(a...)
|
||||
#define __IGNORE0(a...) 0
|
||||
|
|
@ -638,6 +582,7 @@ void __init sh7377_init_irq(void)
|
|||
void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
|
||||
|
||||
register_intc_controller(&intca_desc);
|
||||
register_intc_controller(&intca_irq_pins_desc);
|
||||
register_intc_controller(&intcs_desc);
|
||||
|
||||
/* demux using INTEVTSA */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <mach/intc.h>
|
||||
#include <mach/sh73a0.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
|
@ -255,20 +257,205 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
|
|||
return 0; /* always allow wakeup */
|
||||
}
|
||||
|
||||
#define RELOC_BASE 0x1000
|
||||
|
||||
/* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */
|
||||
#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
|
||||
|
||||
INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
|
||||
INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
|
||||
|
||||
static int to_gic_irq(struct irq_data *data)
|
||||
{
|
||||
unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
|
||||
|
||||
if (vect >= 0x3200)
|
||||
vect -= 0x3000;
|
||||
else
|
||||
vect -= 0x0200;
|
||||
|
||||
return gic_spi((vect >> 5) + 1);
|
||||
}
|
||||
|
||||
static int to_intca_reloc_irq(struct irq_data *data)
|
||||
{
|
||||
return data->irq + (RELOC_BASE >> 5);
|
||||
}
|
||||
|
||||
#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
|
||||
#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
|
||||
|
||||
static void intca_gic_enable(struct irq_data *data)
|
||||
{
|
||||
irq_cb(irq_unmask, to_intca_reloc_irq(data));
|
||||
irq_cb(irq_unmask, to_gic_irq(data));
|
||||
}
|
||||
|
||||
static void intca_gic_disable(struct irq_data *data)
|
||||
{
|
||||
irq_cb(irq_mask, to_gic_irq(data));
|
||||
irq_cb(irq_mask, to_intca_reloc_irq(data));
|
||||
}
|
||||
|
||||
static void intca_gic_mask_ack(struct irq_data *data)
|
||||
{
|
||||
irq_cb(irq_mask, to_gic_irq(data));
|
||||
irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
|
||||
}
|
||||
|
||||
static void intca_gic_eoi(struct irq_data *data)
|
||||
{
|
||||
irq_cb(irq_eoi, to_gic_irq(data));
|
||||
}
|
||||
|
||||
static int intca_gic_set_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
|
||||
}
|
||||
|
||||
static int intca_gic_set_wake(struct irq_data *data, unsigned int on)
|
||||
{
|
||||
return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int intca_gic_set_affinity(struct irq_data *data,
|
||||
const struct cpumask *cpumask,
|
||||
bool force)
|
||||
{
|
||||
return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
|
||||
}
|
||||
#endif
|
||||
|
||||
struct irq_chip intca_gic_irq_chip = {
|
||||
.name = "INTCA-GIC",
|
||||
.irq_mask = intca_gic_disable,
|
||||
.irq_unmask = intca_gic_enable,
|
||||
.irq_mask_ack = intca_gic_mask_ack,
|
||||
.irq_eoi = intca_gic_eoi,
|
||||
.irq_enable = intca_gic_enable,
|
||||
.irq_disable = intca_gic_disable,
|
||||
.irq_shutdown = intca_gic_disable,
|
||||
.irq_set_type = intca_gic_set_type,
|
||||
.irq_set_wake = intca_gic_set_wake,
|
||||
#ifdef CONFIG_SMP
|
||||
.irq_set_affinity = intca_gic_set_affinity,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int to_intc_vect(int irq)
|
||||
{
|
||||
unsigned int irq_pin = irq - gic_spi(1);
|
||||
unsigned int offs;
|
||||
|
||||
if (irq_pin < 16)
|
||||
offs = 0x0200;
|
||||
else
|
||||
offs = 0x3000;
|
||||
|
||||
return offs + (irq_pin << 5);
|
||||
}
|
||||
|
||||
static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
|
||||
{
|
||||
generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction sh73a0_irq_pin_cascade[32];
|
||||
|
||||
#define PINTER0 0xe69000a0
|
||||
#define PINTER1 0xe69000a4
|
||||
#define PINTRR0 0xe69000d0
|
||||
#define PINTRR1 0xe69000d4
|
||||
|
||||
#define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
|
||||
#define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
|
||||
#define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16))
|
||||
#define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
|
||||
#define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
|
||||
|
||||
INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0", \
|
||||
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
|
||||
INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \
|
||||
INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \
|
||||
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
|
||||
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
|
||||
|
||||
INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1", \
|
||||
INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
|
||||
INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \
|
||||
INTC_PINT_V_NONE, INTC_PINT_V_NONE, \
|
||||
INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \
|
||||
INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE);
|
||||
|
||||
static struct irqaction sh73a0_pint0_cascade;
|
||||
static struct irqaction sh73a0_pint1_cascade;
|
||||
|
||||
static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
|
||||
{
|
||||
unsigned long value = ioread32(rr) & ioread32(er);
|
||||
int k;
|
||||
|
||||
for (k = 0; k < 32; k++) {
|
||||
if (value & (1 << (31 - k))) {
|
||||
generic_handle_irq(base_irq + k);
|
||||
iowrite32(~(1 << (31 - k)), rr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
|
||||
{
|
||||
pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0));
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
|
||||
{
|
||||
pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0));
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
void __init sh73a0_init_irq(void)
|
||||
{
|
||||
void __iomem *gic_dist_base = __io(0xf0001000);
|
||||
void __iomem *gic_cpu_base = __io(0xf0000100);
|
||||
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
|
||||
int k, n;
|
||||
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
gic_arch_extn.irq_set_wake = sh73a0_set_wake;
|
||||
|
||||
register_intc_controller(&intcs_desc);
|
||||
register_intc_controller(&intca_irq_pins_desc);
|
||||
register_intc_controller(&intc_pint0_desc);
|
||||
register_intc_controller(&intc_pint1_desc);
|
||||
|
||||
/* demux using INTEVTSA */
|
||||
sh73a0_intcs_cascade.name = "INTCS cascade";
|
||||
sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
|
||||
sh73a0_intcs_cascade.dev_id = intevtsa;
|
||||
setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
|
||||
|
||||
/* IRQ pins require special handling through INTCA and GIC */
|
||||
for (k = 0; k < 32; k++) {
|
||||
sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
|
||||
sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
|
||||
setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
|
||||
|
||||
n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
|
||||
irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
|
||||
handle_level_irq, "level");
|
||||
set_irq_flags(n, IRQF_VALID); /* yuck */
|
||||
}
|
||||
|
||||
/* PINT pins are sanely tied to the GIC as SPI */
|
||||
sh73a0_pint0_cascade.name = "PINT0 cascade";
|
||||
sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
|
||||
setup_irq(gic_spi(33), &sh73a0_pint0_cascade);
|
||||
|
||||
sh73a0_pint1_cascade.name = "PINT1 cascade";
|
||||
sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
|
||||
setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <mach/sh73a0.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#define _1(fn, pfx, sfx) fn(pfx, sfx)
|
||||
|
||||
|
|
@ -488,13 +489,26 @@ enum {
|
|||
KEYIN5_PU_MARK,
|
||||
KEYIN6_PU_MARK,
|
||||
KEYIN7_PU_MARK,
|
||||
SDHICD0_PU_MARK,
|
||||
SDHID0_0_PU_MARK,
|
||||
SDHID0_1_PU_MARK,
|
||||
SDHID0_2_PU_MARK,
|
||||
SDHID0_3_PU_MARK,
|
||||
SDHICMD0_PU_MARK,
|
||||
SDHIWP0_PU_MARK,
|
||||
SDHID1_0_PU_MARK,
|
||||
SDHID1_1_PU_MARK,
|
||||
SDHID1_2_PU_MARK,
|
||||
SDHID1_3_PU_MARK,
|
||||
SDHICMD1_PU_MARK,
|
||||
SDHID2_0_PU_MARK,
|
||||
SDHID2_1_PU_MARK,
|
||||
SDHID2_2_PU_MARK,
|
||||
SDHID2_3_PU_MARK,
|
||||
SDHICMD2_PU_MARK,
|
||||
MMCCMD0_PU_MARK,
|
||||
MMCCMD1_PU_MARK,
|
||||
FSIBISLD_PU_MARK,
|
||||
FSIACK_PU_MARK,
|
||||
FSIAILR_PU_MARK,
|
||||
FSIAIBT_PU_MARK,
|
||||
|
|
@ -1387,19 +1401,28 @@ static pinmux_enum_t pinmux_data[] = {
|
|||
PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
|
||||
PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
|
||||
PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), \
|
||||
PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
|
||||
MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
|
||||
MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
|
||||
MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
|
||||
MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
|
||||
MSEL4CR_MSEL15_0), \
|
||||
PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
|
||||
PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), \
|
||||
PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
|
||||
MSEL4CR_MSEL15_0), \
|
||||
PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
|
||||
PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), \
|
||||
PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
|
||||
MSEL4CR_MSEL15_0), \
|
||||
PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
|
||||
PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), \
|
||||
PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
|
||||
MSEL4CR_MSEL15_0), \
|
||||
PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
|
||||
PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
|
||||
MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
|
||||
PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
|
||||
PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
|
||||
|
|
@ -1516,16 +1539,29 @@ static pinmux_enum_t pinmux_data[] = {
|
|||
PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
|
||||
PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
|
||||
|
||||
PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_IN_PU, PORT259_FN1),
|
||||
PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_IN_PU, PORT260_FN1),
|
||||
PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_IN_PU, PORT261_FN1),
|
||||
PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_IN_PU, PORT262_FN1),
|
||||
PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_IN_PU, PORT263_FN1),
|
||||
PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU),
|
||||
PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU),
|
||||
PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU),
|
||||
PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
|
||||
PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
|
||||
PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
|
||||
PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU),
|
||||
PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
|
||||
PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
|
||||
PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
|
||||
PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU),
|
||||
PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU),
|
||||
PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU),
|
||||
PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU),
|
||||
PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU),
|
||||
PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU),
|
||||
PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU),
|
||||
|
||||
PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
|
||||
MSEL4CR_MSEL15_0),
|
||||
PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT279_IN_PU,
|
||||
PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
|
||||
MSEL4CR_MSEL15_1),
|
||||
PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
|
||||
PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
|
||||
PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
|
||||
PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
|
||||
|
|
@ -2181,11 +2217,23 @@ static struct pinmux_gpio pinmux_gpios[] = {
|
|||
GPIO_FN(KEYIN5_PU),
|
||||
GPIO_FN(KEYIN6_PU),
|
||||
GPIO_FN(KEYIN7_PU),
|
||||
GPIO_FN(SDHICD0_PU),
|
||||
GPIO_FN(SDHID0_0_PU),
|
||||
GPIO_FN(SDHID0_1_PU),
|
||||
GPIO_FN(SDHID0_2_PU),
|
||||
GPIO_FN(SDHID0_3_PU),
|
||||
GPIO_FN(SDHICMD0_PU),
|
||||
GPIO_FN(SDHIWP0_PU),
|
||||
GPIO_FN(SDHID1_0_PU),
|
||||
GPIO_FN(SDHID1_1_PU),
|
||||
GPIO_FN(SDHID1_2_PU),
|
||||
GPIO_FN(SDHID1_3_PU),
|
||||
GPIO_FN(SDHICMD1_PU),
|
||||
GPIO_FN(SDHID2_0_PU),
|
||||
GPIO_FN(SDHID2_1_PU),
|
||||
GPIO_FN(SDHID2_2_PU),
|
||||
GPIO_FN(SDHID2_3_PU),
|
||||
GPIO_FN(SDHICMD2_PU),
|
||||
GPIO_FN(MMCCMD0_PU),
|
||||
GPIO_FN(MMCCMD1_PU),
|
||||
GPIO_FN(FSIACK_PU),
|
||||
|
|
@ -2718,6 +2766,45 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
{ },
|
||||
};
|
||||
|
||||
/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
|
||||
#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
|
||||
#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
|
||||
|
||||
static struct pinmux_irq pinmux_irqs[] = {
|
||||
PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
|
||||
PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
|
||||
};
|
||||
|
||||
static struct pinmux_info sh73a0_pinmux_info = {
|
||||
.name = "sh73a0_pfc",
|
||||
.reserved_id = PINMUX_RESERVED,
|
||||
|
|
@ -2738,6 +2825,9 @@ static struct pinmux_info sh73a0_pinmux_info = {
|
|||
|
||||
.gpio_data = pinmux_data,
|
||||
.gpio_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
||||
.gpio_irq = pinmux_irqs,
|
||||
.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
|
||||
};
|
||||
|
||||
void sh73a0_pinmux_init(void)
|
||||
|
|
|
|||
|
|
@ -21,9 +21,11 @@
|
|||
#include <asm/mach-types.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2())
|
||||
|
||||
static unsigned int __init shmobile_smp_get_core_count(void)
|
||||
{
|
||||
if (machine_is_ag5evm())
|
||||
if (is_sh73a0())
|
||||
return sh73a0_get_core_count();
|
||||
|
||||
return 1;
|
||||
|
|
@ -31,7 +33,7 @@ static unsigned int __init shmobile_smp_get_core_count(void)
|
|||
|
||||
static void __init shmobile_smp_prepare_cpus(void)
|
||||
{
|
||||
if (machine_is_ag5evm())
|
||||
if (is_sh73a0())
|
||||
sh73a0_smp_prepare_cpus();
|
||||
}
|
||||
|
||||
|
|
@ -39,13 +41,13 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
|
|||
{
|
||||
trace_hardirqs_off();
|
||||
|
||||
if (machine_is_ag5evm())
|
||||
if (is_sh73a0())
|
||||
sh73a0_secondary_init(cpu);
|
||||
}
|
||||
|
||||
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
if (machine_is_ag5evm())
|
||||
if (is_sh73a0())
|
||||
return sh73a0_boot_secondary(cpu);
|
||||
|
||||
return -ENOSYS;
|
||||
|
|
|
|||
|
|
@ -186,7 +186,7 @@ static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
|
|||
!defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_SH7372)
|
||||
#if defined(CONFIG_ARM) /* all recent SH-Mobile / R-Mobile ARM support this */
|
||||
[IRQ_TYPE_EDGE_BOTH] = VALID(4),
|
||||
#endif
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue