[media] e4000: revise synthesizer calculation
Update synthesizer calculation to model I prefer nowadays. It is mostly just renaming some variables to ones I think are most standard. Also add 'schematic' of synthesizer following my current understanding. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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@ -115,8 +115,8 @@ static int e4000_set_params(struct dvb_frontend *fe)
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{
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{
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struct e4000 *s = fe->tuner_priv;
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struct e4000 *s = fe->tuner_priv;
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int ret, i, sigma_delta;
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int ret, i;
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unsigned int pll_n, pll_f;
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unsigned int div_n, k, k_cw, div_out;
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u64 f_vco;
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u64 f_vco;
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u8 buf[5], i_data[4], q_data[4];
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u8 buf[5], i_data[4], q_data[4];
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@ -129,7 +129,21 @@ static int e4000_set_params(struct dvb_frontend *fe)
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if (ret)
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if (ret)
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goto err;
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goto err;
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/* PLL */
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/*
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* Fractional-N synthesizer
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*
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* +----------------------------+
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* v |
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* Fref +----+ +-------+ +------+ +---+
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* ------> | PD | --> | VCO | ------> | /N.F | <-- | K |
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* +----+ +-------+ +------+ +---+
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* |
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* |
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* v
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* +-------+ Fout
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* | /Rout | ------>
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* +-------+
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*/
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for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
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for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
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if (c->frequency <= e4000_pll_lut[i].freq)
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if (c->frequency <= e4000_pll_lut[i].freq)
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break;
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break;
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@ -140,18 +154,22 @@ static int e4000_set_params(struct dvb_frontend *fe)
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goto err;
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goto err;
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}
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}
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f_vco = 1ull * c->frequency * e4000_pll_lut[i].mul;
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#define F_REF s->clock
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pll_n = div_u64_rem(f_vco, s->clock, &pll_f);
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div_out = e4000_pll_lut[i].div_out;
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sigma_delta = div_u64(0x10000ULL * pll_f, s->clock);
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f_vco = (u64) c->frequency * div_out;
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buf[0] = pll_n;
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/* calculate PLL integer and fractional control word */
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buf[1] = (sigma_delta >> 0) & 0xff;
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div_n = div_u64_rem(f_vco, F_REF, &k);
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buf[2] = (sigma_delta >> 8) & 0xff;
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k_cw = div_u64((u64) k * 0x10000, F_REF);
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dev_dbg(&s->client->dev,
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"frequency=%u f_vco=%llu F_REF=%u div_n=%u k=%u k_cw=%04x div_out=%u\n",
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c->frequency, f_vco, F_REF, div_n, k, k_cw, div_out);
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buf[0] = div_n;
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buf[1] = (k_cw >> 0) & 0xff;
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buf[2] = (k_cw >> 8) & 0xff;
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buf[3] = 0x00;
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buf[3] = 0x00;
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buf[4] = e4000_pll_lut[i].div;
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buf[4] = e4000_pll_lut[i].div_out_reg;
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dev_dbg(&s->client->dev, "f_vco=%llu pll div=%d sigma_delta=%04x\n",
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f_vco, buf[0], sigma_delta);
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ret = regmap_bulk_write(s->regmap, 0x09, buf, 5);
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ret = regmap_bulk_write(s->regmap, 0x09, buf, 5);
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if (ret)
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if (ret)
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goto err;
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goto err;
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@ -49,8 +49,8 @@ struct e4000 {
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struct e4000_pll {
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struct e4000_pll {
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u32 freq;
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u32 freq;
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u8 div;
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u8 div_out_reg;
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u8 mul;
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u8 div_out;
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};
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};
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static const struct e4000_pll e4000_pll_lut[] = {
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static const struct e4000_pll e4000_pll_lut[] = {
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