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[Blackfin] arch: relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file where it actually gets used. 

relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file
where it actually gets used.  this way when we change
CONFIG_MEM_SIZE in our kconfig, we only rebuild one or two files
rather than a whole bunch that implicitly include cplb.h.

this will also remove the ability to clear the swapcount on
the fly, but i really dont think that functionality is important.

ultimate goal is for CONFIG_MEM_SIZE to go away and calculate
this value on the fly based on what u-boot programmed for us.

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Mike Frysinger 2008-04-23 08:23:51 +08:00 committed by Bryan Wu
parent 53eabf046b
commit 0e184c6b4f
3 changed files with 23 additions and 37 deletions
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11
arch/blackfin/kernel/cplb-nompu/cplbinfo.c
View File

@ -174,16 +174,6 @@ static int cplbinfo_read_proc(char *page, char **start, off_t off,
return len; return len;
} }
static int cplbinfo_write_proc(struct file *file, const char __user *buffer,
unsigned long count, void *data)
{
printk(KERN_INFO "Reset the CPLB swap in/out counts.\n");
memset(ipdt_swapcount_table, 0, MAX_SWITCH_I_CPLBS * sizeof(unsigned long));
memset(dpdt_swapcount_table, 0, MAX_SWITCH_D_CPLBS * sizeof(unsigned long));
return count;
}
static int __init cplbinfo_init(void) static int __init cplbinfo_init(void)
{ {
struct proc_dir_entry *entry; struct proc_dir_entry *entry;
@ -193,7 +183,6 @@ static int __init cplbinfo_init(void)
return -ENOMEM; return -ENOMEM;
entry->read_proc = cplbinfo_read_proc; entry->read_proc = cplbinfo_read_proc;
entry->write_proc = cplbinfo_write_proc;
entry->data = NULL; entry->data = NULL;
return 0; return 0;

23
arch/blackfin/kernel/cplb-nompu/cplbinit.c
View File

@ -26,6 +26,29 @@
#include <asm/cplb.h> #include <asm/cplb.h>
#include <asm/cplbinit.h> #include <asm/cplbinit.h>
/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Data Memory
* possibly 1 for L2 Data Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
+ ASYNC_MEMORY_CPLB_COVERAGE) * 2)
/*
* Number of required instruction CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Instruction Memory
* possibly 1 for L2 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
u_long icplb_table[MAX_CPLBS + 1]; u_long icplb_table[MAX_CPLBS + 1];
u_long dcplb_table[MAX_CPLBS + 1]; u_long dcplb_table[MAX_CPLBS + 1];

26
include/asm-blackfin/cplb.h
View File

@ -74,32 +74,6 @@
#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ #define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Data Memory
* possibly 1 for L2 Data Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
+ ASYNC_MEMORY_CPLB_COVERAGE) * 2)
/*
* Number of required instruction CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Instruction Memory
* possibly 1 for L2 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
#define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_ICACHE_P 0
#define CPLB_ENABLE_DCACHE_P 1 #define CPLB_ENABLE_DCACHE_P 1
#define CPLB_ENABLE_DCACHE2_P 2 #define CPLB_ENABLE_DCACHE2_P 2