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OMAPDSS: DISPC: Remove dispc_mgr_set_pol_freq() 

dispc_mgr_set_pol_freq() configures the fields in the register DISPC_POL_FREQo.
All these fields have been moved to omap_video_timings struct, and are now
programmed in dispc_mgr_set_lcd_timings(). These will be configured when timings
are applied via dss_mgr_set_timings().

Remove dispc_mgr_set_pol_freq() and it's calls from the interface drivers.

Signed-off-by: Archit Taneja <archit@ti.com>
This commit is contained in:
Archit Taneja 2012-06-25 12:34:22 +05:30 committed by Tomi Valkeinen
parent 655e294116
commit 0e065c79e6
4 changed files with 0 additions and 35 deletions
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29
drivers/video/omap2/dss/dispc.c
View File

@ -3165,35 +3165,6 @@ static void dispc_dump_regs(struct seq_file *s)
#undef DUMPREG #undef DUMPREG
} }
static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
bool rf, bool ieo, bool ipc, bool ihs, bool ivs)
{
u32 l = 0;
DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d\n",
onoff, rf, ieo, ipc, ihs, ivs);
l |= FLD_VAL(onoff, 17, 17);
l |= FLD_VAL(rf, 16, 16);
l |= FLD_VAL(ieo, 15, 15);
l |= FLD_VAL(ipc, 14, 14);
l |= FLD_VAL(ihs, 13, 13);
l |= FLD_VAL(ivs, 12, 12);
dispc_write_reg(DISPC_POL_FREQ(channel), l);
}
void dispc_mgr_set_pol_freq(enum omap_channel channel,
enum omap_panel_config config)
{
_dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
(config & OMAP_DSS_LCD_RF) != 0,
(config & OMAP_DSS_LCD_IEO) != 0,
(config & OMAP_DSS_LCD_IPC) != 0,
(config & OMAP_DSS_LCD_IHS) != 0,
(config & OMAP_DSS_LCD_IVS) != 0);
}
/* with fck as input clock rate, find dispc dividers that produce req_pck */ /* with fck as input clock rate, find dispc dividers that produce req_pck */
void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck, void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
struct dispc_clock_info *cinfo) struct dispc_clock_info *cinfo)

2
drivers/video/omap2/dss/dpi.c
View File

@ -131,8 +131,6 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
unsigned long pck; unsigned long pck;
int r = 0; int r = 0;
dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config);
if (dpi_use_dsi_pll(dssdev)) if (dpi_use_dsi_pll(dssdev))
r = dpi_set_dsi_clk(dssdev, t->pixel_clock * 1000, &fck, r = dpi_set_dsi_clk(dssdev, t->pixel_clock * 1000, &fck,
&lck_div, &pck_div); &lck_div, &pck_div);

2
drivers/video/omap2/dss/dss.h
View File

@ -423,8 +423,6 @@ void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
void dispc_mgr_set_lcd_type_tft(enum omap_channel channel); void dispc_mgr_set_lcd_type_tft(enum omap_channel channel);
void dispc_mgr_set_timings(enum omap_channel channel, void dispc_mgr_set_timings(enum omap_channel channel,
struct omap_video_timings *timings); struct omap_video_timings *timings);
void dispc_mgr_set_pol_freq(enum omap_channel channel,
enum omap_panel_config config);
unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
unsigned long dispc_core_clk_rate(void); unsigned long dispc_core_clk_rate(void);

2
drivers/video/omap2/dss/sdi.c
View File

@ -83,8 +83,6 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
dssdev->panel.timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; dssdev->panel.timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
dssdev->panel.timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; dssdev->panel.timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config);
r = dss_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo); r = dss_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo);
if (r) if (r)
goto err_calc_clock_div; goto err_calc_clock_div;