OMAPDSS: DISPC: Remove dispc_mgr_set_pol_freq()
dispc_mgr_set_pol_freq() configures the fields in the register DISPC_POL_FREQo. All these fields have been moved to omap_video_timings struct, and are now programmed in dispc_mgr_set_lcd_timings(). These will be configured when timings are applied via dss_mgr_set_timings(). Remove dispc_mgr_set_pol_freq() and it's calls from the interface drivers. Signed-off-by: Archit Taneja <archit@ti.com>
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655e294116
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0e065c79e6
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@ -3165,35 +3165,6 @@ static void dispc_dump_regs(struct seq_file *s)
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#undef DUMPREG
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}
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static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
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bool rf, bool ieo, bool ipc, bool ihs, bool ivs)
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{
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u32 l = 0;
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DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d\n",
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onoff, rf, ieo, ipc, ihs, ivs);
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l |= FLD_VAL(onoff, 17, 17);
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l |= FLD_VAL(rf, 16, 16);
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l |= FLD_VAL(ieo, 15, 15);
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l |= FLD_VAL(ipc, 14, 14);
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l |= FLD_VAL(ihs, 13, 13);
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l |= FLD_VAL(ivs, 12, 12);
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dispc_write_reg(DISPC_POL_FREQ(channel), l);
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}
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void dispc_mgr_set_pol_freq(enum omap_channel channel,
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enum omap_panel_config config)
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{
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_dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
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(config & OMAP_DSS_LCD_RF) != 0,
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(config & OMAP_DSS_LCD_IEO) != 0,
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(config & OMAP_DSS_LCD_IPC) != 0,
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(config & OMAP_DSS_LCD_IHS) != 0,
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(config & OMAP_DSS_LCD_IVS) != 0);
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}
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/* with fck as input clock rate, find dispc dividers that produce req_pck */
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void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
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struct dispc_clock_info *cinfo)
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@ -131,8 +131,6 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
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unsigned long pck;
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int r = 0;
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dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config);
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if (dpi_use_dsi_pll(dssdev))
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r = dpi_set_dsi_clk(dssdev, t->pixel_clock * 1000, &fck,
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&lck_div, &pck_div);
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@ -423,8 +423,6 @@ void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
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void dispc_mgr_set_lcd_type_tft(enum omap_channel channel);
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void dispc_mgr_set_timings(enum omap_channel channel,
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struct omap_video_timings *timings);
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void dispc_mgr_set_pol_freq(enum omap_channel channel,
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enum omap_panel_config config);
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unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
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unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
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unsigned long dispc_core_clk_rate(void);
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@ -83,8 +83,6 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
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dssdev->panel.timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
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dssdev->panel.timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
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dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config);
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r = dss_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo);
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if (r)
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goto err_calc_clock_div;
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