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Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 

* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (258 commits)
  omap: zoom: host should not pull up wl1271's irq line
  arm: plat-omap: iommu: fix request_mem_region() error path
  OMAP2+: Common CPU DIE ID reading code reads wrong registers for OMAP4430
  omap4: mux: Remove duplicate mux modes
  omap: iovmm: don't check 'da' to set IOVMF_DA_FIXED flag
  omap: iovmm: disallow mapping NULL address when IOVMF_DA_ANON is set
  omap2+: mux: Fix compile when CONFIG_OMAP_MUX is not selected
  omap4: board-omap4panda: Initialise the serial pads
  omap3: board-3430sdp: Initialise the serial pads
  omap4: board-4430sdp: Initialise the serial pads
  omap2+: mux: Add macro for configuring static with omap_hwmod_mux_init
  omap2+: mux: Remove the use of IDLE flag
  omap2+: Add separate list for dynamic pads to mux
  perf: add OMAP support for the new power events
  OMAP4: Add IVA OPP enteries.
  OMAP4: Update Voltage Rail Values for MPU, IVA and CORE
  OMAP4: Enable 800 MHz and 1 GHz MPU-OPP
  OMAP3+: OPP: Replace voltage values with Macros
  OMAP3: wdtimer: Fix CORE idle transition
  Watchdog: omap_wdt: add fine grain runtime-pm
  ...

Fix up various conflicts in
 - arch/arm/mach-omap2/board-omap3evm.c
 - arch/arm/mach-omap2/clock3xxx_data.c
 - arch/arm/mach-omap2/usb-musb.c
 - arch/arm/plat-omap/include/plat/usb.h
 - drivers/usb/musb/musb_core.h
This commit is contained in:
Linus Torvalds 2011-03-17 19:28:15 -07:00
parent 6899608533 05f689400e
commit 0df0914d41
225 changed files with 18859 additions and 5079 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

293
Documentation/hwspinlock.txt Normal file
View File

@ -0,0 +1,293 @@
Hardware Spinlock Framework
1. Introduction
Hardware spinlock modules provide hardware assistance for synchronization
and mutual exclusion between heterogeneous processors and those not operating
under a single, shared operating system.
For example, OMAP4 has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP,
each of which is running a different Operating System (the master, A9,
is usually running Linux and the slave processors, the M3 and the DSP,
are running some flavor of RTOS).
A generic hwspinlock framework allows platform-independent drivers to use
the hwspinlock device in order to access data structures that are shared
between remote processors, that otherwise have no alternative mechanism
to accomplish synchronization and mutual exclusion operations.
This is necessary, for example, for Inter-processor communications:
on OMAP4, cpu-intensive multimedia tasks are offloaded by the host to the
remote M3 and/or C64x+ slave processors (by an IPC subsystem called Syslink).
To achieve fast message-based communications, a minimal kernel support
is needed to deliver messages arriving from a remote processor to the
appropriate user process.
This communication is based on simple data structures that is shared between
the remote processors, and access to it is synchronized using the hwspinlock
module (remote processor directly places new messages in this shared data
structure).
A common hwspinlock interface makes it possible to have generic, platform-
independent, drivers.
2. User API
struct hwspinlock *hwspin_lock_request(void);
- dynamically assign an hwspinlock and return its address, or NULL
in case an unused hwspinlock isn't available. Users of this
API will usually want to communicate the lock's id to the remote core
before it can be used to achieve synchronization.
Can be called from an atomic context (this function will not sleep) but
not from within interrupt context.
struct hwspinlock *hwspin_lock_request_specific(unsigned int id);
- assign a specific hwspinlock id and return its address, or NULL
if that hwspinlock is already in use. Usually board code will
be calling this function in order to reserve specific hwspinlock
ids for predefined purposes.
Can be called from an atomic context (this function will not sleep) but
not from within interrupt context.
int hwspin_lock_free(struct hwspinlock *hwlock);
- free a previously-assigned hwspinlock; returns 0 on success, or an
appropriate error code on failure (e.g. -EINVAL if the hwspinlock
is already free).
Can be called from an atomic context (this function will not sleep) but
not from within interrupt context.
int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int timeout);
- lock a previously-assigned hwspinlock with a timeout limit (specified in
msecs). If the hwspinlock is already taken, the function will busy loop
waiting for it to be released, but give up when the timeout elapses.
Upon a successful return from this function, preemption is disabled so
the caller must not sleep, and is advised to release the hwspinlock as
soon as possible, in order to minimize remote cores polling on the
hardware interconnect.
Returns 0 when successful and an appropriate error code otherwise (most
notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs).
The function will never sleep.
int hwspin_lock_timeout_irq(struct hwspinlock *hwlock, unsigned int timeout);
- lock a previously-assigned hwspinlock with a timeout limit (specified in
msecs). If the hwspinlock is already taken, the function will busy loop
waiting for it to be released, but give up when the timeout elapses.
Upon a successful return from this function, preemption and the local
interrupts are disabled, so the caller must not sleep, and is advised to
release the hwspinlock as soon as possible.
Returns 0 when successful and an appropriate error code otherwise (most
notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs).
The function will never sleep.
int hwspin_lock_timeout_irqsave(struct hwspinlock *hwlock, unsigned int to,
unsigned long *flags);
- lock a previously-assigned hwspinlock with a timeout limit (specified in
msecs). If the hwspinlock is already taken, the function will busy loop
waiting for it to be released, but give up when the timeout elapses.
Upon a successful return from this function, preemption is disabled,
local interrupts are disabled and their previous state is saved at the
given flags placeholder. The caller must not sleep, and is advised to
release the hwspinlock as soon as possible.
Returns 0 when successful and an appropriate error code otherwise (most
notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs).
The function will never sleep.
int hwspin_trylock(struct hwspinlock *hwlock);
- attempt to lock a previously-assigned hwspinlock, but immediately fail if
it is already taken.
Upon a successful return from this function, preemption is disabled so
caller must not sleep, and is advised to release the hwspinlock as soon as
possible, in order to minimize remote cores polling on the hardware
interconnect.
Returns 0 on success and an appropriate error code otherwise (most
notably -EBUSY if the hwspinlock was already taken).
The function will never sleep.
int hwspin_trylock_irq(struct hwspinlock *hwlock);
- attempt to lock a previously-assigned hwspinlock, but immediately fail if
it is already taken.
Upon a successful return from this function, preemption and the local
interrupts are disabled so caller must not sleep, and is advised to
release the hwspinlock as soon as possible.
Returns 0 on success and an appropriate error code otherwise (most
notably -EBUSY if the hwspinlock was already taken).
The function will never sleep.
int hwspin_trylock_irqsave(struct hwspinlock *hwlock, unsigned long *flags);
- attempt to lock a previously-assigned hwspinlock, but immediately fail if
it is already taken.
Upon a successful return from this function, preemption is disabled,
the local interrupts are disabled and their previous state is saved
at the given flags placeholder. The caller must not sleep, and is advised
to release the hwspinlock as soon as possible.
Returns 0 on success and an appropriate error code otherwise (most
notably -EBUSY if the hwspinlock was already taken).
The function will never sleep.
void hwspin_unlock(struct hwspinlock *hwlock);
- unlock a previously-locked hwspinlock. Always succeed, and can be called
from any context (the function never sleeps). Note: code should _never_
unlock an hwspinlock which is already unlocked (there is no protection
against this).
void hwspin_unlock_irq(struct hwspinlock *hwlock);
- unlock a previously-locked hwspinlock and enable local interrupts.
The caller should _never_ unlock an hwspinlock which is already unlocked.
Doing so is considered a bug (there is no protection against this).
Upon a successful return from this function, preemption and local
interrupts are enabled. This function will never sleep.
void
hwspin_unlock_irqrestore(struct hwspinlock *hwlock, unsigned long *flags);
- unlock a previously-locked hwspinlock.
The caller should _never_ unlock an hwspinlock which is already unlocked.
Doing so is considered a bug (there is no protection against this).
Upon a successful return from this function, preemption is reenabled,
and the state of the local interrupts is restored to the state saved at
the given flags. This function will never sleep.
int hwspin_lock_get_id(struct hwspinlock *hwlock);
- retrieve id number of a given hwspinlock. This is needed when an
hwspinlock is dynamically assigned: before it can be used to achieve
mutual exclusion with a remote cpu, the id number should be communicated
to the remote task with which we want to synchronize.
Returns the hwspinlock id number, or -EINVAL if hwlock is null.
3. Typical usage
#include <linux/hwspinlock.h>
#include <linux/err.h>
int hwspinlock_example1(void)
{
struct hwspinlock *hwlock;
int ret;
/* dynamically assign a hwspinlock */
hwlock = hwspin_lock_request();
if (!hwlock)
...
id = hwspin_lock_get_id(hwlock);
/* probably need to communicate id to a remote processor now */
/* take the lock, spin for 1 sec if it's already taken */
ret = hwspin_lock_timeout(hwlock, 1000);
if (ret)
...
/*
* we took the lock, do our thing now, but do NOT sleep
*/
/* release the lock */
hwspin_unlock(hwlock);
/* free the lock */
ret = hwspin_lock_free(hwlock);
if (ret)
...
return ret;
}
int hwspinlock_example2(void)
{
struct hwspinlock *hwlock;
int ret;
/*
* assign a specific hwspinlock id - this should be called early
* by board init code.
*/
hwlock = hwspin_lock_request_specific(PREDEFINED_LOCK_ID);
if (!hwlock)
...
/* try to take it, but don't spin on it */
ret = hwspin_trylock(hwlock);
if (!ret) {
pr_info("lock is already taken\n");
return -EBUSY;
}
/*
* we took the lock, do our thing now, but do NOT sleep
*/
/* release the lock */
hwspin_unlock(hwlock);
/* free the lock */
ret = hwspin_lock_free(hwlock);
if (ret)
...
return ret;
}
4. API for implementors
int hwspin_lock_register(struct hwspinlock *hwlock);
- to be called from the underlying platform-specific implementation, in
order to register a new hwspinlock instance. Can be called from an atomic
context (this function will not sleep) but not from within interrupt
context. Returns 0 on success, or appropriate error code on failure.
struct hwspinlock *hwspin_lock_unregister(unsigned int id);
- to be called from the underlying vendor-specific implementation, in order
to unregister an existing (and unused) hwspinlock instance.
Can be called from an atomic context (will not sleep) but not from
within interrupt context.
Returns the address of hwspinlock on success, or NULL on error (e.g.
if the hwspinlock is sill in use).
5. struct hwspinlock
This struct represents an hwspinlock instance. It is registered by the
underlying hwspinlock implementation using the hwspin_lock_register() API.
/**
* struct hwspinlock - vendor-specific hwspinlock implementation
*
* @dev: underlying device, will be used with runtime PM api
* @ops: vendor-specific hwspinlock handlers
* @id: a global, unique, system-wide, index of the lock.
* @lock: initialized and used by hwspinlock core
* @owner: underlying implementation module, used to maintain module ref count
*/
struct hwspinlock {
struct device *dev;
const struct hwspinlock_ops *ops;
int id;
spinlock_t lock;
struct module *owner;
};
The underlying implementation is responsible to assign the dev, ops, id and
owner members. The lock member, OTOH, is initialized and used by the hwspinlock
core.
6. Implementation callbacks
There are three possible callbacks defined in 'struct hwspinlock_ops':
struct hwspinlock_ops {
int (*trylock)(struct hwspinlock *lock);
void (*unlock)(struct hwspinlock *lock);
void (*relax)(struct hwspinlock *lock);
};
The first two callbacks are mandatory:
The ->trylock() callback should make a single attempt to take the lock, and
return 0 on failure and 1 on success. This callback may _not_ sleep.
The ->unlock() callback releases the lock. It always succeed, and it, too,
may _not_ sleep.
The ->relax() callback is optional. It is called by hwspinlock core while
spinning on a lock, and can be used by the underlying implementation to force
a delay between two successive invocations of ->trylock(). It may _not_ sleep.

12
MAINTAINERS
View File

@ -4510,11 +4510,21 @@ S: Maintained
F: arch/arm/*omap*/*clock*
OMAP POWER MANAGEMENT SUPPORT
M: Kevin Hilman <khilman@deeprootsystems.com>
M: Kevin Hilman <khilman@ti.com>
L: linux-omap@vger.kernel.org
S: Maintained
F: arch/arm/*omap*/*pm*
OMAP POWERDOMAIN/CLOCKDOMAIN SOC ADAPTATION LAYER SUPPORT
M: Rajendra Nayak <rnayak@ti.com>
M: Paul Walmsley <paul@pwsan.com>
L: linux-omap@vger.kernel.org
S: Maintained
F: arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
F: arch/arm/mach-omap2/powerdomain44xx.c
F: arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
F: arch/arm/mach-omap2/clockdomain44xx.c
OMAP AUDIO SUPPORT
M: Jarkko Nikula <jhnikula@gmail.com>
L: alsa-devel@alsa-project.org (subscribers-only)

1
arch/arm/configs/omap2plus_defconfig
View File

@ -58,6 +58,7 @@ CONFIG_ARM_ERRATA_411920=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
# CONFIG_LOCAL_TIMERS is not set
CONFIG_AEABI=y
CONFIG_LEDS=y

2
arch/arm/mach-omap1/Makefile
View File

@ -4,7 +4,7 @@
# Common support
obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
obj-y += clock.o clock_data.o opp_data.o
obj-y += clock.o clock_data.o opp_data.o reset.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o

16
arch/arm/mach-omap1/board-ams-delta.c
View File

@ -165,7 +165,7 @@ static struct map_desc ams_delta_io_desc[] __initdata = {
}
};
static struct omap_lcd_config ams_delta_lcd_config __initdata = {
static struct omap_lcd_config ams_delta_lcd_config = {
.ctrl_name = "internal",
};
@ -175,7 +175,7 @@ static struct omap_usb_config ams_delta_usb_config __initdata = {
.pins[0] = 2,
};
static struct omap_board_config_kernel ams_delta_config[] = {
static struct omap_board_config_kernel ams_delta_config[] __initdata = {
{ OMAP_TAG_LCD, &ams_delta_lcd_config },
};
@ -208,14 +208,14 @@ static const struct matrix_keymap_data ams_delta_keymap_data = {
.keymap_size = ARRAY_SIZE(ams_delta_keymap),
};
static struct omap_kp_platform_data ams_delta_kp_data = {
static struct omap_kp_platform_data ams_delta_kp_data __initdata = {
.rows = 8,
.cols = 8,
.keymap_data = &ams_delta_keymap_data,
.delay = 9,
};
static struct platform_device ams_delta_kp_device = {
static struct platform_device ams_delta_kp_device __initdata = {
.name = "omap-keypad",
.id = -1,
.dev = {
@ -225,12 +225,12 @@ static struct platform_device ams_delta_kp_device = {
.resource = ams_delta_kp_resources,
};
static struct platform_device ams_delta_lcd_device = {
static struct platform_device ams_delta_lcd_device __initdata = {
.name = "lcd_ams_delta",
.id = -1,
};
static struct platform_device ams_delta_led_device = {
static struct platform_device ams_delta_led_device __initdata = {
.name = "ams-delta-led",
.id = -1
};
@ -259,7 +259,7 @@ static int ams_delta_camera_power(struct device *dev, int power)
#define ams_delta_camera_power NULL
#endif
static struct soc_camera_link __initdata ams_delta_iclink = {
static struct soc_camera_link ams_delta_iclink = {
.bus_id = 0, /* OMAP1 SoC camera bus */
.i2c_adapter_id = 1,
.board_info = &ams_delta_camera_board_info[0],
@ -267,7 +267,7 @@ static struct soc_camera_link __initdata ams_delta_iclink = {
.power = ams_delta_camera_power,
};
static struct platform_device ams_delta_camera_device = {
static struct platform_device ams_delta_camera_device __initdata = {
.name = "soc-camera-pdrv",
.id = 0,
.dev = {

4
arch/arm/mach-omap1/board-fsample.c
View File

@ -287,11 +287,11 @@ static struct platform_device *devices[] __initdata = {
&lcd_device,
};
static struct omap_lcd_config fsample_lcd_config __initdata = {
static struct omap_lcd_config fsample_lcd_config = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel fsample_config[] = {
static struct omap_board_config_kernel fsample_config[] __initdata = {
{ OMAP_TAG_LCD, &fsample_lcd_config },
};

2
arch/arm/mach-omap1/board-h2.c
View File

@ -202,7 +202,7 @@ static int h2_nand_dev_ready(struct mtd_info *mtd)
static const char *h2_part_probes[] = { "cmdlinepart", NULL };
struct platform_nand_data h2_nand_platdata = {
static struct platform_nand_data h2_nand_platdata = {
.chip = {
.nr_chips = 1,
.chip_offset = 0,

2
arch/arm/mach-omap1/board-h3.c
View File

@ -204,7 +204,7 @@ static int nand_dev_ready(struct mtd_info *mtd)
static const char *part_probes[] = { "cmdlinepart", NULL };
struct platform_nand_data nand_platdata = {
static struct platform_nand_data nand_platdata = {
.chip = {
.nr_chips = 1,
.chip_offset = 0,

4
arch/arm/mach-omap1/board-htcherald.c
View File

@ -331,7 +331,7 @@ static struct resource htcpld_resources[] = {
},
};
struct htcpld_chip_platform_data htcpld_chips[] = {
static struct htcpld_chip_platform_data htcpld_chips[] = {
[0] = {
.addr = 0x03,
.reset = 0x04,
@ -366,7 +366,7 @@ struct htcpld_chip_platform_data htcpld_chips[] = {
},
};
struct htcpld_core_platform_data htcpld_pfdata = {
static struct htcpld_core_platform_data htcpld_pfdata = {
.int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI,
.int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO,
.i2c_adapter_id = 1,

2
arch/arm/mach-omap1/board-innovator.c
View File

@ -365,7 +365,7 @@ static struct omap_mmc_platform_data mmc1_data = {
static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC];
void __init innovator_mmc_init(void)
static void __init innovator_mmc_init(void)
{
mmc_data[0] = &mmc1_data;
omap1_init_mmc(mmc_data, OMAP15XX_NR_MMC);

6
arch/arm/mach-omap1/board-nokia770.c
View File

@ -115,7 +115,7 @@ static struct mipid_platform_data nokia770_mipid_platform_data = {
.shutdown = mipid_shutdown,
};
static void mipid_dev_init(void)
static void __init mipid_dev_init(void)
{
const struct omap_lcd_config *conf;
@ -126,7 +126,7 @@ static void mipid_dev_init(void)
}
}
static void ads7846_dev_init(void)
static void __init ads7846_dev_init(void)
{
if (gpio_request(ADS7846_PENDOWN_GPIO, "ADS7846 pendown") < 0)
printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
@ -170,7 +170,7 @@ static struct hwa742_platform_data nokia770_hwa742_platform_data = {
.te_connected = 1,
};
static void hwa742_dev_init(void)
static void __init hwa742_dev_init(void)
{
clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL);
omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data);

13
arch/arm/mach-omap1/board-palmte.c
View File

@ -230,19 +230,6 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
},
};
static void palmte_headphones_detect(void *data, int state)
{
if (state) {
/* Headphones connected, disable speaker */
gpio_set_value(PALMTE_SPEAKER_GPIO, 0);
printk(KERN_INFO "PM: speaker off\n");
} else {
/* Headphones unplugged, re-enable speaker */
gpio_set_value(PALMTE_SPEAKER_GPIO, 1);
printk(KERN_INFO "PM: speaker on\n");
}
}
static void __init palmte_misc_gpio_setup(void)
{
/* Set TSC2102 PINTDAV pin as input (used by TSC2102 driver) */

107
arch/arm/mach-omap1/board-voiceblue.c
View File

@ -26,10 +26,12 @@
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <mach/system.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat/board-voiceblue.h>
#include <plat/common.h>
#include <mach/gpio.h>
#include <plat/flash.h>
@ -163,52 +165,6 @@ static void __init voiceblue_init_irq(void)
omap_init_irq();
}
static void __init voiceblue_init(void)
{
/* mux pins for uarts */
omap_cfg_reg(UART1_TX);
omap_cfg_reg(UART1_RTS);
omap_cfg_reg(UART2_TX);
omap_cfg_reg(UART2_RTS);
omap_cfg_reg(UART3_TX);
omap_cfg_reg(UART3_RX);
/* Watchdog */
gpio_request(0, "Watchdog");
/* smc91x reset */
gpio_request(7, "SMC91x reset");
gpio_direction_output(7, 1);
udelay(2); /* wait at least 100ns */
gpio_set_value(7, 0);
mdelay(50); /* 50ms until PHY ready */
/* smc91x interrupt pin */
gpio_request(8, "SMC91x irq");
/* 16C554 reset*/
gpio_request(6, "16C554 reset");
gpio_direction_output(6, 0);
/* 16C554 interrupt pins */
gpio_request(12, "16C554 irq");
gpio_request(13, "16C554 irq");
gpio_request(14, "16C554 irq");
gpio_request(15, "16C554 irq");
set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
omap_board_config = voiceblue_config;
omap_board_config_size = ARRAY_SIZE(voiceblue_config);
omap_serial_init();
omap1_usb_init(&voiceblue_usb_config);
omap_register_i2c_bus(1, 100, NULL, 0);
/* There is a good chance board is going up, so enable power LED
* (it is connected through invertor) */
omap_writeb(0x00, OMAP_LPG1_LCR);
omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
}
static void __init voiceblue_map_io(void)
{
omap1_map_common_io();
@ -275,8 +231,17 @@ void voiceblue_wdt_ping(void)
gpio_set_value(0, wdt_gpio_state);
}
void voiceblue_reset(void)
static void voiceblue_reset(char mode, const char *cmd)
{
/*
* Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
* "Global Software Reset Affects Traffic Controller Frequency".
*/
if (cpu_is_omap5912()) {
omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL);
omap_writew(0x8, ARM_RSTCT1);
}
set_bit(MACHINE_REBOOT, &machine_state);
voiceblue_wdt_enable();
while (1) ;
@ -286,6 +251,54 @@ EXPORT_SYMBOL(voiceblue_wdt_enable);
EXPORT_SYMBOL(voiceblue_wdt_disable);
EXPORT_SYMBOL(voiceblue_wdt_ping);
static void __init voiceblue_init(void)
{
/* mux pins for uarts */
omap_cfg_reg(UART1_TX);
omap_cfg_reg(UART1_RTS);
omap_cfg_reg(UART2_TX);
omap_cfg_reg(UART2_RTS);
omap_cfg_reg(UART3_TX);
omap_cfg_reg(UART3_RX);
/* Watchdog */
gpio_request(0, "Watchdog");
/* smc91x reset */
gpio_request(7, "SMC91x reset");
gpio_direction_output(7, 1);
udelay(2); /* wait at least 100ns */
gpio_set_value(7, 0);
mdelay(50); /* 50ms until PHY ready */
/* smc91x interrupt pin */
gpio_request(8, "SMC91x irq");
/* 16C554 reset*/
gpio_request(6, "16C554 reset");
gpio_direction_output(6, 0);
/* 16C554 interrupt pins */
gpio_request(12, "16C554 irq");
gpio_request(13, "16C554 irq");
gpio_request(14, "16C554 irq");
gpio_request(15, "16C554 irq");
set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
omap_board_config = voiceblue_config;
omap_board_config_size = ARRAY_SIZE(voiceblue_config);
omap_serial_init();
omap1_usb_init(&voiceblue_usb_config);
omap_register_i2c_bus(1, 100, NULL, 0);
/* There is a good chance board is going up, so enable power LED
* (it is connected through invertor) */
omap_writeb(0x00, OMAP_LPG1_LCR);
omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
arch_reset = voiceblue_reset;
}
MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
/* Maintainer: Ladislav Michl <michl@2n.cz> */
.boot_params = 0x10000100,

333
arch/arm/mach-omap1/mcbsp.c
View File

@ -10,6 +10,7 @@
*
* Multichannel mode not supported.
*/
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
@ -78,100 +79,294 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
};
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
struct resource omap7xx_mcbsp_res[][6] = {
{
{
.start = OMAP7XX_MCBSP1_BASE,
.end = OMAP7XX_MCBSP1_BASE + SZ_256,
.flags = IORESOURCE_MEM,
},
{
.name = "rx",
.start = INT_7XX_McBSP1RX,
.flags = IORESOURCE_IRQ,
},
{
.name = "tx",
.start = INT_7XX_McBSP1TX,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = OMAP_DMA_MCBSP1_RX,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = OMAP_DMA_MCBSP1_TX,
.flags = IORESOURCE_DMA,
},
},
{
{
.start = OMAP7XX_MCBSP2_BASE,
.end = OMAP7XX_MCBSP2_BASE + SZ_256,
.flags = IORESOURCE_MEM,
},
{
.name = "rx",
.start = INT_7XX_McBSP2RX,
.flags = IORESOURCE_IRQ,
},
{
.name = "tx",
.start = INT_7XX_McBSP2TX,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = OMAP_DMA_MCBSP3_RX,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = OMAP_DMA_MCBSP3_TX,
.flags = IORESOURCE_DMA,
},
},
};
#define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0]
static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
{
.phys_base = OMAP7XX_MCBSP1_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
.rx_irq = INT_7XX_McBSP1RX,
.tx_irq = INT_7XX_McBSP1TX,
.ops = &omap1_mcbsp_ops,
},
{
.phys_base = OMAP7XX_MCBSP2_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
.rx_irq = INT_7XX_McBSP2RX,
.tx_irq = INT_7XX_McBSP2TX,
.ops = &omap1_mcbsp_ops,
},
};
#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata)
#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
#else
#define omap7xx_mcbsp_res_0 NULL
#define omap7xx_mcbsp_pdata NULL
#define OMAP7XX_MCBSP_PDATA_SZ 0
#define OMAP7XX_MCBSP_REG_NUM 0
#define OMAP7XX_MCBSP_RES_SZ 0
#define OMAP7XX_MCBSP_COUNT 0
#endif
#ifdef CONFIG_ARCH_OMAP15XX
struct resource omap15xx_mcbsp_res[][6] = {
{
{
.start = OMAP1510_MCBSP1_BASE,
.end = OMAP1510_MCBSP1_BASE + SZ_256,
.flags = IORESOURCE_MEM,
},
{
.name = "rx",
.start = INT_McBSP1RX,
.flags = IORESOURCE_IRQ,
},
{
.name = "tx",
.start = INT_McBSP1TX,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = OMAP_DMA_MCBSP1_RX,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = OMAP_DMA_MCBSP1_TX,
.flags = IORESOURCE_DMA,
},
},
{
{
.start = OMAP1510_MCBSP2_BASE,
.end = OMAP1510_MCBSP2_BASE + SZ_256,
.flags = IORESOURCE_MEM,
},
{
.name = "rx",
.start = INT_1510_SPI_RX,
.flags = IORESOURCE_IRQ,
},
{
.name = "tx",
.start = INT_1510_SPI_TX,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = OMAP_DMA_MCBSP2_RX,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = OMAP_DMA_MCBSP2_TX,
.flags = IORESOURCE_DMA,
},
},
{
{
.start = OMAP1510_MCBSP3_BASE,
.end = OMAP1510_MCBSP3_BASE + SZ_256,
.flags = IORESOURCE_MEM,
},
{
.name = "rx",
.start = INT_McBSP3RX,
.flags = IORESOURCE_IRQ,
},
{
.name = "tx",
.start = INT_McBSP3TX,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = OMAP_DMA_MCBSP3_RX,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = OMAP_DMA_MCBSP3_TX,
.flags = IORESOURCE_DMA,
},
},
};
#define omap15xx_mcbsp_res_0 omap15xx_mcbsp_res[0]
static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
{
.phys_base = OMAP1510_MCBSP1_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
.rx_irq = INT_McBSP1RX,
.tx_irq = INT_McBSP1TX,
.ops = &omap1_mcbsp_ops,
},
{
.phys_base = OMAP1510_MCBSP2_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
.dma_tx_sync = OMAP_DMA_MCBSP2_TX,
.rx_irq = INT_1510_SPI_RX,
.tx_irq = INT_1510_SPI_TX,
.ops = &omap1_mcbsp_ops,
},
{
.phys_base = OMAP1510_MCBSP3_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
.rx_irq = INT_McBSP3RX,
.tx_irq = INT_McBSP3TX,
.ops = &omap1_mcbsp_ops,
},
};
#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
#else
#define omap15xx_mcbsp_res_0 NULL
#define omap15xx_mcbsp_pdata NULL
#define OMAP15XX_MCBSP_PDATA_SZ 0
#define OMAP15XX_MCBSP_REG_NUM 0
#define OMAP15XX_MCBSP_RES_SZ 0
#define OMAP15XX_MCBSP_COUNT 0
#endif
#ifdef CONFIG_ARCH_OMAP16XX
struct resource omap16xx_mcbsp_res[][6] = {
{
{
.start = OMAP1610_MCBSP1_BASE,
.end = OMAP1610_MCBSP1_BASE + SZ_256,
.flags = IORESOURCE_MEM,
},
{
.name = "rx",
.start = INT_McBSP1RX,
.flags = IORESOURCE_IRQ,
},
{
.name = "tx",
.start = INT_McBSP1TX,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = OMAP_DMA_MCBSP1_RX,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = OMAP_DMA_MCBSP1_TX,
.flags = IORESOURCE_DMA,
},
},
{
{
.start = OMAP1610_MCBSP2_BASE,
.end = OMAP1610_MCBSP2_BASE + SZ_256,
.flags = IORESOURCE_MEM,
},
{
.name = "rx",
.start = INT_1610_McBSP2_RX,
.flags = IORESOURCE_IRQ,
},
{
.name = "tx",
.start = INT_1610_McBSP2_TX,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = OMAP_DMA_MCBSP2_RX,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = OMAP_DMA_MCBSP2_TX,
.flags = IORESOURCE_DMA,
},
},
{
{
.start = OMAP1610_MCBSP3_BASE,
.end = OMAP1610_MCBSP3_BASE + SZ_256,
.flags = IORESOURCE_MEM,
},
{
.name = "rx",
.start = INT_McBSP3RX,
.flags = IORESOURCE_IRQ,
},
{
.name = "tx",
.start = INT_McBSP3TX,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = OMAP_DMA_MCBSP3_RX,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = OMAP_DMA_MCBSP3_TX,
.flags = IORESOURCE_DMA,
},
},
};
#define omap16xx_mcbsp_res_0 omap16xx_mcbsp_res[0]
static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
{
.phys_base = OMAP1610_MCBSP1_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
.rx_irq = INT_McBSP1RX,
.tx_irq = INT_McBSP1TX,
.ops = &omap1_mcbsp_ops,
},
{
.phys_base = OMAP1610_MCBSP2_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
.dma_tx_sync = OMAP_DMA_MCBSP2_TX,
.rx_irq = INT_1610_McBSP2_RX,
.tx_irq = INT_1610_McBSP2_TX,
.ops = &omap1_mcbsp_ops,
},
{
.phys_base = OMAP1610_MCBSP3_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
.rx_irq = INT_McBSP3RX,
.tx_irq = INT_McBSP3TX,
.ops = &omap1_mcbsp_ops,
},
};
#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
#else
#define omap16xx_mcbsp_res_0 NULL
#define omap16xx_mcbsp_pdata NULL
#define OMAP16XX_MCBSP_PDATA_SZ 0
#define OMAP16XX_MCBSP_REG_NUM 0
#define OMAP16XX_MCBSP_RES_SZ 0
#define OMAP16XX_MCBSP_COUNT 0
#endif
static int __init omap1_mcbsp_init(void)
@ -179,16 +374,12 @@ static int __init omap1_mcbsp_init(void)
if (!cpu_class_is_omap1())
return -ENODEV;
if (cpu_is_omap7xx()) {
omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16);
} else if (cpu_is_omap15xx()) {
omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16);
} else if (cpu_is_omap16xx()) {
omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16);
}
if (cpu_is_omap7xx())
omap_mcbsp_count = OMAP7XX_MCBSP_COUNT;
else if (cpu_is_omap15xx())
omap_mcbsp_count = OMAP15XX_MCBSP_COUNT;
else if (cpu_is_omap16xx())
omap_mcbsp_count = OMAP16XX_MCBSP_COUNT;
mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
GFP_KERNEL);
@ -196,16 +387,22 @@ static int __init omap1_mcbsp_init(void)
return -ENOMEM;
if (cpu_is_omap7xx())
omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
OMAP7XX_MCBSP_PDATA_SZ);
omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
OMAP7XX_MCBSP_RES_SZ,
omap7xx_mcbsp_pdata,
OMAP7XX_MCBSP_COUNT);
if (cpu_is_omap15xx())
omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
OMAP15XX_MCBSP_PDATA_SZ);
omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
OMAP15XX_MCBSP_RES_SZ,
omap15xx_mcbsp_pdata,
OMAP15XX_MCBSP_COUNT);
if (cpu_is_omap16xx())
omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
OMAP16XX_MCBSP_PDATA_SZ);
omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0,
OMAP16XX_MCBSP_RES_SZ,
omap16xx_mcbsp_pdata,
OMAP16XX_MCBSP_COUNT);
return omap_mcbsp_init();
}

25
arch/arm/mach-omap1/reset.c Normal file
View File

@ -0,0 +1,25 @@
/*
* OMAP1 reset support
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/system.h>
#include <plat/prcm.h>
void omap1_arch_reset(char mode, const char *cmd)
{
/*
* Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
* "Global Software Reset Affects Traffic Controller Frequency".
*/
if (cpu_is_omap5912()) {
omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL);
omap_writew(0x8, ARM_RSTCT1);
}
omap_writew(1, ARM_RSTCT1);
}
void (*arch_reset)(char, const char *) = omap1_arch_reset;

28
arch/arm/mach-omap2/Kconfig
View File

@ -54,25 +54,30 @@ config ARCH_OMAP4
comment "OMAP Core Type"
depends on ARCH_OMAP2
config ARCH_OMAP2420
config SOC_OMAP2420
bool "OMAP2420 support"
depends on ARCH_OMAP2
default y
select OMAP_DM_TIMER
select ARCH_OMAP_OTG
config ARCH_OMAP2430
config SOC_OMAP2430
bool "OMAP2430 support"
depends on ARCH_OMAP2
default y
select ARCH_OMAP_OTG
config ARCH_OMAP3430
config SOC_OMAP3430
bool "OMAP3430 support"
depends on ARCH_OMAP3
default y
select ARCH_OMAP_OTG
config SOC_OMAPTI816X
bool "TI816X support"
depends on ARCH_OMAP3
default y
config OMAP_PACKAGE_ZAF
bool
@ -107,25 +112,25 @@ config MACH_OMAP_GENERIC
config MACH_OMAP2_TUSB6010
bool
depends on ARCH_OMAP2 && ARCH_OMAP2420
depends on ARCH_OMAP2 && SOC_OMAP2420
default y if MACH_NOKIA_N8X0
config MACH_OMAP_H4
bool "OMAP 2420 H4 board"
depends on ARCH_OMAP2420
depends on SOC_OMAP2420
default y
select OMAP_PACKAGE_ZAF
select OMAP_DEBUG_DEVICES
config MACH_OMAP_APOLLON
bool "OMAP 2420 Apollon board"
depends on ARCH_OMAP2420
depends on SOC_OMAP2420
default y
select OMAP_PACKAGE_ZAC
config MACH_OMAP_2430SDP
bool "OMAP 2430 SDP board"
depends on ARCH_OMAP2430
depends on SOC_OMAP2430
default y
select OMAP_PACKAGE_ZAC
@ -220,7 +225,7 @@ config MACH_NOKIA_N810_WIMAX
config MACH_NOKIA_N8X0
bool "Nokia N800/N810"
depends on ARCH_OMAP2420
depends on SOC_OMAP2420
default y
select OMAP_PACKAGE_ZAC
select MACH_NOKIA_N800
@ -295,12 +300,18 @@ config MACH_OMAP_3630SDP
default y
select OMAP_PACKAGE_CBP
config MACH_TI8168EVM
bool "TI8168 Evaluation Module"
depends on SOC_OMAPTI816X
default y
config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"
default y
depends on ARCH_OMAP4
select OMAP_PACKAGE_CBL
select OMAP_PACKAGE_CBS
select REGULATOR_FIXED_VOLTAGE
config MACH_OMAP4_PANDA
bool "OMAP4 Panda Board"
@ -308,6 +319,7 @@ config MACH_OMAP4_PANDA
depends on ARCH_OMAP4
select OMAP_PACKAGE_CBL
select OMAP_PACKAGE_CBS
select REGULATOR_FIXED_VOLTAGE
config OMAP3_EMU
bool "OMAP3 debugging peripherals"

66
arch/arm/mach-omap2/Makefile
View File

@ -31,8 +31,8 @@ AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec)
# Functions loaded to SRAM
obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
AFLAGS_sram242x.o :=-Wa,-march=armv6
@ -40,8 +40,8 @@ AFLAGS_sram243x.o :=-Wa,-march=armv6
AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
# Pin multiplexing
obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o
obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o
obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
obj-$(CONFIG_SOC_OMAP2430) += mux2430.o
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
@ -59,10 +59,10 @@ endif
# Power Management
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o voltage.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o voltage.o \
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \
cpuidle34xx.o pm_bus.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o voltage.o pm_bus.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
@ -78,13 +78,25 @@ endif
# PRCM
obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
vc3xxx_data.o vp3xxx_data.o
# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
# will be removed once the OMAP4 part of the codebase is converted to
# use OMAP4-specific PRCM functions.
obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
cm44xx.o prcm_mpu44xx.o \
prminst44xx.o
prminst44xx.o vc44xx_data.o \
vp44xx_data.o
# OMAP voltage domains
ifeq ($(CONFIG_PM),y)
voltagedomain-common := voltage.o
obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
voltagedomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) \
voltagedomains44xx_data.o
endif
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
@ -102,39 +114,49 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
# PRCM clockdomain control
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
clockdomain2xxx_3xxx.o \
clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
clockdomain44xx.o \
clockdomains44xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
clkt2xxx_sys.o \
clkt2xxx_dpllcore.o \
clkt2xxx_virt_prcm_set.o \
clkt2xxx_apll.o clkt2xxx_osc.o
obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o
obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o
clkt2xxx_apll.o clkt2xxx_osc.o \
clkt2xxx_dpll.o clkt_iclk.o
obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
clock34xx.o clkt34xx_dpll3m2.o \
clock3517.o clock36xx.o \
dpll3xxx.o clock3xxx_data.o
dpll3xxx.o clock3xxx_data.o \
clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
dpll3xxx.o
dpll3xxx.o dpll44xx.o
# OMAP2 clock rate set data (old "OPP" data)
obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o
obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
# hwmod data
obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o
obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o
# L3 interconnect
obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o
@ -218,12 +240,14 @@ obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \
hsmmc.o \
omap_phy_internal.o
obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \
omap_phy_internal.o \
obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \
hsmmc.o
obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
# Platform specific device init code
usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o
obj-y += $(usbfs-m) $(usbfs-y)
@ -242,3 +266,7 @@ obj-y += $(smc91x-m) $(smc91x-y)
smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
obj-y += $(smsc911x-m) $(smsc911x-y)
obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
disp-$(CONFIG_OMAP2_DSS) := display.o
obj-y += $(disp-m) $(disp-y)

34
arch/arm/mach-omap2/board-2430sdp.c
View File

@ -22,6 +22,7 @@
#include <linux/mmc/host.h>
#include <linux/delay.h>
#include <linux/i2c/twl.h>
#include <linux/regulator/machine.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
@ -139,15 +140,31 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = {
{OMAP_TAG_LCD, &sdp2430_lcd_config},
};
static void __init omap_2430sdp_init_irq(void)
static void __init omap_2430sdp_init_early(void)
{
omap_board_config = sdp2430_config;
omap_board_config_size = ARRAY_SIZE(sdp2430_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
omap_init_irq();
}
static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
static struct regulator_init_data sdp2430_vmmc1 = {
.constraints = {
.min_uV = 1850000,
.max_uV = 3150000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies),
.consumer_supplies = &sdp2430_vmmc1_supplies[0],
};
static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
.gpio_base = OMAP_MAX_GPIO_LINES,
.irq_base = TWL4030_GPIO_IRQ_BASE,
@ -160,6 +177,7 @@ static struct twl4030_platform_data sdp2430_twldata = {
/* platform_data for children goes here */
.gpio = &sdp2430_gpio_data,
.vmmc1 = &sdp2430_vmmc1,
};
static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = {
@ -226,6 +244,9 @@ static void __init omap_2430sdp_init(void)
omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
omap_board_config = sdp2430_config;
omap_board_config_size = ARRAY_SIZE(sdp2430_config);
omap2430_i2c_init();
platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
@ -253,9 +274,10 @@ static void __init omap_2430sdp_map_io(void)
MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
/* Maintainer: Syed Khasim - Texas Instruments Inc */
.boot_params = 0x80000100,
.map_io = omap_2430sdp_map_io,
.reserve = omap_reserve,
.init_irq = omap_2430sdp_init_irq,
.map_io = omap_2430sdp_map_io,
.init_early = omap_2430sdp_init_early,
.init_irq = omap_init_irq,
.init_machine = omap_2430sdp_init,
.timer = &omap_timer,
MACHINE_END

215
arch/arm/mach-omap2/board-3430sdp.c
View File

@ -307,34 +307,16 @@ static struct omap_dss_board_info sdp3430_dss_data = {
.default_device = &sdp3430_lcd_device,
};
static struct platform_device sdp3430_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &sdp3430_dss_data,
},
};
static struct regulator_consumer_supply sdp3430_vdda_dac_supply = {
.supply = "vdda_dac",
.dev = &sdp3430_dss_device.dev,
};
static struct platform_device *sdp3430_devices[] __initdata = {
&sdp3430_dss_device,
};
static struct regulator_consumer_supply sdp3430_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
static struct omap_board_config_kernel sdp3430_config[] __initdata = {
};
static void __init omap_3430sdp_init_irq(void)
static void __init omap_3430sdp_init_early(void)
{
omap_board_config = sdp3430_config;
omap_board_config_size = ARRAY_SIZE(sdp3430_config);
omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
omap2_init_common_infrastructure();
omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
omap_init_irq();
}
static int sdp3430_batt_table[] = {
@ -370,18 +352,6 @@ static struct omap2_hsmmc_info mmc[] = {
{} /* Terminator */
};
static struct regulator_consumer_supply sdp3430_vmmc1_supply = {
.supply = "vmmc",
};
static struct regulator_consumer_supply sdp3430_vsim_supply = {
.supply = "vmmc_aux",
};
static struct regulator_consumer_supply sdp3430_vmmc2_supply = {
.supply = "vmmc",
};
static int sdp3430_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
@ -392,13 +362,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
mmc[1].gpio_cd = gpio + 1;
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters ... we "know" the
* regulators will be set up only *after* we return.
*/
sdp3430_vmmc1_supply.dev = mmc[0].dev;
sdp3430_vsim_supply.dev = mmc[0].dev;
sdp3430_vmmc2_supply.dev = mmc[1].dev;
/* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
gpio_request(gpio + 7, "sub_lcd_en_bkl");
gpio_direction_output(gpio + 7, 0);
@ -427,6 +390,34 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = {
.irq_line = 1,
};
/* regulator consumer mappings */
/* ads7846 on SPI */
static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
REGULATOR_SUPPLY("vcc", "spi1.0"),
};
static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
REGULATOR_SUPPLY("vdda_dac", "omapdss"),
};
/* VPLL2 for digital video outputs */
static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
};
static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
};
/*
* Apply all the fixed voltages since most versions of U-Boot
* don't bother with that initialization.
@ -469,6 +460,8 @@ static struct regulator_init_data sdp3430_vaux3 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
.consumer_supplies = sdp3430_vaux3_supplies,
};
/* VAUX4 for OMAP VDD_CSI2 (camera) */
@ -495,8 +488,8 @@ static struct regulator_init_data sdp3430_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &sdp3430_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
.consumer_supplies = sdp3430_vmmc1_supplies,
};
/* VMMC2 for MMC2 card */
@ -510,8 +503,8 @@ static struct regulator_init_data sdp3430_vmmc2 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &sdp3430_vmmc2_supply,
.num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
.consumer_supplies = sdp3430_vmmc2_supplies,
};
/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@ -525,8 +518,8 @@ static struct regulator_init_data sdp3430_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &sdp3430_vsim_supply,
.num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
.consumer_supplies = sdp3430_vsim_supplies,
};
/* VDAC for DSS driving S-Video */
@ -540,16 +533,8 @@ static struct regulator_init_data sdp3430_vdac = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &sdp3430_vdda_dac_supply,
};
/* VPLL2 for digital video outputs */
static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
{
.supply = "vdds_dsi",
.dev = &sdp3430_dss_device.dev,
}
.num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
.consumer_supplies = sdp3430_vdda_dac_supplies,
};
static struct regulator_init_data sdp3430_vpll2 = {
@ -567,9 +552,7 @@ static struct regulator_init_data sdp3430_vpll2 = {
.consumer_supplies = sdp3430_vpll2_supplies,
};
static struct twl4030_codec_audio_data sdp3430_audio = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_audio_data sdp3430_audio;
static struct twl4030_codec_data sdp3430_codec = {
.audio_mclk = 26000000,
@ -669,6 +652,106 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static struct omap_device_pad serial1_pads[] __initdata = {
/*
* Note that off output enable is an active low
* signal. So setting this means pin is a
* input enabled in off mode
*/
OMAP_MUX_STATIC("uart1_cts.uart1_cts",
OMAP_PIN_INPUT |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart1_rts.uart1_rts",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart1_rx.uart1_rx",
OMAP_PIN_INPUT |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart1_tx.uart1_tx",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
};
static struct omap_device_pad serial2_pads[] __initdata = {
OMAP_MUX_STATIC("uart2_cts.uart2_cts",
OMAP_PIN_INPUT_PULLUP |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rts.uart2_rts",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rx.uart2_rx",
OMAP_PIN_INPUT |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_tx.uart2_tx",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
};
static struct omap_device_pad serial3_pads[] __initdata = {
OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
OMAP_PIN_INPUT_PULLDOWN |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
OMAP_PIN_INPUT |
OMAP_PIN_OFF_INPUT_PULLDOWN |
OMAP_OFFOUT_EN |
OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
OMAP_PIN_OUTPUT |
OMAP_OFF_EN |
OMAP_MUX_MODE0),
};
static struct omap_board_data serial1_data = {
.id = 0,
.pads = serial1_pads,
.pads_cnt = ARRAY_SIZE(serial1_pads),
};
static struct omap_board_data serial2_data = {
.id = 1,
.pads = serial2_pads,
.pads_cnt = ARRAY_SIZE(serial2_pads),
};
static struct omap_board_data serial3_data = {
.id = 2,
.pads = serial3_pads,
.pads_cnt = ARRAY_SIZE(serial3_pads),
};
static inline void board_serial_init(void)
{
omap_serial_init_port(&serial1_data);
omap_serial_init_port(&serial2_data);
omap_serial_init_port(&serial3_data);
}
#else
#define board_mux NULL
static inline void board_serial_init(void)
{
omap_serial_init();
}
#endif
/*
@ -800,8 +883,11 @@ static struct omap_musb_board_data musb_board_data = {
static void __init omap_3430sdp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_board_config = sdp3430_config;
omap_board_config_size = ARRAY_SIZE(sdp3430_config);
omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
omap3430_i2c_init();
platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
omap_display_init(&sdp3430_dss_data);
if (omap_rev() > OMAP3430_REV_ES1_0)
ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
else
@ -810,10 +896,10 @@ static void __init omap_3430sdp_init(void)
spi_register_board_info(sdp3430_spi_board_info,
ARRAY_SIZE(sdp3430_spi_board_info));
ads7846_dev_init();
omap_serial_init();
board_serial_init();
usb_musb_init(&musb_board_data);
board_smc91x_init();
board_flash_init(sdp_flash_partitions, chip_sel_3430);
board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
sdp3430_display_init();
enable_board_wakeup_source();
usbhs_init(&usbhs_bdata);
@ -822,9 +908,10 @@ static void __init omap_3430sdp_init(void)
MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
/* Maintainer: Syed Khasim - Texas Instruments Inc */
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = omap_3430sdp_init_irq,
.map_io = omap3_map_io,
.init_early = omap_3430sdp_init_early,
.init_irq = omap_init_irq,
.init_machine = omap_3430sdp_init,
.timer = &omap_timer,
MACHINE_END

15
arch/arm/mach-omap2/board-3630sdp.c
View File

@ -11,6 +11,7 @@
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/mtd/nand.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -69,14 +70,11 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
static struct omap_board_config_kernel sdp_config[] __initdata = {
};
static void __init omap_sdp_init_irq(void)
static void __init omap_sdp_init_early(void)
{
omap_board_config = sdp_config;
omap_board_config_size = ARRAY_SIZE(sdp_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
h8mbx00u0mer0em_sdrc_params);
omap_init_irq();
}
#ifdef CONFIG_OMAP_MUX
@ -206,19 +204,22 @@ static struct flash_partitions sdp_flash_partitions[] = {
static void __init omap_sdp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
omap_board_config = sdp_config;
omap_board_config_size = ARRAY_SIZE(sdp_config);
zoom_peripherals_init();
zoom_display_init();
board_smc91x_init();
board_flash_init(sdp_flash_partitions, chip_sel_sdp);
board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
enable_board_wakeup_source();
usbhs_init(&usbhs_bdata);
}
MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = omap_sdp_init_irq,
.map_io = omap3_map_io,
.init_early = omap_sdp_init_early,
.init_irq = omap_init_irq,
.init_machine = omap_sdp_init,
.timer = &omap_timer,
MACHINE_END

190
arch/arm/mach-omap2/board-4430sdp.c
View File

@ -35,6 +35,7 @@
#include <plat/common.h>
#include <plat/usb.h>
#include <plat/mmc.h>
#include <plat/omap4-keypad.h>
#include "mux.h"
#include "hsmmc.h"
@ -47,6 +48,90 @@
#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
#define OMAP4_SFH7741_ENABLE_GPIO 188
static const int sdp4430_keymap[] = {
KEY(0, 0, KEY_E),
KEY(0, 1, KEY_R),
KEY(0, 2, KEY_T),
KEY(0, 3, KEY_HOME),
KEY(0, 4, KEY_F5),
KEY(0, 5, KEY_UNKNOWN),
KEY(0, 6, KEY_I),
KEY(0, 7, KEY_LEFTSHIFT),
KEY(1, 0, KEY_D),
KEY(1, 1, KEY_F),
KEY(1, 2, KEY_G),
KEY(1, 3, KEY_SEND),
KEY(1, 4, KEY_F6),
KEY(1, 5, KEY_UNKNOWN),
KEY(1, 6, KEY_K),
KEY(1, 7, KEY_ENTER),
KEY(2, 0, KEY_X),
KEY(2, 1, KEY_C),
KEY(2, 2, KEY_V),
KEY(2, 3, KEY_END),
KEY(2, 4, KEY_F7),
KEY(2, 5, KEY_UNKNOWN),
KEY(2, 6, KEY_DOT),
KEY(2, 7, KEY_CAPSLOCK),
KEY(3, 0, KEY_Z),
KEY(3, 1, KEY_KPPLUS),
KEY(3, 2, KEY_B),
KEY(3, 3, KEY_F1),
KEY(3, 4, KEY_F8),
KEY(3, 5, KEY_UNKNOWN),
KEY(3, 6, KEY_O),
KEY(3, 7, KEY_SPACE),
KEY(4, 0, KEY_W),
KEY(4, 1, KEY_Y),
KEY(4, 2, KEY_U),
KEY(4, 3, KEY_F2),
KEY(4, 4, KEY_VOLUMEUP),
KEY(4, 5, KEY_UNKNOWN),
KEY(4, 6, KEY_L),
KEY(4, 7, KEY_LEFT),
KEY(5, 0, KEY_S),
KEY(5, 1, KEY_H),
KEY(5, 2, KEY_J),
KEY(5, 3, KEY_F3),
KEY(5, 4, KEY_F9),
KEY(5, 5, KEY_VOLUMEDOWN),
KEY(5, 6, KEY_M),
KEY(5, 7, KEY_RIGHT),
KEY(6, 0, KEY_Q),
KEY(6, 1, KEY_A),
KEY(6, 2, KEY_N),
KEY(6, 3, KEY_BACK),
KEY(6, 4, KEY_BACKSPACE),
KEY(6, 5, KEY_UNKNOWN),
KEY(6, 6, KEY_P),
KEY(6, 7, KEY_UP),
KEY(7, 0, KEY_PROG1),
KEY(7, 1, KEY_PROG2),
KEY(7, 2, KEY_PROG3),
KEY(7, 3, KEY_PROG4),
KEY(7, 4, KEY_F4),
KEY(7, 5, KEY_UNKNOWN),
KEY(7, 6, KEY_OK),
KEY(7, 7, KEY_DOWN),
};
static struct matrix_keymap_data sdp4430_keymap_data = {
.keymap = sdp4430_keymap,
.keymap_size = ARRAY_SIZE(sdp4430_keymap),
};
static struct omap4_keypad_platform_data sdp4430_keypad_data = {
.keymap_data = &sdp4430_keymap_data,
.rows = 8,
.cols = 8,
};
static struct gpio_led sdp4430_gpio_leds[] = {
{
.name = "omap4:green:debug0",
@ -238,16 +323,13 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
{ OMAP_TAG_LCD, &sdp4430_lcd_config },
};
static void __init omap_4430sdp_init_irq(void)
static void __init omap_4430sdp_init_early(void)
{
omap_board_config = sdp4430_config;
omap_board_config_size = ARRAY_SIZE(sdp4430_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(1);
#endif
gic_init_irq();
}
static struct omap_musb_board_data musb_board_data = {
@ -265,11 +347,6 @@ static struct twl4030_usb_data omap4_usbphy_data = {
};
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_wp = -EINVAL,
},
{
.mmc = 2,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
@ -278,19 +355,24 @@ static struct omap2_hsmmc_info mmc[] = {
.nonremovable = true,
.ocr_mask = MMC_VDD_29_30,
},
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_wp = -EINVAL,
},
{} /* Terminator */
};
static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
{
.supply = "vmmc",
.dev_name = "mmci-omap-hs.1",
.dev_name = "omap_hsmmc.1",
},
};
static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
{
.supply = "vmmc",
.dev_name = "mmci-omap-hs.0",
.dev_name = "omap_hsmmc.0",
},
};
@ -424,7 +506,6 @@ static struct regulator_init_data sdp4430_vana = {
.constraints = {
.min_uV = 2100000,
.max_uV = 2100000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
@ -436,7 +517,6 @@ static struct regulator_init_data sdp4430_vcxio = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
@ -448,7 +528,6 @@ static struct regulator_init_data sdp4430_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
@ -547,9 +626,76 @@ static struct omap_board_mux board_mux[] __initdata = {
OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static struct omap_device_pad serial2_pads[] __initdata = {
OMAP_MUX_STATIC("uart2_cts.uart2_cts",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rts.uart2_rts",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rx.uart2_rx",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_tx.uart2_tx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_device_pad serial3_pads[] __initdata = {
OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_device_pad serial4_pads[] __initdata = {
OMAP_MUX_STATIC("uart4_rx.uart4_rx",
OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart4_tx.uart4_tx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_board_data serial2_data = {
.id = 1,
.pads = serial2_pads,
.pads_cnt = ARRAY_SIZE(serial2_pads),
};
static struct omap_board_data serial3_data = {
.id = 2,
.pads = serial3_pads,
.pads_cnt = ARRAY_SIZE(serial3_pads),
};
static struct omap_board_data serial4_data = {
.id = 3,
.pads = serial4_pads,
.pads_cnt = ARRAY_SIZE(serial4_pads),
};
static inline void board_serial_init(void)
{
struct omap_board_data bdata;
bdata.flags = 0;
bdata.pads = NULL;
bdata.pads_cnt = 0;
bdata.id = 0;
/* pass dummy data for UART1 */
omap_serial_init_port(&bdata);
omap_serial_init_port(&serial2_data);
omap_serial_init_port(&serial3_data);
omap_serial_init_port(&serial4_data);
}
#else
#define board_mux NULL
#endif
static inline void board_serial_init(void)
{
omap_serial_init();
}
#endif
static void __init omap_4430sdp_init(void)
{
@ -560,10 +706,13 @@ static void __init omap_4430sdp_init(void)
package = OMAP_PACKAGE_CBL;
omap4_mux_init(board_mux, package);
omap_board_config = sdp4430_config;
omap_board_config_size = ARRAY_SIZE(sdp4430_config);
omap4_i2c_init();
omap_sfh7741prox_init();
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
omap_serial_init();
board_serial_init();
omap4_twl6030_hsmmc_init(mmc);
usb_musb_init(&musb_board_data);
@ -576,6 +725,10 @@ static void __init omap_4430sdp_init(void)
spi_register_board_info(sdp4430_spi_board_info,
ARRAY_SIZE(sdp4430_spi_board_info));
}
status = omap4_keyboard_init(&sdp4430_keypad_data);
if (status)
pr_err("Keypad initialization failed: %d\n", status);
}
static void __init omap_4430sdp_map_io(void)
@ -587,9 +740,10 @@ static void __init omap_4430sdp_map_io(void)
MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
/* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
.boot_params = 0x80000100,
.map_io = omap_4430sdp_map_io,
.reserve = omap_reserve,
.init_irq = omap_4430sdp_init_irq,
.map_io = omap_4430sdp_map_io,
.init_early = omap_4430sdp_init_early,
.init_irq = gic_init_irq,
.init_machine = omap_4430sdp_init,
.timer = &omap_timer,
MACHINE_END

14
arch/arm/mach-omap2/board-am3517crane.c
View File

@ -49,14 +49,10 @@ static struct omap_board_mux board_mux[] __initdata = {
#define board_mux NULL
#endif
static void __init am3517_crane_init_irq(void)
static void __init am3517_crane_init_early(void)
{
omap_board_config = am3517_crane_config;
omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
omap_init_irq();
}
static struct usbhs_omap_board_data usbhs_bdata __initdata = {
@ -77,6 +73,9 @@ static void __init am3517_crane_init(void)
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_serial_init();
omap_board_config = am3517_crane_config;
omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
/* Configure GPIO for EHCI port */
if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
@ -108,9 +107,10 @@ static void __init am3517_crane_init(void)
MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = am3517_crane_init_irq,
.map_io = omap3_map_io,
.init_early = am3517_crane_init_early,
.init_irq = omap_init_irq,
.init_machine = am3517_crane_init,
.timer = &omap_timer,
MACHINE_END

41
arch/arm/mach-omap2/board-am3517evm.c
View File

@ -199,6 +199,9 @@ static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = {
.gpio_base = OMAP_MAX_GPIO_LINES,
};
static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = {
{
I2C_BOARD_INFO("tlv320aic23", 0x1A),
},
{
I2C_BOARD_INFO("tca6416", 0x21),
.platform_data = &am3517evm_gpio_expander_info_0,
@ -378,37 +381,23 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
.default_device = &am3517_evm_lcd_device,
};
static struct platform_device am3517_evm_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &am3517_evm_dss_data,
},
};
/*
* Board initialization
*/
static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
};
static struct platform_device *am3517_evm_devices[] __initdata = {
&am3517_evm_dss_device,
};
static void __init am3517_evm_init_irq(void)
static void __init am3517_evm_init_early(void)
{
omap_board_config = am3517_evm_config;
omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
omap_init_irq();
}
static struct omap_musb_board_data musb_board_data = {
.interface_type = MUSB_INTERFACE_ULPI,
.mode = MUSB_OTG,
.power = 500,
.set_phy_power = am35x_musb_phy_power,
.clear_irq = am35x_musb_clear_irq,
.set_mode = am35x_musb_set_mode,
.reset = am35x_musb_reset,
};
static __init void am3517_evm_musb_init(void)
@ -490,14 +479,17 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
platform_device_register(&am3517_hecc_device);
}
static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
};
static void __init am3517_evm_init(void)
{
omap_board_config = am3517_evm_config;
omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
am3517_evm_i2c_init();
platform_add_devices(am3517_evm_devices,
ARRAY_SIZE(am3517_evm_devices));
omap_display_init(&am3517_evm_dss_data);
omap_serial_init();
/* Configure GPIO for EHCI port */
@ -521,9 +513,10 @@ static void __init am3517_evm_init(void)
MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = am3517_evm_init_irq,
.map_io = omap3_map_io,
.init_early = am3517_evm_init_early,
.init_irq = omap_init_irq,
.init_machine = am3517_evm_init,
.timer = &omap_timer,
MACHINE_END

12
arch/arm/mach-omap2/board-apollon.c
View File

@ -274,13 +274,10 @@ static struct omap_board_config_kernel apollon_config[] __initdata = {
{ OMAP_TAG_LCD, &apollon_lcd_config },
};
static void __init omap_apollon_init_irq(void)
static void __init omap_apollon_init_early(void)
{
omap_board_config = apollon_config;
omap_board_config_size = ARRAY_SIZE(apollon_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
omap_init_irq();
}
static void __init apollon_led_init(void)
@ -320,6 +317,8 @@ static void __init omap_apollon_init(void)
u32 v;
omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
omap_board_config = apollon_config;
omap_board_config_size = ARRAY_SIZE(apollon_config);
apollon_init_smc91x();
apollon_led_init();
@ -355,9 +354,10 @@ static void __init omap_apollon_map_io(void)
MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
.boot_params = 0x80000100,
.map_io = omap_apollon_map_io,
.reserve = omap_reserve,
.init_irq = omap_apollon_init_irq,
.map_io = omap_apollon_map_io,
.init_early = omap_apollon_init_early,
.init_irq = omap_init_irq,
.init_machine = omap_apollon_init,
.timer = &omap_timer,
MACHINE_END

43
arch/arm/mach-omap2/board-cm-t35.c
View File

@ -401,14 +401,6 @@ static struct omap_dss_board_info cm_t35_dss_data = {
.default_device = &cm_t35_dvi_device,
};
static struct platform_device cm_t35_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &cm_t35_dss_data,
},
};
static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
.turbo_mode = 0,
.single_channel = 1, /* 0: slave, 1: master */
@ -468,7 +460,7 @@ static void __init cm_t35_init_display(void)
msleep(50);
gpio_set_value(lcd_en_gpio, 1);
err = platform_device_register(&cm_t35_dss_device);
err = omap_display_init(&cm_t35_dss_data);
if (err) {
pr_err("CM-T35: failed to register DSS device\n");
goto err_dev_reg;
@ -495,15 +487,11 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
.supply = "vmmc_aux",
};
static struct regulator_consumer_supply cm_t35_vdac_supply = {
.supply = "vdda_dac",
.dev = &cm_t35_dss_device.dev,
};
static struct regulator_consumer_supply cm_t35_vdac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
static struct regulator_consumer_supply cm_t35_vdvi_supply = {
.supply = "vdvi",
.dev = &cm_t35_dss_device.dev,
};
static struct regulator_consumer_supply cm_t35_vdvi_supply =
REGULATOR_SUPPLY("vdvi", "omapdss");
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data cm_t35_vmmc1 = {
@ -680,20 +668,14 @@ static void __init cm_t35_init_i2c(void)
ARRAY_SIZE(cm_t35_i2c_boardinfo));
}
static struct omap_board_config_kernel cm_t35_config[] __initdata = {
};
static void __init cm_t35_init_irq(void)
static void __init cm_t35_init_early(void)
{
omap_board_config = cm_t35_config;
omap_board_config_size = ARRAY_SIZE(cm_t35_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* nCS and IRQ for CM-T35 ethernet */
OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
@ -791,6 +773,7 @@ static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
static struct omap_musb_board_data musb_board_data = {
.interface_type = MUSB_INTERFACE_ULPI,
@ -798,8 +781,13 @@ static struct omap_musb_board_data musb_board_data = {
.power = 100,
};
static struct omap_board_config_kernel cm_t35_config[] __initdata = {
};
static void __init cm_t35_init(void)
{
omap_board_config = cm_t35_config;
omap_board_config_size = ARRAY_SIZE(cm_t35_config);
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
omap_serial_init();
cm_t35_init_i2c();
@ -815,9 +803,10 @@ static void __init cm_t35_init(void)
MACHINE_START(CM_T35, "Compulab CM-T35")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = cm_t35_init_irq,
.map_io = omap3_map_io,
.init_early = cm_t35_init_early,
.init_irq = omap_init_irq,
.init_machine = cm_t35_init,
.timer = &omap_timer,
MACHINE_END

15
arch/arm/mach-omap2/board-cm-t3517.c
View File

@ -254,16 +254,13 @@ static inline void cm_t3517_init_nand(void) {}
static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
};
static void __init cm_t3517_init_irq(void)
static void __init cm_t3517_init_early(void)
{
omap_board_config = cm_t3517_config;
omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
omap_init_irq();
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* GPIO186 - Green LED */
OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
@ -289,11 +286,14 @@ static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
static void __init cm_t3517_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_serial_init();
omap_board_config = cm_t3517_config;
omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
cm_t3517_init_leds();
cm_t3517_init_nand();
cm_t3517_init_rtc();
@ -303,9 +303,10 @@ static void __init cm_t3517_init(void)
MACHINE_START(CM_T3517, "Compulab CM-T3517")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = cm_t3517_init_irq,
.map_io = omap3_map_io,
.init_early = cm_t3517_init_early,
.init_irq = omap_init_irq,
.init_machine = cm_t3517_init,
.timer = &omap_timer,
MACHINE_END

27
arch/arm/mach-omap2/board-devkit8000.c
View File

@ -140,7 +140,7 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
}
static struct regulator_consumer_supply devkit8000_vmmc1_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
/* ads7846 on SPI */
@ -195,14 +195,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
.default_device = &devkit8000_lcd_device,
};
static struct platform_device devkit8000_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &devkit8000_dss_data,
},
};
static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
@ -350,9 +342,7 @@ static struct twl4030_usb_data devkit8000_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_codec_audio_data devkit8000_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_audio_data devkit8000_audio_data;
static struct twl4030_codec_data devkit8000_codec_data = {
.audio_mclk = 26000000,
@ -456,11 +446,15 @@ static struct platform_device keys_gpio = {
};
static void __init devkit8000_init_irq(void)
static void __init devkit8000_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
}
static void __init devkit8000_init_irq(void)
{
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
@ -575,7 +569,6 @@ static void __init omap_dm9000_init(void)
}
static struct platform_device *devkit8000_devices[] __initdata = {
&devkit8000_dss_device,
&leds_gpio,
&keys_gpio,
&omap_dm9000_dev,
@ -632,6 +625,7 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* nCS and IRQ for Devkit8000 ethernet */
OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE0),
@ -785,6 +779,7 @@ static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
static void __init devkit8000_init(void)
{
@ -797,6 +792,7 @@ static void __init devkit8000_init(void)
platform_add_devices(devkit8000_devices,
ARRAY_SIZE(devkit8000_devices));
omap_display_init(&devkit8000_dss_data);
spi_register_board_info(devkit8000_spi_board_info,
ARRAY_SIZE(devkit8000_spi_board_info));
@ -813,8 +809,9 @@ static void __init devkit8000_init(void)
MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = devkit8000_init_early,
.init_irq = devkit8000_init_irq,
.init_machine = devkit8000_init,
.timer = &omap_timer,

32
arch/arm/mach-omap2/board-flash.c
View File

@ -1,5 +1,5 @@
/*
* board-sdp-flash.c
* board-flash.c
* Modified from mach-omap2/board-3430sdp-flash.c
*
* Copyright (C) 2009 Nokia Corporation
@ -16,6 +16,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <plat/irqs.h>
#include <plat/gpmc.h>
#include <plat/nand.h>
@ -73,11 +74,11 @@ __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
+ FLASH_SIZE_SDPV1 - 1;
}
if (err < 0) {
printk(KERN_ERR "NOR: Can't request GPMC CS\n");
pr_err("NOR: Can't request GPMC CS\n");
return;
}
if (platform_device_register(&board_nor_device) < 0)
printk(KERN_ERR "Unable to register NOR device\n");
pr_err("Unable to register NOR device\n");
}
#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
@ -139,17 +140,21 @@ static struct omap_nand_platform_data board_nand_data = {
};
void
__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
__init board_nand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs, int nand_type)
{
board_nand_data.cs = cs;
board_nand_data.parts = nand_parts;
board_nand_data.nr_parts = nr_parts;
board_nand_data.devsize = nand_type;
board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
gpmc_nand_init(&board_nand_data);
}
#else
void
__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type)
{
}
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@ -189,12 +194,12 @@ unmap:
}
/**
* sdp3430_flash_init - Identify devices connected to GPMC and register.
* board_flash_init - Identify devices connected to GPMC and register.
*
* @return - void.
*/
void board_flash_init(struct flash_partitions partition_info[],
char chip_sel_board[][GPMC_CS_NUM])
char chip_sel_board[][GPMC_CS_NUM], int nand_type)
{
u8 cs = 0;
u8 norcs = GPMC_CS_NUM + 1;
@ -208,7 +213,7 @@ void board_flash_init(struct flash_partitions partition_info[],
*/
idx = get_gpmc0_type();
if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs);
pr_err("%s: Invalid chip select: %d\n", __func__, cs);
return;
}
config_sel = (unsigned char *)(chip_sel_board[idx]);
@ -232,23 +237,20 @@ void board_flash_init(struct flash_partitions partition_info[],
}
if (norcs > GPMC_CS_NUM)
printk(KERN_INFO "NOR: Unable to find configuration "
"in GPMC\n");
pr_err("NOR: Unable to find configuration in GPMC\n");
else
board_nor_init(partition_info[0].parts,
partition_info[0].nr_parts, norcs);
if (onenandcs > GPMC_CS_NUM)
printk(KERN_INFO "OneNAND: Unable to find configuration "
"in GPMC\n");
pr_err("OneNAND: Unable to find configuration in GPMC\n");
else
board_onenand_init(partition_info[1].parts,
partition_info[1].nr_parts, onenandcs);
if (nandcs > GPMC_CS_NUM)
printk(KERN_INFO "NAND: Unable to find configuration "
"in GPMC\n");
pr_err("NAND: Unable to find configuration in GPMC\n");
else
board_nand_init(partition_info[2].parts,
partition_info[2].nr_parts, nandcs);
partition_info[2].nr_parts, nandcs, nand_type);
}

4
arch/arm/mach-omap2/board-flash.h
View File

@ -25,6 +25,6 @@ struct flash_partitions {
};
extern void board_flash_init(struct flash_partitions [],
char chip_sel[][GPMC_CS_NUM]);
char chip_sel[][GPMC_CS_NUM], int nand_type);
extern void board_nand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs);
u8 nr_parts, u8 cs, int nand_type);

12
arch/arm/mach-omap2/board-generic.c
View File

@ -33,18 +33,17 @@
static struct omap_board_config_kernel generic_config[] = {
};
static void __init omap_generic_init_irq(void)
static void __init omap_generic_init_early(void)
{
omap_board_config = generic_config;
omap_board_config_size = ARRAY_SIZE(generic_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
omap_init_irq();
}
static void __init omap_generic_init(void)
{
omap_serial_init();
omap_board_config = generic_config;
omap_board_config_size = ARRAY_SIZE(generic_config);
}
static void __init omap_generic_map_io(void)
@ -68,9 +67,10 @@ static void __init omap_generic_map_io(void)
MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
/* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
.boot_params = 0x80000100,
.map_io = omap_generic_map_io,
.reserve = omap_reserve,
.init_irq = omap_generic_init_irq,
.map_io = omap_generic_map_io,
.init_early = omap_generic_init_early,
.init_irq = omap_init_irq,
.init_machine = omap_generic_init,
.timer = &omap_timer,
MACHINE_END

16
arch/arm/mach-omap2/board-h4.c
View File

@ -290,14 +290,15 @@ static struct omap_board_config_kernel h4_config[] __initdata = {
{ OMAP_TAG_LCD, &h4_lcd_config },
};
static void __init omap_h4_init_irq(void)
static void __init omap_h4_init_early(void)
{
omap_board_config = h4_config;
omap_board_config_size = ARRAY_SIZE(h4_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
}
static void __init omap_h4_init_irq(void)
{
omap_init_irq();
h4_init_flash();
}
static struct at24_platform_data m24c01 = {
@ -330,6 +331,9 @@ static void __init omap_h4_init(void)
{
omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
omap_board_config = h4_config;
omap_board_config_size = ARRAY_SIZE(h4_config);
/*
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on
@ -367,6 +371,7 @@ static void __init omap_h4_init(void)
platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
omap2_usbfs_init(&h4_usb_config);
omap_serial_init();
h4_init_flash();
}
static void __init omap_h4_map_io(void)
@ -378,8 +383,9 @@ static void __init omap_h4_map_io(void)
MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
/* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
.boot_params = 0x80000100,
.map_io = omap_h4_map_io,
.reserve = omap_reserve,
.map_io = omap_h4_map_io,
.init_early = omap_h4_init_early,
.init_irq = omap_h4_init_irq,
.init_machine = omap_h4_init,
.timer = &omap_timer,

34
arch/arm/mach-omap2/board-igep0020.c
View File

@ -250,7 +250,7 @@ static inline void __init igep2_init_smsc911x(void) { }
#endif
static struct regulator_consumer_supply igep2_vmmc1_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
static struct regulator_init_data igep2_vmmc1 = {
@ -268,7 +268,7 @@ static struct regulator_init_data igep2_vmmc1 = {
};
static struct regulator_consumer_supply igep2_vio_supply =
REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
static struct regulator_init_data igep2_vio = {
.constraints = {
@ -286,7 +286,7 @@ static struct regulator_init_data igep2_vio = {
};
static struct regulator_consumer_supply igep2_vmmc2_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
static struct regulator_init_data igep2_vmmc2 = {
.constraints = {
@ -485,18 +485,8 @@ static struct omap_dss_board_info igep2_dss_data = {
.default_device = &igep2_dvi_device,
};
static struct platform_device igep2_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &igep2_dss_data,
},
};
static struct regulator_consumer_supply igep2_vpll2_supply = {
.supply = "vdds_dsi",
.dev = &igep2_dss_device.dev,
};
static struct regulator_consumer_supply igep2_vpll2_supply =
REGULATOR_SUPPLY("vdds_dsi", "omapdss");
static struct regulator_init_data igep2_vpll2 = {
.constraints = {
@ -521,21 +511,17 @@ static void __init igep2_display_init(void)
}
static struct platform_device *igep2_devices[] __initdata = {
&igep2_dss_device,
&igep2_vwlan_device,
};
static void __init igep2_init_irq(void)
static void __init igep2_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(m65kxxxxam_sdrc_params,
m65kxxxxam_sdrc_params);
omap_init_irq();
}
static struct twl4030_codec_audio_data igep2_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_audio_data igep2_audio_data;
static struct twl4030_codec_data igep2_codec_data = {
.audio_mclk = 26000000,
@ -697,6 +683,7 @@ static void __init igep2_init(void)
/* Register I2C busses and drivers */
igep2_i2c_init();
platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
omap_display_init(&igep2_dss_data);
omap_serial_init();
usb_musb_init(&musb_board_data);
usbhs_init(&usbhs_bdata);
@ -716,9 +703,10 @@ static void __init igep2_init(void)
MACHINE_START(IGEP0020, "IGEP v2 board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = igep2_init_irq,
.map_io = omap3_map_io,
.init_early = igep2_init_early,
.init_irq = omap_init_irq,
.init_machine = igep2_init,
.timer = &omap_timer,
MACHINE_END

12
arch/arm/mach-omap2/board-igep0030.c
View File

@ -142,7 +142,7 @@ static void __init igep3_flash_init(void) {}
#endif
static struct regulator_consumer_supply igep3_vmmc1_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
static struct regulator_init_data igep3_vmmc1 = {
@ -160,7 +160,7 @@ static struct regulator_init_data igep3_vmmc1 = {
};
static struct regulator_consumer_supply igep3_vio_supply =
REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
static struct regulator_init_data igep3_vio = {
.constraints = {
@ -178,7 +178,7 @@ static struct regulator_init_data igep3_vio = {
};
static struct regulator_consumer_supply igep3_vmmc2_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
static struct regulator_init_data igep3_vmmc2 = {
.constraints = {
@ -331,12 +331,11 @@ static struct platform_device *igep3_devices[] __initdata = {
&igep3_vwlan_device,
};
static void __init igep3_init_irq(void)
static void __init igep3_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(m65kxxxxam_sdrc_params,
m65kxxxxam_sdrc_params);
omap_init_irq();
}
static struct twl4030_platform_data igep3_twl4030_pdata = {
@ -452,7 +451,8 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
.boot_params = 0x80000100,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_irq = igep3_init_irq,
.init_early = igep3_init_early,
.init_irq = omap_init_irq,
.init_machine = igep3_init,
.timer = &omap_timer,
MACHINE_END

35
arch/arm/mach-omap2/board-ldp.c
View File

@ -288,13 +288,10 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
{ OMAP_TAG_LCD, &ldp_lcd_config },
};
static void __init omap_ldp_init_irq(void)
static void __init omap_ldp_init_early(void)
{
omap_board_config = ldp_config;
omap_board_config_size = ARRAY_SIZE(ldp_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
omap_init_irq();
}
static struct twl4030_usb_data ldp_usb_data = {
@ -330,6 +327,26 @@ static struct regulator_init_data ldp_vmmc1 = {
.consumer_supplies = &ldp_vmmc1_supply,
};
/* ads7846 on SPI */
static struct regulator_consumer_supply ldp_vaux1_supplies[] = {
REGULATOR_SUPPLY("vcc", "spi1.0"),
};
/* VAUX1 */
static struct regulator_init_data ldp_vaux1 = {
.constraints = {
.min_uV = 3000000,
.max_uV = 3000000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(ldp_vaux1_supplies),
.consumer_supplies = ldp_vaux1_supplies,
};
static struct twl4030_platform_data ldp_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
@ -338,6 +355,7 @@ static struct twl4030_platform_data ldp_twldata = {
.madc = &ldp_madc_data,
.usb = &ldp_usb_data,
.vmmc1 = &ldp_vmmc1,
.vaux1 = &ldp_vaux1,
.gpio = &ldp_gpio_data,
.keypad = &ldp_kp_twl4030_data,
};
@ -423,6 +441,8 @@ static struct mtd_partition ldp_nand_partitions[] = {
static void __init omap_ldp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_board_config = ldp_config;
omap_board_config_size = ARRAY_SIZE(ldp_config);
ldp_init_smsc911x();
omap_i2c_init();
platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
@ -434,7 +454,7 @@ static void __init omap_ldp_init(void)
omap_serial_init();
usb_musb_init(&musb_board_data);
board_nand_init(ldp_nand_partitions,
ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS);
ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
@ -443,9 +463,10 @@ static void __init omap_ldp_init(void)
MACHINE_START(OMAP_LDP, "OMAP LDP board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = omap_ldp_init_irq,
.map_io = omap3_map_io,
.init_early = omap_ldp_init_early,
.init_irq = omap_init_irq,
.init_machine = omap_ldp_init,
.timer = &omap_timer,
MACHINE_END

20
arch/arm/mach-omap2/board-n8x0.c
View File

@ -536,7 +536,7 @@ static void __init n8x0_mmc_init(void)
}
mmc_data[0] = &mmc1_data;
omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC);
omap242x_init_mmc(mmc_data);
}
#else
@ -628,11 +628,10 @@ static void __init n8x0_map_io(void)
omap242x_map_common_io();
}
static void __init n8x0_init_irq(void)
static void __init n8x0_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
omap_init_irq();
}
#ifdef CONFIG_OMAP_MUX
@ -703,27 +702,30 @@ static void __init n8x0_init_machine(void)
MACHINE_START(NOKIA_N800, "Nokia N800")
.boot_params = 0x80000100,
.map_io = n8x0_map_io,
.reserve = omap_reserve,
.init_irq = n8x0_init_irq,
.map_io = n8x0_map_io,
.init_early = n8x0_init_early,
.init_irq = omap_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
MACHINE_END
MACHINE_START(NOKIA_N810, "Nokia N810")
.boot_params = 0x80000100,
.map_io = n8x0_map_io,
.reserve = omap_reserve,
.init_irq = n8x0_init_irq,
.map_io = n8x0_map_io,
.init_early = n8x0_init_early,
.init_irq = omap_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
MACHINE_END
MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
.boot_params = 0x80000100,
.map_io = n8x0_map_io,
.reserve = omap_reserve,
.init_irq = n8x0_init_irq,
.map_io = n8x0_map_io,
.init_early = n8x0_init_early,
.init_irq = omap_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
MACHINE_END

73
arch/arm/mach-omap2/board-omap3beagle.c
View File

@ -23,6 +23,7 @@
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/opp.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@ -45,10 +46,12 @@
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/usb.h>
#include <plat/omap_device.h>
#include "mux.h"
#include "hsmmc.h"
#include "timer-gp.h"
#include "pm.h"
#define NAND_BLOCK_SIZE SZ_128K
@ -228,14 +231,6 @@ static struct omap_dss_board_info beagle_dss_data = {
.default_device = &beagle_dvi_device,
};
static struct platform_device beagle_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &beagle_dss_data,
},
};
static struct regulator_consumer_supply beagle_vdac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
@ -435,9 +430,7 @@ static struct twl4030_usb_data beagle_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_codec_audio_data beagle_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_audio_data beagle_audio_data;
static struct twl4030_codec_data beagle_codec_data = {
.audio_mclk = 26000000,
@ -536,11 +529,15 @@ static struct platform_device keys_gpio = {
},
};
static void __init omap3_beagle_init_irq(void)
static void __init omap3_beagle_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
}
static void __init omap3_beagle_init_irq(void)
{
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
@ -550,7 +547,6 @@ static void __init omap3_beagle_init_irq(void)
static struct platform_device *omap3_beagle_devices[] __initdata = {
&leds_gpio,
&keys_gpio,
&beagle_dss_device,
};
static void __init omap3beagle_flash_init(void)
@ -610,6 +606,52 @@ static struct omap_musb_board_data musb_board_data = {
.power = 100,
};
static void __init beagle_opp_init(void)
{
int r = 0;
/* Initialize the omap3 opp table */
if (omap3_opp_init()) {
pr_err("%s: opp default init failed\n", __func__);
return;
}
/* Custom OPP enabled for XM */
if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
struct omap_hwmod *mh = omap_hwmod_lookup("mpu");
struct omap_hwmod *dh = omap_hwmod_lookup("iva");
struct device *dev;
if (!mh || !dh) {
pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
__func__, mh, dh);
return;
}
/* Enable MPU 1GHz and lower opps */
dev = &mh->od->pdev.dev;
r = opp_enable(dev, 800000000);
/* TODO: MPU 1GHz needs SR and ABB */
/* Enable IVA 800MHz and lower opps */
dev = &dh->od->pdev.dev;
r |= opp_enable(dev, 660000000);
/* TODO: DSP 800MHz needs SR and ABB */
if (r) {
pr_err("%s: failed to enable higher opp %d\n",
__func__, r);
/*
* Cleanup - disable the higher freqs - we dont care
* about the results
*/
dev = &mh->od->pdev.dev;
opp_disable(dev, 800000000);
dev = &dh->od->pdev.dev;
opp_disable(dev, 660000000);
}
}
return;
}
static void __init omap3_beagle_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@ -617,6 +659,7 @@ static void __init omap3_beagle_init(void)
omap3_beagle_i2c_init();
platform_add_devices(omap3_beagle_devices,
ARRAY_SIZE(omap3_beagle_devices));
omap_display_init(&beagle_dss_data);
omap_serial_init();
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
@ -633,13 +676,15 @@ static void __init omap3_beagle_init(void)
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
beagle_display_init();
beagle_opp_init();
}
MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
/* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3_beagle_init_early,
.init_irq = omap3_beagle_init_irq,
.init_machine = omap3_beagle_init,
.timer = &omap_timer,

246
arch/arm/mach-omap2/board-omap3evm.c
View File

@ -30,6 +30,8 @@
#include <linux/usb/otg.h>
#include <linux/smsc911x.h>
#include <linux/wl12xx.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/mmc/host.h>
@ -58,6 +60,13 @@
#define OMAP3EVM_ETHR_ID_REV 0x50
#define OMAP3EVM_ETHR_GPIO_IRQ 176
#define OMAP3EVM_SMSC911X_CS 5
/*
* Eth Reset signal
* 64 = Generation 1 (<=RevD)
* 7 = Generation 2 (>=RevE)
*/
#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
static u8 omap3_evm_version;
@ -124,10 +133,15 @@ static struct platform_device omap3evm_smsc911x_device = {
static inline void __init omap3evm_init_smsc911x(void)
{
int eth_cs;
int eth_cs, eth_rst;
struct clk *l3ck;
unsigned int rate;
if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
eth_rst = OMAP3EVM_GEN1_ETHR_GPIO_RST;
else
eth_rst = OMAP3EVM_GEN2_ETHR_GPIO_RST;
eth_cs = OMAP3EVM_SMSC911X_CS;
l3ck = clk_get(NULL, "l3_ck");
@ -136,6 +150,27 @@ static inline void __init omap3evm_init_smsc911x(void)
else
rate = clk_get_rate(l3ck);
/* Configure ethernet controller reset gpio */
if (cpu_is_omap3430()) {
if (gpio_request(eth_rst, "SMSC911x gpio") < 0) {
pr_err(KERN_ERR "Failed to request %d for smsc911x\n",
eth_rst);
return;
}
if (gpio_direction_output(eth_rst, 1) < 0) {
pr_err(KERN_ERR "Failed to set direction of %d for" \
" smsc911x\n", eth_rst);
return;
}
/* reset pulse to ethernet controller*/
usleep_range(150, 220);
gpio_set_value(eth_rst, 0);
usleep_range(150, 220);
gpio_set_value(eth_rst, 1);
usleep_range(1, 2);
}
if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
OMAP3EVM_ETHR_GPIO_IRQ);
@ -235,9 +270,9 @@ static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
else
gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
lcd_enabled = 1;
return 0;
@ -248,9 +283,9 @@ static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
else
gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
lcd_enabled = 0;
}
@ -289,7 +324,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
return -EINVAL;
}
gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
dvi_enabled = 1;
return 0;
@ -297,7 +332,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
{
gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
dvi_enabled = 0;
}
@ -328,14 +363,6 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
.default_device = &omap3_evm_lcd_device,
};
static struct platform_device omap3_evm_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &omap3_evm_dss_data,
},
};
static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
.supply = "vmmc",
};
@ -381,6 +408,16 @@ static struct omap2_hsmmc_info mmc[] = {
.gpio_cd = -EINVAL,
.gpio_wp = 63,
},
#ifdef CONFIG_WL12XX_PLATFORM_DATA
{
.name = "wl1271",
.mmc = 2,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
.gpio_wp = -EINVAL,
.gpio_cd = -EINVAL,
.nonremovable = true,
},
#endif
{} /* Terminator */
};
@ -411,6 +448,8 @@ static struct platform_device leds_gpio = {
static int omap3evm_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
int r;
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
omap_mux_init_gpio(63, OMAP_PIN_INPUT);
mmc[0].gpio_cd = gpio + 0;
@ -426,8 +465,12 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
*/
/* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
if (!r)
r = gpio_direction_output(gpio + TWL4030_GPIO_MAX,
(get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0);
if (r)
printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
/* gpio + 7 == DVI Enable */
gpio_request(gpio + 7, "EN_DVI");
@ -491,19 +534,15 @@ static struct twl4030_madc_platform_data omap3evm_madc_data = {
.irq_line = 1,
};
static struct twl4030_codec_audio_data omap3evm_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_audio_data omap3evm_audio_data;
static struct twl4030_codec_data omap3evm_codec_data = {
.audio_mclk = 26000000,
.audio = &omap3evm_audio_data,
};
static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = {
.supply = "vdda_dac",
.dev = &omap3_evm_dss_device.dev,
};
static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
/* VDAC for DSS driving S-Video */
static struct regulator_init_data omap3_evm_vdac = {
@ -538,6 +577,66 @@ static struct regulator_init_data omap3_evm_vpll2 = {
.consumer_supplies = &omap3_evm_vpll2_supply,
};
/* ads7846 on SPI */
static struct regulator_consumer_supply omap3evm_vio_supply =
REGULATOR_SUPPLY("vcc", "spi1.0");
/* VIO for ads7846 */
static struct regulator_init_data omap3evm_vio = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3evm_vio_supply,
};
#ifdef CONFIG_WL12XX_PLATFORM_DATA
#define OMAP3EVM_WLAN_PMENA_GPIO (150)
#define OMAP3EVM_WLAN_IRQ_GPIO (149)
static struct regulator_consumer_supply omap3evm_vmmc2_supply =
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
/* VMMC2 for driving the WL12xx module */
static struct regulator_init_data omap3evm_vmmc2 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3evm_vmmc2_supply,
};
static struct fixed_voltage_config omap3evm_vwlan = {
.supply_name = "vwl1271",
.microvolts = 1800000, /* 1.80V */
.gpio = OMAP3EVM_WLAN_PMENA_GPIO,
.startup_delay = 70000, /* 70ms */
.enable_high = 1,
.enabled_at_boot = 0,
.init_data = &omap3evm_vmmc2,
};
static struct platform_device omap3evm_wlan_regulator = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &omap3evm_vwlan,
},
};
struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
.irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
.board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
};
#endif
static struct twl4030_platform_data omap3evm_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
@ -550,6 +649,7 @@ static struct twl4030_platform_data omap3evm_twldata = {
.codec = &omap3evm_codec_data,
.vdac = &omap3_evm_vdac,
.vpll2 = &omap3_evm_vpll2,
.vio = &omap3evm_vio,
};
static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = {
@ -625,19 +725,12 @@ static struct spi_board_info omap3evm_spi_board_info[] = {
static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
};
static void __init omap3_evm_init_irq(void)
static void __init omap3_evm_init_early(void)
{
omap_board_config = omap3_evm_config;
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
omap_init_irq();
}
static struct platform_device *omap3_evm_devices[] __initdata = {
&omap3_evm_dss_device,
};
static struct usbhs_omap_board_data usbhs_bdata __initdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
@ -652,14 +745,76 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
static struct omap_board_mux omap35x_board_mux[] __initdata = {
OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
OMAP_PIN_OFF_WAKEUPENABLE),
OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
OMAP_PIN_OFF_WAKEUPENABLE),
OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
OMAP_PIN_OFF_NONE),
OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
OMAP_PIN_OFF_NONE),
#ifdef CONFIG_WL12XX_PLATFORM_DATA
/* WLAN IRQ - GPIO 149 */
OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* WLAN POWER ENABLE - GPIO 150 */
OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
/* MMC2 SDIO pin muxes for WL12xx */
OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
#endif
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static struct omap_board_mux omap36x_board_mux[] __initdata = {
OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
OMAP_PIN_OFF_WAKEUPENABLE),
OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
OMAP_PIN_OFF_WAKEUPENABLE),
/* AM/DM37x EVM: DSS data bus muxed with sys_boot */
OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
#ifdef CONFIG_WL12XX_PLATFORM_DATA
/* WLAN IRQ - GPIO 149 */
OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* WLAN POWER ENABLE - GPIO 150 */
OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
/* MMC2 SDIO pin muxes for WL12xx */
OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
#endif
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap35x_board_mux NULL
#define omap36x_board_mux NULL
#endif
static struct omap_musb_board_data musb_board_data = {
@ -671,11 +826,18 @@ static struct omap_musb_board_data musb_board_data = {
static void __init omap3_evm_init(void)
{
omap3_evm_get_revision();
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
if (cpu_is_omap3630())
omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
else
omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
omap_board_config = omap3_evm_config;
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
omap3_evm_i2c_init();
platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
omap_display_init(&omap3_evm_dss_data);
spi_register_board_info(omap3evm_spi_board_info,
ARRAY_SIZE(omap3evm_spi_board_info));
@ -715,14 +877,22 @@ static void __init omap3_evm_init(void)
ads7846_dev_init();
omap3evm_init_smsc911x();
omap3_evm_display_init();
#ifdef CONFIG_WL12XX_PLATFORM_DATA
/* WL12xx WLAN Init */
if (wl12xx_set_platform_data(&omap3evm_wlan_data))
pr_err("error setting wl12xx data\n");
platform_device_register(&omap3evm_wlan_regulator);
#endif
}
MACHINE_START(OMAP3EVM, "OMAP3 EVM")
/* Maintainer: Syed Mohammed Khasim - Texas Instruments */
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = omap3_evm_init_irq,
.map_io = omap3_map_io,
.init_early = omap3_evm_init_early,
.init_irq = omap_init_irq,
.init_machine = omap3_evm_init,
.timer = &omap_timer,
MACHINE_END

9
arch/arm/mach-omap2/board-omap3logic.c
View File

@ -195,11 +195,10 @@ static inline void __init board_smsc911x_init(void)
gpmc_smsc911x_init(&board_smsc911x_data);
}
static void __init omap3logic_init_irq(void)
static void __init omap3logic_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
omap_init_irq();
}
#ifdef CONFIG_OMAP_MUX
@ -225,7 +224,8 @@ static void __init omap3logic_init(void)
MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.init_irq = omap3logic_init_irq,
.init_early = omap3logic_init_early,
.init_irq = omap_init_irq,
.init_machine = omap3logic_init,
.timer = &omap_timer,
MACHINE_END
@ -233,7 +233,8 @@ MACHINE_END
MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.init_irq = omap3logic_init_irq,
.init_early = omap3logic_init_early,
.init_irq = omap_init_irq,
.init_machine = omap3logic_init,
.timer = &omap_timer,
MACHINE_END

28
arch/arm/mach-omap2/board-omap3pandora.c
View File

@ -253,14 +253,6 @@ static struct omap_dss_board_info pandora_dss_data = {
.default_device = &pandora_lcd_device,
};
static struct platform_device pandora_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &pandora_dss_data,
},
};
static void pandora_wl1251_init_card(struct mmc_card *card)
{
/*
@ -341,13 +333,13 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
};
static struct regulator_consumer_supply pandora_vmmc1_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
static struct regulator_consumer_supply pandora_vmmc2_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
static struct regulator_consumer_supply pandora_vmmc3_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2");
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2");
static struct regulator_consumer_supply pandora_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
@ -524,9 +516,7 @@ static struct twl4030_usb_data omap3pandora_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_codec_audio_data omap3pandora_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_audio_data omap3pandora_audio_data;
static struct twl4030_codec_data omap3pandora_codec_data = {
.audio_mclk = 26000000,
@ -634,12 +624,11 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
}
};
static void __init omap3pandora_init_irq(void)
static void __init omap3pandora_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
}
static void __init pandora_wl1251_init(void)
@ -677,7 +666,6 @@ fail:
static struct platform_device *omap3pandora_devices[] __initdata = {
&pandora_leds_gpio,
&pandora_keys_gpio,
&pandora_dss_device,
&pandora_vwlan_device,
};
@ -712,6 +700,7 @@ static void __init omap3pandora_init(void)
pandora_wl1251_init();
platform_add_devices(omap3pandora_devices,
ARRAY_SIZE(omap3pandora_devices));
omap_display_init(&pandora_dss_data);
omap_serial_init();
spi_register_board_info(omap3pandora_spi_board_info,
ARRAY_SIZE(omap3pandora_spi_board_info));
@ -727,9 +716,10 @@ static void __init omap3pandora_init(void)
MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = omap3pandora_init_irq,
.map_io = omap3_map_io,
.init_early = omap3pandora_init_early,
.init_irq = omap_init_irq,
.init_machine = omap3pandora_init,
.timer = &omap_timer,
MACHINE_END

37
arch/arm/mach-omap2/board-omap3stalker.c
View File

@ -240,14 +240,6 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
.default_device = &omap3_stalker_dvi_device,
};
static struct platform_device omap3_stalker_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &omap3_stalker_dss_data,
},
};
static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
.supply = "vmmc",
};
@ -439,19 +431,15 @@ static struct twl4030_madc_platform_data omap3stalker_madc_data = {
.irq_line = 1,
};
static struct twl4030_codec_audio_data omap3stalker_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_audio_data omap3stalker_audio_data;
static struct twl4030_codec_data omap3stalker_codec_data = {
.audio_mclk = 26000000,
.audio = &omap3stalker_audio_data,
};
static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = {
.supply = "vdda_dac",
.dev = &omap3_stalker_dss_device.dev,
};
static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss");
/* VDAC for DSS driving S-Video */
static struct regulator_init_data omap3_stalker_vdac = {
@ -469,10 +457,8 @@ static struct regulator_init_data omap3_stalker_vdac = {
};
/* VPLL2 for digital video outputs */
static struct regulator_consumer_supply omap3_stalker_vpll2_supply = {
.supply = "vdds_dsi",
.dev = &omap3_stalker_lcd_device.dev,
};
static struct regulator_consumer_supply omap3_stalker_vpll2_supply =
REGULATOR_SUPPLY("vdds_dsi", "omapdss");
static struct regulator_init_data omap3_stalker_vpll2 = {
.constraints = {
@ -591,12 +577,14 @@ static struct spi_board_info omap3stalker_spi_board_info[] = {
static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
};
static void __init omap3_stalker_init_irq(void)
static void __init omap3_stalker_init_early(void)
{
omap_board_config = omap3_stalker_config;
omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
}
static void __init omap3_stalker_init_irq(void)
{
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
@ -604,7 +592,6 @@ static void __init omap3_stalker_init_irq(void)
}
static struct platform_device *omap3_stalker_devices[] __initdata = {
&omap3_stalker_dss_device,
&keys_gpio,
};
@ -638,12 +625,15 @@ static struct omap_musb_board_data musb_board_data = {
static void __init omap3_stalker_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
omap_board_config = omap3_stalker_config;
omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
omap3_stalker_i2c_init();
platform_add_devices(omap3_stalker_devices,
ARRAY_SIZE(omap3_stalker_devices));
omap_display_init(&omap3_stalker_dss_data);
spi_register_board_info(omap3stalker_spi_board_info,
ARRAY_SIZE(omap3stalker_spi_board_info));
@ -666,6 +656,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
/* Maintainer: Jason Lam -lzg@ema-tech.com */
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.init_early = omap3_stalker_init_early,
.init_irq = omap3_stalker_init_irq,
.init_machine = omap3_stalker_init,
.timer = &omap_timer,

20
arch/arm/mach-omap2/board-omap3touchbook.c
View File

@ -252,9 +252,7 @@ static struct twl4030_usb_data touchbook_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_codec_audio_data touchbook_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_audio_data touchbook_audio_data;
static struct twl4030_codec_data touchbook_codec_data = {
.audio_mclk = 26000000,
@ -415,14 +413,15 @@ static struct omap_board_mux board_mux[] __initdata = {
};
#endif
static void __init omap3_touchbook_init_irq(void)
static void __init omap3_touchbook_init_early(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_board_config = omap3_touchbook_config;
omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
}
static void __init omap3_touchbook_init_irq(void)
{
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
@ -510,6 +509,10 @@ static struct omap_musb_board_data musb_board_data = {
static void __init omap3_touchbook_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_board_config = omap3_touchbook_config;
omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
pm_power_off = omap3_touchbook_poweroff;
omap3_touchbook_i2c_init();
@ -538,8 +541,9 @@ static void __init omap3_touchbook_init(void)
MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
/* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3_touchbook_init_early,
.init_irq = omap3_touchbook_init_irq,
.init_machine = omap3_touchbook_init,
.timer = &omap_timer,

158
arch/arm/mach-omap2/board-omap4panda.c
View File

@ -26,6 +26,8 @@
#include <linux/usb/otg.h>
#include <linux/i2c/twl.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/wl12xx.h>
#include <mach/hardware.h>
#include <mach/omap4-common.h>
@ -45,6 +47,18 @@
#define GPIO_HUB_POWER 1
#define GPIO_HUB_NRESET 62
#define GPIO_WIFI_PMENA 43
#define GPIO_WIFI_IRQ 53
/* wl127x BT, FM, GPS connectivity chip */
static int wl1271_gpios[] = {46, -1, -1};
static struct platform_device wl1271_device = {
.name = "kim",
.id = -1,
.dev = {
.platform_data = &wl1271_gpios,
},
};
static struct gpio_led gpio_leds[] = {
{
@ -74,13 +88,13 @@ static struct platform_device leds_gpio = {
static struct platform_device *panda_devices[] __initdata = {
&leds_gpio,
&wl1271_device,
};
static void __init omap4_panda_init_irq(void)
static void __init omap4_panda_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
gic_init_irq();
}
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
@ -163,16 +177,62 @@ static struct omap2_hsmmc_info mmc[] = {
.gpio_wp = -EINVAL,
.gpio_cd = -EINVAL,
},
{
.name = "wl1271",
.mmc = 5,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
.gpio_wp = -EINVAL,
.gpio_cd = -EINVAL,
.ocr_mask = MMC_VDD_165_195,
.nonremovable = true,
},
{} /* Terminator */
};
static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
{
.supply = "vmmc",
.dev_name = "mmci-omap-hs.0",
.dev_name = "omap_hsmmc.0",
},
};
static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
.supply = "vmmc",
.dev_name = "omap_hsmmc.4",
};
static struct regulator_init_data panda_vmmc5 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap4_panda_vmmc5_supply,
};
static struct fixed_voltage_config panda_vwlan = {
.supply_name = "vwl1271",
.microvolts = 1800000, /* 1.8V */
.gpio = GPIO_WIFI_PMENA,
.startup_delay = 70000, /* 70msec */
.enable_high = 1,
.enabled_at_boot = 0,
.init_data = &panda_vmmc5,
};
static struct platform_device omap_vwlan_device = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &panda_vwlan,
},
};
struct wl12xx_platform_data omap_panda_wlan_data __initdata = {
.irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
/* PANDA ref clock is 38.4 MHz */
.board_ref_clock = 2,
};
static int omap4_twl6030_hsmmc_late_init(struct device *dev)
{
int ret = 0;
@ -306,7 +366,6 @@ static struct regulator_init_data omap4_panda_vana = {
.constraints = {
.min_uV = 2100000,
.max_uV = 2100000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
@ -318,7 +377,6 @@ static struct regulator_init_data omap4_panda_vcxio = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
@ -330,7 +388,6 @@ static struct regulator_init_data omap4_panda_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
@ -392,10 +449,90 @@ static int __init omap4_panda_i2c_init(void)
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* WLAN IRQ - GPIO 53 */
OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
/* WLAN POWER ENABLE - GPIO 43 */
OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
/* WLAN SDIO: MMC5 CMD */
OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
/* WLAN SDIO: MMC5 CLK */
OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
/* WLAN SDIO: MMC5 DAT[0-3] */
OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static struct omap_device_pad serial2_pads[] __initdata = {
OMAP_MUX_STATIC("uart2_cts.uart2_cts",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rts.uart2_rts",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_rx.uart2_rx",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart2_tx.uart2_tx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_device_pad serial3_pads[] __initdata = {
OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_device_pad serial4_pads[] __initdata = {
OMAP_MUX_STATIC("uart4_rx.uart4_rx",
OMAP_PIN_INPUT | OMAP_MUX_MODE0),
OMAP_MUX_STATIC("uart4_tx.uart4_tx",
OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
};
static struct omap_board_data serial2_data = {
.id = 1,
.pads = serial2_pads,
.pads_cnt = ARRAY_SIZE(serial2_pads),
};
static struct omap_board_data serial3_data = {
.id = 2,
.pads = serial3_pads,
.pads_cnt = ARRAY_SIZE(serial3_pads),
};
static struct omap_board_data serial4_data = {
.id = 3,
.pads = serial4_pads,
.pads_cnt = ARRAY_SIZE(serial4_pads),
};
static inline void board_serial_init(void)
{
struct omap_board_data bdata;
bdata.flags = 0;
bdata.pads = NULL;
bdata.pads_cnt = 0;
bdata.id = 0;
/* pass dummy data for UART1 */
omap_serial_init_port(&bdata);
omap_serial_init_port(&serial2_data);
omap_serial_init_port(&serial3_data);
omap_serial_init_port(&serial4_data);
}
#else
#define board_mux NULL
static inline void board_serial_init(void)
{
omap_serial_init();
}
#endif
static void __init omap4_panda_init(void)
@ -406,9 +543,13 @@ static void __init omap4_panda_init(void)
package = OMAP_PACKAGE_CBL;
omap4_mux_init(board_mux, package);
if (wl12xx_set_platform_data(&omap_panda_wlan_data))
pr_err("error setting wl12xx data\n");
omap4_panda_i2c_init();
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
omap_serial_init();
platform_device_register(&omap_vwlan_device);
board_serial_init();
omap4_twl6030_hsmmc_init(mmc);
omap4_ehci_init();
usb_musb_init(&musb_board_data);
@ -425,7 +566,8 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
.boot_params = 0x80000100,
.reserve = omap_reserve,
.map_io = omap4_panda_map_io,
.init_irq = omap4_panda_init_irq,
.init_early = omap4_panda_init_early,
.init_irq = gic_init_irq,
.init_machine = omap4_panda_init,
.timer = &omap_timer,
MACHINE_END

16
arch/arm/mach-omap2/board-overo.c
View File

@ -358,9 +358,7 @@ static struct regulator_init_data overo_vmmc1 = {
.consumer_supplies = &overo_vmmc1_supply,
};
static struct twl4030_codec_audio_data overo_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_audio_data overo_audio_data;
static struct twl4030_codec_data overo_codec_data = {
.audio_mclk = 26000000,
@ -409,14 +407,11 @@ static struct omap_board_config_kernel overo_config[] __initdata = {
{ OMAP_TAG_LCD, &overo_lcd_config },
};
static void __init overo_init_irq(void)
static void __init overo_init_early(void)
{
omap_board_config = overo_config;
omap_board_config_size = ARRAY_SIZE(overo_config);
omap2_init_common_infrastructure();
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
}
static struct platform_device *overo_devices[] __initdata = {
@ -449,6 +444,8 @@ static struct omap_musb_board_data musb_board_data = {
static void __init overo_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_board_config = overo_config;
omap_board_config_size = ARRAY_SIZE(overo_config);
overo_i2c_init();
platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
omap_serial_init();
@ -501,9 +498,10 @@ static void __init overo_init(void)
MACHINE_START(OVERO, "Gumstix Overo")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = overo_init_irq,
.map_io = omap3_map_io,
.init_early = overo_init_early,
.init_irq = omap_init_irq,
.init_machine = overo_init,
.timer = &omap_timer,
MACHINE_END

10
arch/arm/mach-omap2/board-rm680.c
View File

@ -33,7 +33,7 @@
#include "sdram-nokia.h"
static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
};
/* Fixed regulator for internal eMMC */
@ -138,14 +138,13 @@ static void __init rm680_peripherals_init(void)
omap2_hsmmc_init(mmc);
}
static void __init rm680_init_irq(void)
static void __init rm680_init_early(void)
{
struct omap_sdrc_params *sdrc_params;
omap2_init_common_infrastructure();
sdrc_params = nokia_get_sdram_timings();
omap2_init_common_devices(sdrc_params, sdrc_params);
omap_init_irq();
}
#ifdef CONFIG_OMAP_MUX
@ -176,9 +175,10 @@ static void __init rm680_map_io(void)
MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
.boot_params = 0x80000100,
.map_io = rm680_map_io,
.reserve = omap_reserve,
.init_irq = rm680_init_irq,
.map_io = rm680_map_io,
.init_early = rm680_init_early,
.init_irq = omap_init_irq,
.init_machine = rm680_init,
.timer = &omap_timer,
MACHINE_END

61
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@ -36,6 +36,8 @@
#include <sound/tlv320aic3x.h>
#include <sound/tpa6130a2-plat.h>
#include <media/radio-si4713.h>
#include <media/si4713.h>
#include <../drivers/staging/iio/light/tsl2563.h>
@ -47,6 +49,8 @@
#define RX51_WL1251_POWER_GPIO 87
#define RX51_WL1251_IRQ_GPIO 42
#define RX51_FMTX_RESET_GPIO 163
#define RX51_FMTX_IRQ 53
/* list all spi devices here */
enum {
@ -331,13 +335,13 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
};
static struct regulator_consumer_supply rx51_vmmc1_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
static struct regulator_consumer_supply rx51_vaux3_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
static struct regulator_consumer_supply rx51_vsim_supply =
REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
/* tlv320aic3x analog supplies */
@ -348,7 +352,7 @@ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
/* tpa6130a2 */
REGULATOR_SUPPLY("Vdd", "2-0060"),
/* Keep vmmc as last item. It is not iterated for newer boards */
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
};
static struct regulator_consumer_supply rx51_vio_supplies[] = {
@ -357,10 +361,14 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
REGULATOR_SUPPLY("DVDD", "2-0018"),
REGULATOR_SUPPLY("IOVDD", "2-0019"),
REGULATOR_SUPPLY("DVDD", "2-0019"),
/* Si4713 IO supply */
REGULATOR_SUPPLY("vio", "2-0063"),
};
static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
/* Si4713 supply */
REGULATOR_SUPPLY("vdd", "2-0063"),
};
static struct regulator_consumer_supply rx51_vdac_supply[] = {
@ -511,6 +519,41 @@ static struct regulator_init_data rx51_vio = {
.consumer_supplies = rx51_vio_supplies,
};
static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
.gpio_reset = RX51_FMTX_RESET_GPIO,
};
static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = {
I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH),
.platform_data = &rx51_si4713_i2c_data,
};
static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = {
.i2c_bus = 2,
.subdev_board_info = &rx51_si4713_board_info,
};
static struct platform_device rx51_si4713_dev __initdata_or_module = {
.name = "radio-si4713",
.id = -1,
.dev = {
.platform_data = &rx51_si4713_data,
},
};
static __init void rx51_init_si4713(void)
{
int err;
err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
if (err) {
printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
return;
}
rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ);
platform_device_register(&rx51_si4713_dev);
}
static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
{
/* FIXME this gpio setup is just a placeholder for now */
@ -699,6 +742,14 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
.resource_config = twl4030_rconfig,
};
struct twl4030_codec_vibra_data rx51_vibra_data __initdata = {
.coexist = 0,
};
struct twl4030_codec_data rx51_codec_data __initdata = {
.audio_mclk = 26000000,
.vibra = &rx51_vibra_data,
};
static struct twl4030_platform_data rx51_twldata __initdata = {
.irq_base = TWL4030_IRQ_BASE,
@ -710,6 +761,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
.madc = &rx51_madc_data,
.usb = &rx51_usb_data,
.power = &rx51_t2scripts_data,
.codec = &rx51_codec_data,
.vaux1 = &rx51_vaux1,
.vaux2 = &rx51_vaux2,
@ -921,6 +973,7 @@ void __init rx51_peripherals_init(void)
board_smc91x_init();
rx51_add_gpio_keys();
rx51_init_wl1251();
rx51_init_si4713();
spi_register_board_info(rx51_peripherals_spi_board_info,
ARRAY_SIZE(rx51_peripherals_spi_board_info));

15
arch/arm/mach-omap2/board-rx51-video.c
View File

@ -66,18 +66,6 @@ static struct omap_dss_board_info rx51_dss_board_info = {
.default_device = &rx51_lcd_device,
};
struct platform_device rx51_display_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &rx51_dss_board_info,
},
};
static struct platform_device *rx51_video_devices[] __initdata = {
&rx51_display_device,
};
static int __init rx51_video_init(void)
{
if (!machine_is_nokia_rx51())
@ -95,8 +83,7 @@ static int __init rx51_video_init(void)
gpio_direction_output(RX51_LCD_RESET_GPIO, 1);
platform_add_devices(rx51_video_devices,
ARRAY_SIZE(rx51_video_devices));
omap_display_init(&rx51_dss_board_info);
return 0;
}

14
arch/arm/mach-omap2/board-rx51.c
View File

@ -98,17 +98,13 @@ static struct omap_board_config_kernel rx51_config[] = {
{ OMAP_TAG_LCD, &rx51_lcd_config },
};
static void __init rx51_init_irq(void)
static void __init rx51_init_early(void)
{
struct omap_sdrc_params *sdrc_params;
omap_board_config = rx51_config;
omap_board_config_size = ARRAY_SIZE(rx51_config);
omap3_pm_init_cpuidle(rx51_cpuidle_params);
omap2_init_common_infrastructure();
sdrc_params = nokia_get_sdram_timings();
omap2_init_common_devices(sdrc_params, sdrc_params);
omap_init_irq();
}
extern void __init rx51_peripherals_init(void);
@ -128,6 +124,9 @@ static struct omap_musb_board_data musb_board_data = {
static void __init rx51_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_board_config = rx51_config;
omap_board_config_size = ARRAY_SIZE(rx51_config);
omap3_pm_init_cpuidle(rx51_cpuidle_params);
omap_serial_init();
usb_musb_init(&musb_board_data);
rx51_peripherals_init();
@ -149,9 +148,10 @@ static void __init rx51_map_io(void)
MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
/* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
.boot_params = 0x80000100,
.map_io = rx51_map_io,
.reserve = omap_reserve,
.init_irq = rx51_init_irq,
.map_io = rx51_map_io,
.init_early = rx51_init_early,
.init_irq = omap_init_irq,
.init_machine = rx51_init,
.timer = &omap_timer,
MACHINE_END

62
arch/arm/mach-omap2/board-ti8168evm.c Normal file
View File

@ -0,0 +1,62 @@
/*
* Code for TI8168 EVM.
*
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat/irqs.h>
#include <plat/board.h>
#include <plat/common.h>
static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
};
static void __init ti8168_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
}
static void __init ti8168_evm_init_irq(void)
{
omap_init_irq();
}
static void __init ti8168_evm_init(void)
{
omap_serial_init();
omap_board_config = ti8168_evm_config;
omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
}
static void __init ti8168_evm_map_io(void)
{
omap2_set_globals_ti816x();
omapti816x_map_common_io();
}
MACHINE_START(TI8168EVM, "ti8168evm")
/* Maintainer: Texas Instruments */
.boot_params = 0x80000100,
.map_io = ti8168_evm_map_io,
.init_early = ti8168_init_early,
.init_irq = ti8168_evm_init_irq,
.timer = &omap_timer,
.init_machine = ti8168_evm_init,
MACHINE_END

15
arch/arm/mach-omap2/board-zoom-display.c
View File

@ -130,14 +130,6 @@ static struct omap_dss_board_info zoom_dss_data = {
.default_device = &zoom_lcd_device,
};
static struct platform_device zoom_dss_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = &zoom_dss_data,
},
};
static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
.turbo_mode = 1,
.single_channel = 1, /* 0: slave, 1: master */
@ -153,14 +145,9 @@ static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
},
};
static struct platform_device *zoom_display_devices[] __initdata = {
&zoom_dss_device,
};
void __init zoom_display_init(void)
{
platform_add_devices(zoom_display_devices,
ARRAY_SIZE(zoom_display_devices));
omap_display_init(&zoom_dss_data);
spi_register_board_info(nec_8048_spi_board_info,
ARRAY_SIZE(nec_8048_spi_board_info));
zoom_lcd_panel_init();

6
arch/arm/mach-omap2/board-zoom-peripherals.c
View File

@ -118,7 +118,7 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = {
static struct regulator_consumer_supply zoom_vmmc3_supply = {
.supply = "vmmc",
.dev_name = "mmci-omap-hs.2",
.dev_name = "omap_hsmmc.2",
};
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
@ -322,9 +322,7 @@ static struct twl4030_madc_platform_data zoom_madc_data = {
.irq_line = 1,
};
static struct twl4030_codec_audio_data zoom_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_audio_data zoom_audio_data;
static struct twl4030_codec_data zoom_codec_data = {
.audio_mclk = 26000000,

21
arch/arm/mach-omap2/board-zoom.c
View File

@ -16,6 +16,7 @@
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/i2c/twl.h>
#include <linux/mtd/nand.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -33,7 +34,7 @@
#define ZOOM3_EHCI_RESET_GPIO 64
static void __init omap_zoom_init_irq(void)
static void __init omap_zoom_init_early(void)
{
omap2_init_common_infrastructure();
if (machine_is_omap_zoom2())
@ -42,14 +43,12 @@ static void __init omap_zoom_init_irq(void)
else if (machine_is_omap_zoom3())
omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
h8mbx00u0mer0em_sdrc_params);
omap_init_irq();
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* WLAN IRQ - GPIO 162 */
OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* WLAN POWER ENABLE - GPIO 101 */
OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
/* WLAN SDIO: MMC3 CMD */
@ -126,8 +125,8 @@ static void __init omap_zoom_init(void)
usbhs_init(&usbhs_bdata);
}
board_nand_init(zoom_nand_partitions,
ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
ZOOM_NAND_CS, NAND_BUSWIDTH_16);
zoom_debugboard_init();
zoom_peripherals_init();
zoom_display_init();
@ -135,18 +134,20 @@ static void __init omap_zoom_init(void)
MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = omap_zoom_init_irq,
.map_io = omap3_map_io,
.init_early = omap_zoom_init_early,
.init_irq = omap_init_irq,
.init_machine = omap_zoom_init,
.timer = &omap_timer,
MACHINE_END
MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.reserve = omap_reserve,
.init_irq = omap_zoom_init_irq,
.map_io = omap3_map_io,
.init_early = omap_zoom_init_early,
.init_irq = omap_init_irq,
.init_machine = omap_zoom_init,
.timer = &omap_timer,
MACHINE_END

24
arch/arm/mach-omap2/clkt2xxx_apll.c
View File

@ -78,6 +78,26 @@ static int omap2_clk_apll54_enable(struct clk *clk)
return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
}
static void _apll96_allow_idle(struct clk *clk)
{
omap2xxx_cm_set_apll96_auto_low_power_stop();
}
static void _apll96_deny_idle(struct clk *clk)
{
omap2xxx_cm_set_apll96_disable_autoidle();
}
static void _apll54_allow_idle(struct clk *clk)
{
omap2xxx_cm_set_apll54_auto_low_power_stop();
}
static void _apll54_deny_idle(struct clk *clk)
{
omap2xxx_cm_set_apll54_disable_autoidle();
}
/* Stop APLL */
static void omap2_clk_apll_disable(struct clk *clk)
{
@ -93,11 +113,15 @@ static void omap2_clk_apll_disable(struct clk *clk)
const struct clkops clkops_apll96 = {
.enable = omap2_clk_apll96_enable,
.disable = omap2_clk_apll_disable,
.allow_idle = _apll96_allow_idle,
.deny_idle = _apll96_deny_idle,
};
const struct clkops clkops_apll54 = {
.enable = omap2_clk_apll54_enable,
.disable = omap2_clk_apll_disable,
.allow_idle = _apll54_allow_idle,
.deny_idle = _apll54_deny_idle,
};
/* Public functions */

63
arch/arm/mach-omap2/clkt2xxx_dpll.c Normal file
View File

@ -0,0 +1,63 @@
/*
* OMAP2-specific DPLL control functions
*
* Copyright (C) 2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <plat/clock.h>
#include "clock.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
/* Private functions */
/**
* _allow_idle - enable DPLL autoidle bits
* @clk: struct clk * of the DPLL to operate on
*
* Enable DPLL automatic idle control. The DPLL will enter low-power
* stop when its downstream clocks are gated. No return value.
* REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
* instead. Add some mechanism to optionally enter this mode.
*/
static void _allow_idle(struct clk *clk)
{
if (!clk || !clk->dpll_data)
return;
omap2xxx_cm_set_dpll_auto_low_power_stop();
}
/**
* _deny_idle - prevent DPLL from automatically idling
* @clk: struct clk * of the DPLL to operate on
*
* Disable DPLL automatic idle control. No return value.
*/
static void _deny_idle(struct clk *clk)
{
if (!clk || !clk->dpll_data)
return;
omap2xxx_cm_set_dpll_disable_autoidle();
}
/* Public data */
const struct clkops clkops_omap2xxx_dpll_ops = {
.allow_idle = _allow_idle,
.deny_idle = _deny_idle,
};

14
arch/arm/mach-omap2/clkt2xxx_osc.c
View File

@ -30,6 +30,13 @@
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
/*
* XXX This does not actually enable the osc_ck, since the osc_ck must
* be running for this function to be called. Instead, this function
* is used to disable an autoidle mode on the osc_ck. The existing
* clk_enable/clk_disable()-based usecounting for osc_ck should be
* replaced with autoidle-based usecounting.
*/
static int omap2_enable_osc_ck(struct clk *clk)
{
u32 pcc;
@ -41,6 +48,13 @@ static int omap2_enable_osc_ck(struct clk *clk)
return 0;
}
/*
* XXX This does not actually disable the osc_ck, since doing so would
* immediately halt the system. Instead, this function is used to
* enable an autoidle mode on the osc_ck. The existing
* clk_enable/clk_disable()-based usecounting for osc_ck should be
* replaced with autoidle-based usecounting.
*/
static void omap2_disable_osc_ck(struct clk *clk)
{
u32 pcc;

2
arch/arm/mach-omap2/clkt_clksel.c
View File

@ -97,7 +97,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
u32 *field_val)
{
const struct clksel *clks;
const struct clksel_rate *clkr, *max_clkr;
const struct clksel_rate *clkr, *max_clkr = NULL;
u8 max_div = 0;
clks = _get_clksel_by_parent(clk, src_clk);

89
arch/arm/mach-omap2/clkt_dpll.c
View File

@ -178,12 +178,11 @@ void omap2_init_dpll_parent(struct clk *clk)
if (!dd)
return;
/* Return bypass rate if DPLL is bypassed */
v = __raw_readl(dd->control_reg);
v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask);
/* Reparent in case the dpll is in bypass */
/* Reparent the struct clk in case the dpll is in bypass */
if (cpu_is_omap24xx()) {
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
@ -259,51 +258,23 @@ u32 omap2_get_dpll_rate(struct clk *clk)
/* DPLL rate rounding code */
/**
* omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
* @clk: struct clk * of the DPLL
* @tolerance: maximum rate error tolerance
*
* Set the maximum DPLL rate error tolerance for the rate rounding
* algorithm. The rate tolerance is an attempt to balance DPLL power
* saving (the least divider value "n") vs. rate fidelity (the least
* difference between the desired DPLL target rate and the rounded
* rate out of the algorithm). So, increasing the tolerance is likely
* to decrease DPLL power consumption and increase DPLL rate error.
* Returns -EINVAL if provided a null clock ptr or a clk that is not a
* DPLL; or 0 upon success.
*/
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
{
if (!clk || !clk->dpll_data)
return -EINVAL;
clk->dpll_data->rate_tolerance = tolerance;
return 0;
}
/**
* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
* @clk: struct clk * for a DPLL
* @target_rate: desired DPLL clock rate
*
* Given a DPLL, a desired target rate, and a rate tolerance, round
* the target rate to a possible, programmable rate for this DPLL.
* Rate tolerance is assumed to be set by the caller before this
* function is called. Attempts to select the minimum possible n
* within the tolerance to reduce power consumption. Stores the
* computed (m, n) in the DPLL's dpll_data structure so set_rate()
* will not need to call this (expensive) function again. Returns ~0
* if the target rate cannot be rounded, either because the rate is
* too low or because the rate tolerance is set too tightly; or the
* rounded rate upon success.
* Given a DPLL and a desired target rate, round the target rate to a
* possible, programmable rate for this DPLL. Attempts to select the
* minimum possible n. Stores the computed (m, n) in the DPLL's
* dpll_data structure so set_rate() will not need to call this
* (expensive) function again. Returns ~0 if the target rate cannot
* be rounded, or the rounded rate upon success.
*/
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
{
int m, n, r, e, scaled_max_m;
unsigned long scaled_rt_rp, new_rate;
int min_e = -1, min_e_m = -1, min_e_n = -1;
int m, n, r, scaled_max_m;
unsigned long scaled_rt_rp;
unsigned long new_rate = 0;
struct dpll_data *dd;
if (!clk || !clk->dpll_data)
@ -311,8 +282,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
dd = clk->dpll_data;
pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
"%ld\n", clk->name, target_rate);
pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
clk->name, target_rate);
scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
@ -347,39 +318,23 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
if (r == DPLL_MULT_UNDERFLOW)
continue;
e = target_rate - new_rate;
pr_debug("clock: n = %d: m = %d: rate error is %d "
"(new_rate = %ld)\n", n, m, e, new_rate);
pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
clk->name, m, n, new_rate);
if (min_e == -1 ||
min_e >= (int)(abs(e) - dd->rate_tolerance)) {
min_e = e;
min_e_m = m;
min_e_n = n;
pr_debug("clock: found new least error %d\n", min_e);
/* We found good settings -- bail out now */
if (min_e <= dd->rate_tolerance)
if (target_rate == new_rate) {
dd->last_rounded_m = m;
dd->last_rounded_n = n;
dd->last_rounded_rate = target_rate;
break;
}
}
if (min_e < 0) {
pr_debug("clock: error: target rate or tolerance too low\n");
if (target_rate != new_rate) {
pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
target_rate);
return ~0;
}
dd->last_rounded_m = min_e_m;
dd->last_rounded_n = min_e_n;
dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
min_e_m, min_e_n);
pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
min_e, min_e_m, min_e_n);
pr_debug("clock: final rate: %ld (target rate: %ld)\n",
dd->last_rounded_rate, target_rate);
return dd->last_rounded_rate;
return target_rate;
}

82
arch/arm/mach-omap2/clkt_iclk.c Normal file
View File

@ -0,0 +1,82 @@
/*
* OMAP2/3 interface clock control
*
* Copyright (C) 2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#undef DEBUG
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <plat/clock.h>
#include <plat/prcm.h>
#include "clock.h"
#include "clock2xxx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
/* Private functions */
/* XXX */
void omap2_clkt_iclk_allow_idle(struct clk *clk)
{
u32 v, r;
r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
v = __raw_readl((__force void __iomem *)r);
v |= (1 << clk->enable_bit);
__raw_writel(v, (__force void __iomem *)r);
}
/* XXX */
void omap2_clkt_iclk_deny_idle(struct clk *clk)
{
u32 v, r;
r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
v = __raw_readl((__force void __iomem *)r);
v &= ~(1 << clk->enable_bit);
__raw_writel(v, (__force void __iomem *)r);
}
/* Public data */
const struct clkops clkops_omap2_iclk_dflt_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_companion = omap2_clk_dflt_find_companion,
.find_idlest = omap2_clk_dflt_find_idlest,
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};
const struct clkops clkops_omap2_iclk_dflt = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};
const struct clkops clkops_omap2_iclk_idle_only = {
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};
const struct clkops clkops_omap2_mdmclk_dflt_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_companion = omap2_clk_dflt_find_companion,
.find_idlest = omap2_clk_dflt_find_idlest,
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};

29
arch/arm/mach-omap2/clock.c
View File

@ -22,7 +22,9 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <trace/events/power.h>
#include <asm/cpu.h>
#include <plat/clock.h>
#include "clockdomain.h"
#include <plat/cpu.h>
@ -261,10 +263,13 @@ void omap2_clk_disable(struct clk *clk)
pr_debug("clock: %s: disabling in hardware\n", clk->name);
if (clk->ops && clk->ops->disable) {
trace_clock_disable(clk->name, 0, smp_processor_id());
clk->ops->disable(clk);
}
if (clk->clkdm)
omap2_clkdm_clk_disable(clk->clkdm, clk);
clkdm_clk_disable(clk->clkdm, clk);
if (clk->parent)
omap2_clk_disable(clk->parent);
@ -304,7 +309,7 @@ int omap2_clk_enable(struct clk *clk)
}
if (clk->clkdm) {
ret = omap2_clkdm_clk_enable(clk->clkdm, clk);
ret = clkdm_clk_enable(clk->clkdm, clk);
if (ret) {
WARN(1, "clock: %s: could not enable clockdomain %s: "
"%d\n", clk->name, clk->clkdm->name, ret);
@ -312,17 +317,21 @@ int omap2_clk_enable(struct clk *clk)
}
}
if (clk->ops && clk->ops->enable) {
trace_clock_enable(clk->name, 1, smp_processor_id());
ret = clk->ops->enable(clk);
if (ret) {
WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
WARN(1, "clock: %s: could not enable: %d\n",
clk->name, ret);
goto oce_err3;
}
}
return 0;
oce_err3:
if (clk->clkdm)
omap2_clkdm_clk_disable(clk->clkdm, clk);
clkdm_clk_disable(clk->clkdm, clk);
oce_err2:
if (clk->parent)
omap2_clk_disable(clk->parent);
@ -349,8 +358,10 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
if (clk->set_rate)
if (clk->set_rate) {
trace_clock_set_rate(clk->name, rate, smp_processor_id());
ret = clk->set_rate(clk, rate);
}
return ret;
}
@ -373,11 +384,17 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
const struct clkops clkops_omap3_noncore_dpll_ops = {
.enable = omap3_noncore_dpll_enable,
.disable = omap3_noncore_dpll_disable,
.allow_idle = omap3_dpll_allow_idle,
.deny_idle = omap3_dpll_deny_idle,
};
const struct clkops clkops_omap3_core_dpll_ops = {
.allow_idle = omap3_dpll_allow_idle,
.deny_idle = omap3_dpll_deny_idle,
};
#endif
/*
* OMAP2+ clock reset and init functions
*/

21
arch/arm/mach-omap2/clock.h
View File

@ -2,7 +2,7 @@
* linux/arch/arm/mach-omap2/clock.h
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2009 Nokia Corporation
* Copyright (C) 2004-2011 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
@ -18,9 +18,6 @@
#include <plat/clock.h>
/* The maximum error between a target DPLL rate and the rounded rate in Hz */
#define DEFAULT_DPLL_RATE_TOLERANCE 50000
/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
#define CORE_CLK_SRC_32K 0x0
#define CORE_CLK_SRC_DPLL 0x1
@ -55,7 +52,6 @@ void omap2_clk_disable(struct clk *clk);
long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
unsigned long omap3_dpll_recalc(struct clk *clk);
unsigned long omap3_clkoutx2_recalc(struct clk *clk);
@ -65,6 +61,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk);
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
int omap3_noncore_dpll_enable(struct clk *clk);
void omap3_noncore_dpll_disable(struct clk *clk);
int omap4_dpllmx_gatectrl_read(struct clk *clk);
void omap4_dpllmx_allow_gatectrl(struct clk *clk);
void omap4_dpllmx_deny_gatectrl(struct clk *clk);
#ifdef CONFIG_OMAP_RESET_CLOCKS
void omap2_clk_disable_unused(struct clk *clk);
@ -83,6 +82,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
/* clkt_iclk.c public functions */
extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
u32 omap2_get_dpll_rate(struct clk *clk);
void omap2_init_dpll_parent(struct clk *clk);
@ -136,6 +139,7 @@ extern struct clk *vclk, *sclk;
extern const struct clksel_rate gpt_32k_rates[];
extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
@ -145,6 +149,13 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
#define omap2_clk_exit_cpufreq_table 0
#endif
extern const struct clkops clkops_omap2_iclk_dflt_wait;
extern const struct clkops clkops_omap2_iclk_dflt;
extern const struct clkops clkops_omap2_iclk_idle_only;
extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
extern const struct clkops clkops_omap2xxx_dpll_ops;
extern const struct clkops clkops_omap3_noncore_dpll_ops;
extern const struct clkops clkops_omap3_core_dpll_ops;
extern const struct clkops clkops_omap4_dpllmx_ops;
#endif

213
arch/arm/mach-omap2/clock2420_data.c
View File

@ -1,8 +1,8 @@
/*
* linux/arch/arm/mach-omap2/clock2420_data.c
* OMAP2420 clock data
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2010 Nokia Corporation
* Copyright (C) 2004-2011 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
@ -34,18 +34,15 @@
/*
* 2420 clock tree.
*
* NOTE:In many cases here we are assigning a 'default' parent. In many
* cases the parent is selectable. The get/set parent calls will also
* switch sources.
*
* Many some clocks say always_enabled, but they can be auto idled for
* power savings. They will always be available upon clock request.
* NOTE:In many cases here we are assigning a 'default' parent. In
* many cases the parent is selectable. The set parent calls will
* also switch sources.
*
* Several sources are given initial rates which may be wrong, this will
* be fixed up in the init func.
*
* Things are broadly separated below by clock domains. It is
* noteworthy that most periferals have dependencies on multiple clock
* noteworthy that most peripherals have dependencies on multiple clock
* domains. Many get their interface clocks from the L4 domain, but get
* functional clocks from fixed sources or other core domain derived
* clocks.
@ -55,7 +52,7 @@
static struct clk func_32k_ck = {
.name = "func_32k_ck",
.ops = &clkops_null,
.rate = 32000,
.rate = 32768,
.clkdm_name = "wkup_clkdm",
};
@ -116,7 +113,6 @@ static struct dpll_data dpll_dd = {
.max_multiplier = 1023,
.min_divider = 1,
.max_divider = 16,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
};
/*
@ -125,7 +121,7 @@ static struct dpll_data dpll_dd = {
*/
static struct clk dpll_ck = {
.name = "dpll_ck",
.ops = &clkops_null,
.ops = &clkops_omap2xxx_dpll_ops,
.parent = &sys_ck, /* Can be func_32k also */
.dpll_data = &dpll_dd,
.clkdm_name = "wkup_clkdm",
@ -455,36 +451,22 @@ static struct clk dsp_fck = {
.recalc = &omap2_clksel_recalc,
};
/* DSP interface clock */
static const struct clksel_rate dsp_irate_ick_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 0 },
};
static const struct clksel dsp_irate_ick_clksel[] = {
{ .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
static const struct clksel dsp_ick_clksel[] = {
{ .parent = &dsp_fck, .rates = dsp_ick_rates },
{ .parent = NULL }
};
/* This clock does not exist as such in the TRM. */
static struct clk dsp_irate_ick = {
.name = "dsp_irate_ick",
.ops = &clkops_null,
.parent = &dsp_fck,
.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
.clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
.clksel = dsp_irate_ick_clksel,
.recalc = &omap2_clksel_recalc,
};
/* 2420 only */
static struct clk dsp_ick = {
.name = "dsp_ick", /* apparently ipi and isp */
.ops = &clkops_omap2_dflt_wait,
.parent = &dsp_irate_ick,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &dsp_fck,
.clkdm_name = "dsp_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
.enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
.clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
.clksel = dsp_ick_clksel,
.recalc = &omap2_clksel_recalc,
};
/*
@ -579,7 +561,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
static struct clk usb_l4_ick = { /* FS-USB interface clock */
.name = "usb_l4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l3_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -661,7 +643,7 @@ static struct clk ssi_ssr_sst_fck = {
*/
static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -716,6 +698,7 @@ static struct clk gfx_2d_fck = {
.recalc = &omap2_clksel_recalc,
};
/* This interface clock does not have a CM_AUTOIDLE bit */
static struct clk gfx_ick = {
.name = "gfx_ick", /* From l3 */
.ops = &clkops_omap2_dflt_wait,
@ -763,7 +746,7 @@ static const struct clksel dss1_fck_clksel[] = {
static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
.name = "dss_ick",
.ops = &clkops_omap2_dflt,
.ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ck, /* really both l3 and l4 */
.clkdm_name = "dss_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -825,6 +808,14 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
.recalc = &followparent_recalc,
};
static struct clk wu_l4_ick = {
.name = "wu_l4_ick",
.ops = &clkops_null,
.parent = &sys_ck,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
/*
* CORE power domain ICLK & FCLK defines.
* Many of the these can have more than one possible parent. Entries
@ -845,9 +836,9 @@ static const struct clksel omap24xx_gpt_clksel[] = {
static struct clk gpt1_ick = {
.name = "gpt1_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.recalc = &followparent_recalc,
@ -871,7 +862,7 @@ static struct clk gpt1_fck = {
static struct clk gpt2_ick = {
.name = "gpt2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -895,7 +886,7 @@ static struct clk gpt2_fck = {
static struct clk gpt3_ick = {
.name = "gpt3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -919,7 +910,7 @@ static struct clk gpt3_fck = {
static struct clk gpt4_ick = {
.name = "gpt4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -943,7 +934,7 @@ static struct clk gpt4_fck = {
static struct clk gpt5_ick = {
.name = "gpt5_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -967,7 +958,7 @@ static struct clk gpt5_fck = {
static struct clk gpt6_ick = {
.name = "gpt6_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -991,8 +982,9 @@ static struct clk gpt6_fck = {
static struct clk gpt7_ick = {
.name = "gpt7_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
.recalc = &followparent_recalc,
@ -1014,7 +1006,7 @@ static struct clk gpt7_fck = {
static struct clk gpt8_ick = {
.name = "gpt8_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1038,7 +1030,7 @@ static struct clk gpt8_fck = {
static struct clk gpt9_ick = {
.name = "gpt9_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1062,7 +1054,7 @@ static struct clk gpt9_fck = {
static struct clk gpt10_ick = {
.name = "gpt10_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1086,7 +1078,7 @@ static struct clk gpt10_fck = {
static struct clk gpt11_ick = {
.name = "gpt11_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1110,7 +1102,7 @@ static struct clk gpt11_fck = {
static struct clk gpt12_ick = {
.name = "gpt12_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1134,7 +1126,7 @@ static struct clk gpt12_fck = {
static struct clk mcbsp1_ick = {
.name = "mcbsp1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1174,7 +1166,7 @@ static struct clk mcbsp1_fck = {
static struct clk mcbsp2_ick = {
.name = "mcbsp2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1198,7 +1190,7 @@ static struct clk mcbsp2_fck = {
static struct clk mcspi1_ick = {
.name = "mcspi1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1218,7 +1210,7 @@ static struct clk mcspi1_fck = {
static struct clk mcspi2_ick = {
.name = "mcspi2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1238,7 +1230,7 @@ static struct clk mcspi2_fck = {
static struct clk uart1_ick = {
.name = "uart1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1258,7 +1250,7 @@ static struct clk uart1_fck = {
static struct clk uart2_ick = {
.name = "uart2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1278,7 +1270,7 @@ static struct clk uart2_fck = {
static struct clk uart3_ick = {
.name = "uart3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1298,9 +1290,9 @@ static struct clk uart3_fck = {
static struct clk gpios_ick = {
.name = "gpios_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &followparent_recalc,
@ -1318,9 +1310,9 @@ static struct clk gpios_fck = {
static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
@ -1338,10 +1330,10 @@ static struct clk mpu_wdt_fck = {
static struct clk sync_32k_ick = {
.name = "sync_32k_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
.recalc = &followparent_recalc,
@ -1349,9 +1341,9 @@ static struct clk sync_32k_ick = {
static struct clk wdt1_ick = {
.name = "wdt1_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_WDT1_SHIFT,
.recalc = &followparent_recalc,
@ -1359,10 +1351,10 @@ static struct clk wdt1_ick = {
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
.recalc = &followparent_recalc,
@ -1370,7 +1362,7 @@ static struct clk omapctrl_ick = {
static struct clk cam_ick = {
.name = "cam_ick",
.ops = &clkops_omap2_dflt,
.ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1395,7 +1387,7 @@ static struct clk cam_fck = {
static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1405,7 +1397,7 @@ static struct clk mailboxes_ick = {
static struct clk wdt4_ick = {
.name = "wdt4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1425,7 +1417,7 @@ static struct clk wdt4_fck = {
static struct clk wdt3_ick = {
.name = "wdt3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1445,7 +1437,7 @@ static struct clk wdt3_fck = {
static struct clk mspro_ick = {
.name = "mspro_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1465,7 +1457,7 @@ static struct clk mspro_fck = {
static struct clk mmc_ick = {
.name = "mmc_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1485,7 +1477,7 @@ static struct clk mmc_fck = {
static struct clk fac_ick = {
.name = "fac_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1505,7 +1497,7 @@ static struct clk fac_fck = {
static struct clk eac_ick = {
.name = "eac_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1525,7 +1517,7 @@ static struct clk eac_fck = {
static struct clk hdq_ick = {
.name = "hdq_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1545,7 +1537,7 @@ static struct clk hdq_fck = {
static struct clk i2c2_ick = {
.name = "i2c2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1565,7 +1557,7 @@ static struct clk i2c2_fck = {
static struct clk i2c1_ick = {
.name = "i2c1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1583,12 +1575,18 @@ static struct clk i2c1_fck = {
.recalc = &followparent_recalc,
};
/*
* The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
* accesses derived from this data.
*/
static struct clk gpmc_fck = {
.name = "gpmc_fck",
.ops = &clkops_null, /* RMK: missing? */
.ops = &clkops_omap2_iclk_idle_only,
.parent = &core_l3_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
.recalc = &followparent_recalc,
};
@ -1600,17 +1598,38 @@ static struct clk sdma_fck = {
.recalc = &followparent_recalc,
};
/*
* The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
* accesses derived from this data.
*/
static struct clk sdma_ick = {
.name = "sdma_ick",
.ops = &clkops_null, /* RMK: missing? */
.parent = &l4_ck,
.ops = &clkops_omap2_iclk_idle_only,
.parent = &core_l3_ck,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
.recalc = &followparent_recalc,
};
/*
* The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
* accesses derived from this data.
*/
static struct clk sdrc_ick = {
.name = "sdrc_ick",
.ops = &clkops_omap2_iclk_idle_only,
.parent = &core_l3_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
.recalc = &followparent_recalc,
};
static struct clk vlynq_ick = {
.name = "vlynq_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l3_ck,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1659,7 +1678,7 @@ static struct clk vlynq_fck = {
static struct clk des_ick = {
.name = "des_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@ -1669,7 +1688,7 @@ static struct clk des_ick = {
static struct clk sha_ick = {
.name = "sha_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@ -1679,7 +1698,7 @@ static struct clk sha_ick = {
static struct clk rng_ick = {
.name = "rng_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@ -1689,7 +1708,7 @@ static struct clk rng_ick = {
static struct clk aes_ick = {
.name = "aes_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@ -1699,7 +1718,7 @@ static struct clk aes_ick = {
static struct clk pka_ick = {
.name = "pka_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@ -1777,7 +1796,6 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
/* dsp domain clocks */
CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X),
CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
@ -1797,6 +1815,7 @@ static struct omap_clk omap2420_clks[] = {
/* L4 domain clocks */
CLK(NULL, "l4_ck", &l4_ck, CK_242X),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
/* virtual meta-group clock */
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
/* general l4 interface ck, multi-parent functional clk */
@ -1869,6 +1888,7 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
CLK(NULL, "des_ick", &des_ick, CK_242X),
@ -1913,6 +1933,9 @@ int __init omap2420_clk_init(void)
omap2_init_clk_clkdm(c->lk.clk);
}
/* Disable autoidle on all clocks; let the PM code enable it later */
omap_clk_disable_autoidle_all();
/* Check the MPU rate set by bootloader */
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
for (prcm = rate_table; prcm->mpu_speed; prcm++) {

236
arch/arm/mach-omap2/clock2430_data.c
View File

@ -1,8 +1,8 @@
/*
* linux/arch/arm/mach-omap2/clock2430_data.c
* OMAP2430 clock data
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2010 Nokia Corporation
* Copyright (C) 2004-2011 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
@ -34,18 +34,15 @@
/*
* 2430 clock tree.
*
* NOTE:In many cases here we are assigning a 'default' parent. In many
* cases the parent is selectable. The get/set parent calls will also
* switch sources.
*
* Many some clocks say always_enabled, but they can be auto idled for
* power savings. They will always be available upon clock request.
* NOTE:In many cases here we are assigning a 'default' parent. In
* many cases the parent is selectable. The set parent calls will
* also switch sources.
*
* Several sources are given initial rates which may be wrong, this will
* be fixed up in the init func.
*
* Things are broadly separated below by clock domains. It is
* noteworthy that most periferals have dependencies on multiple clock
* noteworthy that most peripherals have dependencies on multiple clock
* domains. Many get their interface clocks from the L4 domain, but get
* functional clocks from fixed sources or other core domain derived
* clocks.
@ -55,7 +52,7 @@
static struct clk func_32k_ck = {
.name = "func_32k_ck",
.ops = &clkops_null,
.rate = 32000,
.rate = 32768,
.clkdm_name = "wkup_clkdm",
};
@ -116,7 +113,6 @@ static struct dpll_data dpll_dd = {
.max_multiplier = 1023,
.min_divider = 1,
.max_divider = 16,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
};
/*
@ -125,7 +121,7 @@ static struct dpll_data dpll_dd = {
*/
static struct clk dpll_ck = {
.name = "dpll_ck",
.ops = &clkops_null,
.ops = &clkops_omap2xxx_dpll_ops,
.parent = &sys_ck, /* Can be func_32k also */
.dpll_data = &dpll_dd,
.clkdm_name = "wkup_clkdm",
@ -434,37 +430,23 @@ static struct clk dsp_fck = {
.recalc = &omap2_clksel_recalc,
};
/* DSP interface clock */
static const struct clksel_rate dsp_irate_ick_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 3, .val = 3, .flags = RATE_IN_243X },
{ .div = 0 },
};
static const struct clksel dsp_irate_ick_clksel[] = {
{ .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
static const struct clksel dsp_ick_clksel[] = {
{ .parent = &dsp_fck, .rates = dsp_ick_rates },
{ .parent = NULL }
};
/* This clock does not exist as such in the TRM. */
static struct clk dsp_irate_ick = {
.name = "dsp_irate_ick",
.ops = &clkops_null,
.parent = &dsp_fck,
.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
.clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
.clksel = dsp_irate_ick_clksel,
.recalc = &omap2_clksel_recalc,
};
/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
static struct clk iva2_1_ick = {
.name = "iva2_1_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &dsp_irate_ick,
.parent = &dsp_fck,
.clkdm_name = "dsp_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
.clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
.clksel = dsp_ick_clksel,
.recalc = &omap2_clksel_recalc,
};
/*
@ -525,7 +507,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
static struct clk usb_l4_ick = { /* FS-USB interface clock */
.name = "usb_l4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l3_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -606,7 +588,7 @@ static struct clk ssi_ssr_sst_fck = {
*/
static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -661,6 +643,7 @@ static struct clk gfx_2d_fck = {
.recalc = &omap2_clksel_recalc,
};
/* This interface clock does not have a CM_AUTOIDLE bit */
static struct clk gfx_ick = {
.name = "gfx_ick", /* From l3 */
.ops = &clkops_omap2_dflt_wait,
@ -693,7 +676,7 @@ static const struct clksel mdm_ick_clksel[] = {
static struct clk mdm_ick = { /* used both as a ick and fck */
.name = "mdm_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_ck,
.clkdm_name = "mdm_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
@ -706,7 +689,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
static struct clk mdm_osc_ck = {
.name = "mdm_osc_ck",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_mdmclk_dflt_wait,
.parent = &osc_ck,
.clkdm_name = "mdm_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
@ -751,7 +734,7 @@ static const struct clksel dss1_fck_clksel[] = {
static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
.name = "dss_ick",
.ops = &clkops_omap2_dflt,
.ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ck, /* really both l3 and l4 */
.clkdm_name = "dss_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -813,6 +796,14 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
.recalc = &followparent_recalc,
};
static struct clk wu_l4_ick = {
.name = "wu_l4_ick",
.ops = &clkops_null,
.parent = &sys_ck,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
/*
* CORE power domain ICLK & FCLK defines.
* Many of the these can have more than one possible parent. Entries
@ -833,9 +824,9 @@ static const struct clksel omap24xx_gpt_clksel[] = {
static struct clk gpt1_ick = {
.name = "gpt1_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.recalc = &followparent_recalc,
@ -859,7 +850,7 @@ static struct clk gpt1_fck = {
static struct clk gpt2_ick = {
.name = "gpt2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -883,7 +874,7 @@ static struct clk gpt2_fck = {
static struct clk gpt3_ick = {
.name = "gpt3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -907,7 +898,7 @@ static struct clk gpt3_fck = {
static struct clk gpt4_ick = {
.name = "gpt4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -931,7 +922,7 @@ static struct clk gpt4_fck = {
static struct clk gpt5_ick = {
.name = "gpt5_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -955,7 +946,7 @@ static struct clk gpt5_fck = {
static struct clk gpt6_ick = {
.name = "gpt6_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -979,8 +970,9 @@ static struct clk gpt6_fck = {
static struct clk gpt7_ick = {
.name = "gpt7_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
.recalc = &followparent_recalc,
@ -1002,7 +994,7 @@ static struct clk gpt7_fck = {
static struct clk gpt8_ick = {
.name = "gpt8_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1026,7 +1018,7 @@ static struct clk gpt8_fck = {
static struct clk gpt9_ick = {
.name = "gpt9_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1050,7 +1042,7 @@ static struct clk gpt9_fck = {
static struct clk gpt10_ick = {
.name = "gpt10_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1074,7 +1066,7 @@ static struct clk gpt10_fck = {
static struct clk gpt11_ick = {
.name = "gpt11_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1098,7 +1090,7 @@ static struct clk gpt11_fck = {
static struct clk gpt12_ick = {
.name = "gpt12_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1122,7 +1114,7 @@ static struct clk gpt12_fck = {
static struct clk mcbsp1_ick = {
.name = "mcbsp1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1162,7 +1154,7 @@ static struct clk mcbsp1_fck = {
static struct clk mcbsp2_ick = {
.name = "mcbsp2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1186,7 +1178,7 @@ static struct clk mcbsp2_fck = {
static struct clk mcbsp3_ick = {
.name = "mcbsp3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1210,7 +1202,7 @@ static struct clk mcbsp3_fck = {
static struct clk mcbsp4_ick = {
.name = "mcbsp4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1234,7 +1226,7 @@ static struct clk mcbsp4_fck = {
static struct clk mcbsp5_ick = {
.name = "mcbsp5_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1258,7 +1250,7 @@ static struct clk mcbsp5_fck = {
static struct clk mcspi1_ick = {
.name = "mcspi1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1278,7 +1270,7 @@ static struct clk mcspi1_fck = {
static struct clk mcspi2_ick = {
.name = "mcspi2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1298,7 +1290,7 @@ static struct clk mcspi2_fck = {
static struct clk mcspi3_ick = {
.name = "mcspi3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1318,7 +1310,7 @@ static struct clk mcspi3_fck = {
static struct clk uart1_ick = {
.name = "uart1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1338,7 +1330,7 @@ static struct clk uart1_fck = {
static struct clk uart2_ick = {
.name = "uart2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1358,7 +1350,7 @@ static struct clk uart2_fck = {
static struct clk uart3_ick = {
.name = "uart3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1378,9 +1370,9 @@ static struct clk uart3_fck = {
static struct clk gpios_ick = {
.name = "gpios_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &followparent_recalc,
@ -1398,9 +1390,9 @@ static struct clk gpios_fck = {
static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
@ -1418,10 +1410,10 @@ static struct clk mpu_wdt_fck = {
static struct clk sync_32k_ick = {
.name = "sync_32k_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.ops = &clkops_omap2_iclk_dflt_wait,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
.recalc = &followparent_recalc,
@ -1429,9 +1421,9 @@ static struct clk sync_32k_ick = {
static struct clk wdt1_ick = {
.name = "wdt1_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_WDT1_SHIFT,
.recalc = &followparent_recalc,
@ -1439,10 +1431,10 @@ static struct clk wdt1_ick = {
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.ops = &clkops_omap2_iclk_dflt_wait,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
.recalc = &followparent_recalc,
@ -1450,9 +1442,9 @@ static struct clk omapctrl_ick = {
static struct clk icr_ick = {
.name = "icr_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wu_l4_ick,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP2430_EN_ICR_SHIFT,
.recalc = &followparent_recalc,
@ -1460,7 +1452,7 @@ static struct clk icr_ick = {
static struct clk cam_ick = {
.name = "cam_ick",
.ops = &clkops_omap2_dflt,
.ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1485,7 +1477,7 @@ static struct clk cam_fck = {
static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1495,7 +1487,7 @@ static struct clk mailboxes_ick = {
static struct clk wdt4_ick = {
.name = "wdt4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1515,7 +1507,7 @@ static struct clk wdt4_fck = {
static struct clk mspro_ick = {
.name = "mspro_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1535,7 +1527,7 @@ static struct clk mspro_fck = {
static struct clk fac_ick = {
.name = "fac_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1555,7 +1547,7 @@ static struct clk fac_fck = {
static struct clk hdq_ick = {
.name = "hdq_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1579,7 +1571,7 @@ static struct clk hdq_fck = {
*/
static struct clk i2c2_ick = {
.name = "i2c2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1603,7 +1595,7 @@ static struct clk i2chs2_fck = {
*/
static struct clk i2c1_ick = {
.name = "i2c1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -1621,12 +1613,18 @@ static struct clk i2chs1_fck = {
.recalc = &followparent_recalc,
};
/*
* The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
* accesses derived from this data.
*/
static struct clk gpmc_fck = {
.name = "gpmc_fck",
.ops = &clkops_null, /* RMK: missing? */
.ops = &clkops_omap2_iclk_idle_only,
.parent = &core_l3_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
.recalc = &followparent_recalc,
};
@ -1638,20 +1636,26 @@ static struct clk sdma_fck = {
.recalc = &followparent_recalc,
};
/*
* The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
* accesses derived from this data.
*/
static struct clk sdma_ick = {
.name = "sdma_ick",
.ops = &clkops_null, /* RMK: missing? */
.parent = &l4_ck,
.ops = &clkops_omap2_iclk_idle_only,
.parent = &core_l3_ck,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
.recalc = &followparent_recalc,
};
static struct clk sdrc_ick = {
.name = "sdrc_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.ops = &clkops_omap2_iclk_idle_only,
.parent = &core_l3_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP2430_EN_SDRC_SHIFT,
.recalc = &followparent_recalc,
@ -1659,7 +1663,7 @@ static struct clk sdrc_ick = {
static struct clk des_ick = {
.name = "des_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@ -1669,7 +1673,7 @@ static struct clk des_ick = {
static struct clk sha_ick = {
.name = "sha_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@ -1679,7 +1683,7 @@ static struct clk sha_ick = {
static struct clk rng_ick = {
.name = "rng_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@ -1689,7 +1693,7 @@ static struct clk rng_ick = {
static struct clk aes_ick = {
.name = "aes_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@ -1699,7 +1703,7 @@ static struct clk aes_ick = {
static struct clk pka_ick = {
.name = "pka_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@ -1719,7 +1723,7 @@ static struct clk usb_fck = {
static struct clk usbhs_ick = {
.name = "usbhs_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l3_ck,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1729,7 +1733,7 @@ static struct clk usbhs_ick = {
static struct clk mmchs1_ick = {
.name = "mmchs1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1741,7 +1745,7 @@ static struct clk mmchs1_fck = {
.name = "mmchs1_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &func_96m_ck,
.clkdm_name = "core_l3_clkdm",
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
.recalc = &followparent_recalc,
@ -1749,7 +1753,7 @@ static struct clk mmchs1_fck = {
static struct clk mmchs2_ick = {
.name = "mmchs2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1761,6 +1765,7 @@ static struct clk mmchs2_fck = {
.name = "mmchs2_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
.recalc = &followparent_recalc,
@ -1768,7 +1773,7 @@ static struct clk mmchs2_fck = {
static struct clk gpio5_ick = {
.name = "gpio5_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1788,7 +1793,7 @@ static struct clk gpio5_fck = {
static struct clk mdm_intc_ick = {
.name = "mdm_intc_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@ -1880,7 +1885,6 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
/* dsp domain clocks */
CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X),
CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
/* GFX domain clocks */
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
@ -1901,6 +1905,7 @@ static struct omap_clk omap2430_clks[] = {
/* L4 domain clocks */
CLK(NULL, "l4_ck", &l4_ck, CK_243X),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
/* virtual meta-group clock */
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
/* general l4 interface ck, multi-parent functional clk */
@ -1984,15 +1989,15 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "pka_ick", &pka_ick, CK_243X),
CLK(NULL, "usb_fck", &usb_fck, CK_243X),
CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X),
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
};
/*
@ -2028,6 +2033,9 @@ int __init omap2430_clk_init(void)
omap2_init_clk_clkdm(c->lk.clk);
}
/* Disable autoidle on all clocks; let the PM code enable it later */
omap_clk_disable_autoidle_all();
/* Check the MPU rate set by bootloader */
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
for (prcm = rate_table; prcm->mpu_speed; prcm++) {

8
arch/arm/mach-omap2/clock2xxx.h
View File

@ -20,16 +20,16 @@ u32 omap2xxx_get_apll_clkin(void);
u32 omap2xxx_get_sysclkdiv(void);
void omap2xxx_clk_prepare_for_reboot(void);
#ifdef CONFIG_ARCH_OMAP2420
#ifdef CONFIG_SOC_OMAP2420
int omap2420_clk_init(void);
#else
#define omap2420_clk_init() 0
#define omap2420_clk_init() do { } while(0)
#endif
#ifdef CONFIG_ARCH_OMAP2430
#ifdef CONFIG_SOC_OMAP2430
int omap2430_clk_init(void);
#else
#define omap2430_clk_init() 0
#define omap2430_clk_init() do { } while(0)
#endif
extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll;

29
arch/arm/mach-omap2/clock34xx.c
View File

@ -2,7 +2,7 @@
* OMAP3-specific clock framework functions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2010 Nokia Corporation
* Copyright (C) 2007-2011 Nokia Corporation
*
* Paul Walmsley
* Jouni Högander
@ -59,6 +59,15 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
.find_companion = omap2_clk_dflt_find_companion,
};
const struct clkops clkops_omap3430es2_iclk_ssi_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap3430es2_clk_ssi_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};
/**
* omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
* @clk: struct clk * being enabled
@ -94,6 +103,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
.find_companion = omap2_clk_dflt_find_companion,
};
const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};
/**
* omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
* @clk: struct clk * being enabled
@ -124,3 +142,12 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};

5
arch/arm/mach-omap2/clock34xx.h
View File

@ -2,14 +2,17 @@
* OMAP34xx clock function prototypes and macros
*
* Copyright (C) 2007-2010 Texas Instruments, Inc.
* Copyright (C) 2007-2010 Nokia Corporation
* Copyright (C) 2007-2011 Nokia Corporation
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
extern const struct clkops clkops_omap3430es2_ssi_wait;
extern const struct clkops clkops_omap3430es2_iclk_ssi_wait;
extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
extern const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
extern const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait;
#endif

4
arch/arm/mach-omap2/clock3517.c
View File

@ -2,7 +2,7 @@
* OMAP3517/3505-specific clock framework functions
*
* Copyright (C) 2010 Texas Instruments, Inc.
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2011 Nokia Corporation
*
* Ranjith Lohithakshan
* Paul Walmsley
@ -119,6 +119,8 @@ const struct clkops clkops_am35xx_ipss_wait = {
.disable = omap2_dflt_clk_disable,
.find_idlest = am35xx_clk_ipss_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};

3
arch/arm/mach-omap2/clock3xxx.c
View File

@ -65,9 +65,6 @@ void __init omap3_clk_lock_dpll5(void)
clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
clk_enable(dpll5_clk);
/* Enable autoidle to allow it to enter low power bypass */
omap3_dpll_allow_idle(dpll5_clk);
/* Program dpll5_m2_clk divider for no division */
dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
clk_enable(dpll5_m2_clk);

182
arch/arm/mach-omap2/clock3xxx_data.c
View File

@ -2,7 +2,7 @@
* OMAP3 clock data
*
* Copyright (C) 2007-2010 Texas Instruments, Inc.
* Copyright (C) 2007-2010 Nokia Corporation
* Copyright (C) 2007-2011 Nokia Corporation
*
* Written by Paul Walmsley
* With many device clock fixes by Kevin Hilman and Jouni Högander
@ -291,12 +291,11 @@ static struct dpll_data dpll1_dd = {
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
};
static struct clk dpll1_ck = {
.name = "dpll1_ck",
.ops = &clkops_null,
.ops = &clkops_omap3_noncore_dpll_ops,
.parent = &sys_ck,
.dpll_data = &dpll1_dd,
.round_rate = &omap2_dpll_round_rate,
@ -364,7 +363,6 @@ static struct dpll_data dpll2_dd = {
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
};
static struct clk dpll2_ck = {
@ -424,12 +422,11 @@ static struct dpll_data dpll3_dd = {
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
};
static struct clk dpll3_ck = {
.name = "dpll3_ck",
.ops = &clkops_null,
.ops = &clkops_omap3_core_dpll_ops,
.parent = &sys_ck,
.dpll_data = &dpll3_dd,
.round_rate = &omap2_dpll_round_rate,
@ -583,7 +580,6 @@ static struct dpll_data dpll4_dd_34xx __initdata = {
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
};
static struct dpll_data dpll4_dd_3630 __initdata = {
@ -607,7 +603,6 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
.max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
.flags = DPLL_J_TYPE
};
@ -939,7 +934,6 @@ static struct dpll_data dpll5_dd = {
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
};
static struct clk dpll5_ck = {
@ -1205,7 +1199,10 @@ static const struct clksel gfx_l3_clksel[] = {
{ .parent = NULL }
};
/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
/*
* Virtual parent clock for gfx_l3_ick and gfx_l3_fck
* This interface clock does not have a CM_AUTOIDLE bit
*/
static struct clk gfx_l3_ck = {
.name = "gfx_l3_ck",
.ops = &clkops_omap2_dflt_wait,
@ -1304,6 +1301,7 @@ static struct clk sgx_fck = {
.round_rate = &omap2_clksel_round_rate
};
/* This interface clock does not have a CM_AUTOIDLE bit */
static struct clk sgx_ick = {
.name = "sgx_ick",
.ops = &clkops_omap2_dflt_wait,
@ -1328,7 +1326,7 @@ static struct clk d2d_26m_fck = {
static struct clk modem_fck = {
.name = "modem_fck",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_mdmclk_dflt_wait,
.parent = &sys_ck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MODEM_SHIFT,
@ -1338,7 +1336,7 @@ static struct clk modem_fck = {
static struct clk sad2d_ick = {
.name = "sad2d_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SAD2D_SHIFT,
@ -1348,7 +1346,7 @@ static struct clk sad2d_ick = {
static struct clk mad2d_ick = {
.name = "mad2d_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430_EN_MAD2D_SHIFT,
@ -1718,7 +1716,7 @@ static struct clk core_l3_ick = {
static struct clk hsotgusb_ick_3430es1 = {
.name = "hsotgusb_ick",
.ops = &clkops_omap2_dflt,
.ops = &clkops_omap2_iclk_dflt,
.parent = &core_l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@ -1728,7 +1726,7 @@ static struct clk hsotgusb_ick_3430es1 = {
static struct clk hsotgusb_ick_3430es2 = {
.name = "hsotgusb_ick",
.ops = &clkops_omap3430es2_hsotgusb_wait,
.ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
.parent = &core_l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@ -1736,6 +1734,7 @@ static struct clk hsotgusb_ick_3430es2 = {
.recalc = &followparent_recalc,
};
/* This interface clock does not have a CM_AUTOIDLE bit */
static struct clk sdrc_ick = {
.name = "sdrc_ick",
.ops = &clkops_omap2_dflt_wait,
@ -1767,7 +1766,7 @@ static struct clk security_l3_ick = {
static struct clk pka_ick = {
.name = "pka_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &security_l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_PKA_SHIFT,
@ -1786,7 +1785,7 @@ static struct clk core_l4_ick = {
static struct clk usbtll_ick = {
.name = "usbtll_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
@ -1796,7 +1795,7 @@ static struct clk usbtll_ick = {
static struct clk mmchs3_ick = {
.name = "mmchs3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@ -1807,7 +1806,7 @@ static struct clk mmchs3_ick = {
/* Intersystem Communication Registers - chassis mode only */
static struct clk icr_ick = {
.name = "icr_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_ICR_SHIFT,
@ -1817,7 +1816,7 @@ static struct clk icr_ick = {
static struct clk aes2_ick = {
.name = "aes2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_AES2_SHIFT,
@ -1827,7 +1826,7 @@ static struct clk aes2_ick = {
static struct clk sha12_ick = {
.name = "sha12_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SHA12_SHIFT,
@ -1837,7 +1836,7 @@ static struct clk sha12_ick = {
static struct clk des2_ick = {
.name = "des2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_DES2_SHIFT,
@ -1847,7 +1846,7 @@ static struct clk des2_ick = {
static struct clk mmchs2_ick = {
.name = "mmchs2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
@ -1857,7 +1856,7 @@ static struct clk mmchs2_ick = {
static struct clk mmchs1_ick = {
.name = "mmchs1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
@ -1867,7 +1866,7 @@ static struct clk mmchs1_ick = {
static struct clk mspro_ick = {
.name = "mspro_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
@ -1877,7 +1876,7 @@ static struct clk mspro_ick = {
static struct clk hdq_ick = {
.name = "hdq_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
@ -1887,7 +1886,7 @@ static struct clk hdq_ick = {
static struct clk mcspi4_ick = {
.name = "mcspi4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
@ -1897,7 +1896,7 @@ static struct clk mcspi4_ick = {
static struct clk mcspi3_ick = {
.name = "mcspi3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
@ -1907,7 +1906,7 @@ static struct clk mcspi3_ick = {
static struct clk mcspi2_ick = {
.name = "mcspi2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
@ -1917,7 +1916,7 @@ static struct clk mcspi2_ick = {
static struct clk mcspi1_ick = {
.name = "mcspi1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
@ -1927,7 +1926,7 @@ static struct clk mcspi1_ick = {
static struct clk i2c3_ick = {
.name = "i2c3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
@ -1937,7 +1936,7 @@ static struct clk i2c3_ick = {
static struct clk i2c2_ick = {
.name = "i2c2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
@ -1947,7 +1946,7 @@ static struct clk i2c2_ick = {
static struct clk i2c1_ick = {
.name = "i2c1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
@ -1957,7 +1956,7 @@ static struct clk i2c1_ick = {
static struct clk uart2_ick = {
.name = "uart2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
@ -1967,7 +1966,7 @@ static struct clk uart2_ick = {
static struct clk uart1_ick = {
.name = "uart1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
@ -1977,7 +1976,7 @@ static struct clk uart1_ick = {
static struct clk gpt11_ick = {
.name = "gpt11_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
@ -1987,7 +1986,7 @@ static struct clk gpt11_ick = {
static struct clk gpt10_ick = {
.name = "gpt10_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
@ -1997,7 +1996,7 @@ static struct clk gpt10_ick = {
static struct clk mcbsp5_ick = {
.name = "mcbsp5_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@ -2007,7 +2006,7 @@ static struct clk mcbsp5_ick = {
static struct clk mcbsp1_ick = {
.name = "mcbsp1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@ -2017,7 +2016,7 @@ static struct clk mcbsp1_ick = {
static struct clk fac_ick = {
.name = "fac_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
@ -2027,7 +2026,7 @@ static struct clk fac_ick = {
static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
@ -2037,7 +2036,7 @@ static struct clk mailboxes_ick = {
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
@ -2057,7 +2056,7 @@ static struct clk ssi_l4_ick = {
static struct clk ssi_ick_3430es1 = {
.name = "ssi_ick",
.ops = &clkops_omap2_dflt,
.ops = &clkops_omap2_iclk_dflt,
.parent = &ssi_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
@ -2067,7 +2066,7 @@ static struct clk ssi_ick_3430es1 = {
static struct clk ssi_ick_3430es2 = {
.name = "ssi_ick",
.ops = &clkops_omap3430es2_ssi_wait,
.ops = &clkops_omap3430es2_iclk_ssi_wait,
.parent = &ssi_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
@ -2085,7 +2084,7 @@ static const struct clksel usb_l4_clksel[] = {
static struct clk usb_l4_ick = {
.name = "usb_l4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ick,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@ -2107,7 +2106,7 @@ static struct clk security_l4_ick2 = {
static struct clk aes1_ick = {
.name = "aes1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &security_l4_ick2,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_AES1_SHIFT,
@ -2116,7 +2115,7 @@ static struct clk aes1_ick = {
static struct clk rng_ick = {
.name = "rng_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &security_l4_ick2,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_RNG_SHIFT,
@ -2125,7 +2124,7 @@ static struct clk rng_ick = {
static struct clk sha11_ick = {
.name = "sha11_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &security_l4_ick2,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_SHA11_SHIFT,
@ -2134,7 +2133,7 @@ static struct clk sha11_ick = {
static struct clk des1_ick = {
.name = "des1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &security_l4_ick2,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_DES1_SHIFT,
@ -2195,7 +2194,7 @@ static struct clk dss2_alwon_fck = {
static struct clk dss_ick_3430es1 = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
.ops = &clkops_omap2_dflt,
.ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@ -2206,7 +2205,7 @@ static struct clk dss_ick_3430es1 = {
static struct clk dss_ick_3430es2 = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
.parent = &l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@ -2229,7 +2228,7 @@ static struct clk cam_mclk = {
static struct clk cam_ick = {
/* Handles both L3 and L4 clocks */
.name = "cam_ick",
.ops = &clkops_omap2_dflt,
.ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
@ -2272,7 +2271,7 @@ static struct clk usbhost_48m_fck = {
static struct clk usbhost_ick = {
/* Handles both L3 and L4 clocks */
.name = "usbhost_ick",
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
.parent = &l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
@ -2372,7 +2371,7 @@ static struct clk wkup_l4_ick = {
/* Never specifically named in the TRM, so we have to infer a likely name */
static struct clk usim_ick = {
.name = "usim_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
@ -2382,7 +2381,7 @@ static struct clk usim_ick = {
static struct clk wdt2_ick = {
.name = "wdt2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
@ -2392,7 +2391,7 @@ static struct clk wdt2_ick = {
static struct clk wdt1_ick = {
.name = "wdt1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
@ -2402,7 +2401,7 @@ static struct clk wdt1_ick = {
static struct clk gpio1_ick = {
.name = "gpio1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
@ -2412,7 +2411,7 @@ static struct clk gpio1_ick = {
static struct clk omap_32ksync_ick = {
.name = "omap_32ksync_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
@ -2423,7 +2422,7 @@ static struct clk omap_32ksync_ick = {
/* XXX This clock no longer exists in 3430 TRM rev F */
static struct clk gpt12_ick = {
.name = "gpt12_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
@ -2433,7 +2432,7 @@ static struct clk gpt12_ick = {
static struct clk gpt1_ick = {
.name = "gpt1_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
@ -2663,7 +2662,7 @@ static struct clk per_l4_ick = {
static struct clk gpio6_ick = {
.name = "gpio6_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
@ -2673,7 +2672,7 @@ static struct clk gpio6_ick = {
static struct clk gpio5_ick = {
.name = "gpio5_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
@ -2683,7 +2682,7 @@ static struct clk gpio5_ick = {
static struct clk gpio4_ick = {
.name = "gpio4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
@ -2693,7 +2692,7 @@ static struct clk gpio4_ick = {
static struct clk gpio3_ick = {
.name = "gpio3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
@ -2703,7 +2702,7 @@ static struct clk gpio3_ick = {
static struct clk gpio2_ick = {
.name = "gpio2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
@ -2713,7 +2712,7 @@ static struct clk gpio2_ick = {
static struct clk wdt3_ick = {
.name = "wdt3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
@ -2723,7 +2722,7 @@ static struct clk wdt3_ick = {
static struct clk uart3_ick = {
.name = "uart3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
@ -2733,7 +2732,7 @@ static struct clk uart3_ick = {
static struct clk uart4_ick = {
.name = "uart4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3630_EN_UART4_SHIFT,
@ -2743,7 +2742,7 @@ static struct clk uart4_ick = {
static struct clk gpt9_ick = {
.name = "gpt9_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
@ -2753,7 +2752,7 @@ static struct clk gpt9_ick = {
static struct clk gpt8_ick = {
.name = "gpt8_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
@ -2763,7 +2762,7 @@ static struct clk gpt8_ick = {
static struct clk gpt7_ick = {
.name = "gpt7_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
@ -2773,7 +2772,7 @@ static struct clk gpt7_ick = {
static struct clk gpt6_ick = {
.name = "gpt6_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
@ -2783,7 +2782,7 @@ static struct clk gpt6_ick = {
static struct clk gpt5_ick = {
.name = "gpt5_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
@ -2793,7 +2792,7 @@ static struct clk gpt5_ick = {
static struct clk gpt4_ick = {
.name = "gpt4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
@ -2803,7 +2802,7 @@ static struct clk gpt4_ick = {
static struct clk gpt3_ick = {
.name = "gpt3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
@ -2813,7 +2812,7 @@ static struct clk gpt3_ick = {
static struct clk gpt2_ick = {
.name = "gpt2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
@ -2823,7 +2822,7 @@ static struct clk gpt2_ick = {
static struct clk mcbsp2_ick = {
.name = "mcbsp2_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@ -2833,7 +2832,7 @@ static struct clk mcbsp2_ick = {
static struct clk mcbsp3_ick = {
.name = "mcbsp3_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@ -2843,7 +2842,7 @@ static struct clk mcbsp3_ick = {
static struct clk mcbsp4_ick = {
.name = "mcbsp4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
@ -3186,7 +3185,7 @@ static struct clk vpfe_fck = {
*/
static struct clk uart4_ick_am35xx = {
.name = "uart4_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = AM35XX_EN_UART4_SHIFT,
@ -3290,10 +3289,10 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX),
CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX),
CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
@ -3323,13 +3322,13 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
@ -3480,6 +3479,9 @@ int __init omap3xxx_clk_init(void)
} else if (cpu_is_omap3630()) {
cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
cpu_clkflg = CK_36XX;
} else if (cpu_is_ti816x()) {
cpu_mask = RATE_IN_TI816X;
cpu_clkflg = CK_TI816X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
@ -3544,6 +3546,9 @@ int __init omap3xxx_clk_init(void)
omap2_init_clk_clkdm(c->lk.clk);
}
/* Disable autoidle on all clocks; let the PM code enable it later */
omap_clk_disable_autoidle_all();
recalculate_root_clocks();
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
@ -3557,9 +3562,10 @@ int __init omap3xxx_clk_init(void)
clk_enable_init_clocks();
/*
* Lock DPLL5 and put it in autoidle.
* Lock DPLL5 -- here only until other device init code can
* handle this
*/
if (omap_rev() >= OMAP3430_REV_ES2_0)
if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */

77
arch/arm/mach-omap2/clock44xx_data.c
View File

@ -278,8 +278,10 @@ static struct clk dpll_abe_ck = {
static struct clk dpll_abe_x2_ck = {
.name = "dpll_abe_x2_ck",
.parent = &dpll_abe_ck,
.ops = &clkops_null,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap3_clkoutx2_recalc,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
};
static const struct clksel_rate div31_1to31_rates[] = {
@ -328,7 +330,7 @@ static struct clk dpll_abe_m2x2_ck = {
.clksel = dpll_abe_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -395,7 +397,7 @@ static struct clk dpll_abe_m3x2_ck = {
.clksel = dpll_abe_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -443,13 +445,14 @@ static struct clk dpll_core_ck = {
.parent = &sys_clkin_ck,
.dpll_data = &dpll_core_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_null,
.ops = &clkops_omap3_core_dpll_ops,
.recalc = &omap3_dpll_recalc,
};
static struct clk dpll_core_x2_ck = {
.name = "dpll_core_x2_ck",
.parent = &dpll_core_ck,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_null,
.recalc = &omap3_clkoutx2_recalc,
};
@ -465,7 +468,7 @@ static struct clk dpll_core_m6x2_ck = {
.clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -495,7 +498,7 @@ static struct clk dpll_core_m2_ck = {
.clksel = dpll_core_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -515,7 +518,7 @@ static struct clk dpll_core_m5x2_ck = {
.clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -581,7 +584,7 @@ static struct clk dpll_core_m4x2_ck = {
.clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -606,7 +609,7 @@ static struct clk dpll_abe_m2_ck = {
.clksel = dpll_abe_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -632,7 +635,7 @@ static struct clk dpll_core_m7x2_ck = {
.clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -689,6 +692,7 @@ static struct clk dpll_iva_ck = {
static struct clk dpll_iva_x2_ck = {
.name = "dpll_iva_x2_ck",
.parent = &dpll_iva_ck,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_null,
.recalc = &omap3_clkoutx2_recalc,
};
@ -704,7 +708,7 @@ static struct clk dpll_iva_m4x2_ck = {
.clksel = dpll_iva_m4x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -716,7 +720,7 @@ static struct clk dpll_iva_m5x2_ck = {
.clksel = dpll_iva_m4x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -764,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = {
.clksel = dpll_mpu_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -837,7 +841,7 @@ static struct clk dpll_per_m2_ck = {
.clksel = dpll_per_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -846,8 +850,10 @@ static struct clk dpll_per_m2_ck = {
static struct clk dpll_per_x2_ck = {
.name = "dpll_per_x2_ck",
.parent = &dpll_per_ck,
.ops = &clkops_null,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap3_clkoutx2_recalc,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
};
static const struct clksel dpll_per_m2x2_div[] = {
@ -861,7 +867,7 @@ static struct clk dpll_per_m2x2_ck = {
.clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -887,7 +893,7 @@ static struct clk dpll_per_m4x2_ck = {
.clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -899,7 +905,7 @@ static struct clk dpll_per_m5x2_ck = {
.clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -911,7 +917,7 @@ static struct clk dpll_per_m6x2_ck = {
.clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -923,7 +929,7 @@ static struct clk dpll_per_m7x2_ck = {
.clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -964,6 +970,7 @@ static struct clk dpll_unipro_ck = {
static struct clk dpll_unipro_x2_ck = {
.name = "dpll_unipro_x2_ck",
.parent = &dpll_unipro_ck,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_null,
.recalc = &omap3_clkoutx2_recalc,
};
@ -979,7 +986,7 @@ static struct clk dpll_unipro_m2x2_ck = {
.clksel = dpll_unipro_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -1028,7 +1035,8 @@ static struct clk dpll_usb_ck = {
static struct clk dpll_usb_clkdcoldo_ck = {
.name = "dpll_usb_clkdcoldo_ck",
.parent = &dpll_usb_ck,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
.recalc = &followparent_recalc,
};
@ -1043,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = {
.clksel = dpll_usb_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
.ops = &clkops_null,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@ -3158,11 +3166,11 @@ static struct omap_clk omap44xx_clks[] = {
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X),
CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X),
CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X),
CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X),
CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X),
CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X),
CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X),
CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
@ -3245,11 +3253,11 @@ static struct omap_clk omap44xx_clks[] = {
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
@ -3301,6 +3309,9 @@ int __init omap4xxx_clk_init(void)
omap2_init_clk_clkdm(c->lk.clk);
}
/* Disable autoidle on all clocks; let the PM code enable it later */
omap_clk_disable_autoidle_all();
recalculate_root_clocks();
/*

6
arch/arm/mach-omap2/clock_common_data.c
View File

@ -37,3 +37,9 @@ const struct clksel_rate gfx_l3_rates[] = {
{ .div = 0 }
};
const struct clksel_rate dsp_ick_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 3, .val = 3, .flags = RATE_IN_243X },
{ .div = 0 },
};

439
arch/arm/mach-omap2/clockdomain.c
View File

@ -26,17 +26,8 @@
#include <linux/bitops.h>
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "cminst44xx.h"
#include "prcm44xx.h"
#include <plat/clock.h>
#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/prcm.h>
/* clkdm_list contains all registered struct clockdomains */
static LIST_HEAD(clkdm_list);
@ -44,6 +35,7 @@ static LIST_HEAD(clkdm_list);
/* array of clockdomain deps to be added/removed when clkdm in hwsup mode */
static struct clkdm_autodep *autodeps;
static struct clkdm_ops *arch_clkdm;
/* Private functions */
@ -177,11 +169,11 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
* XXX autodeps are deprecated and should be removed at the earliest
* opportunity
*/
static void _clkdm_add_autodeps(struct clockdomain *clkdm)
void _clkdm_add_autodeps(struct clockdomain *clkdm)
{
struct clkdm_autodep *autodep;
if (!autodeps)
if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
return;
for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
@ -211,11 +203,11 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
* XXX autodeps are deprecated and should be removed at the earliest
* opportunity
*/
static void _clkdm_del_autodeps(struct clockdomain *clkdm)
void _clkdm_del_autodeps(struct clockdomain *clkdm)
{
struct clkdm_autodep *autodep;
if (!autodeps)
if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
return;
for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
@ -235,55 +227,29 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
}
/**
* _enable_hwsup - place a clockdomain into hardware-supervised idle
* @clkdm: struct clockdomain *
* _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
* @clkdm: clockdomain that we are resolving dependencies for
* @clkdm_deps: ptr to array of struct clkdm_deps to resolve
*
* Place the clockdomain into hardware-supervised idle mode. No return
* value.
*
* XXX Should this return an error if the clockdomain does not support
* hardware-supervised idle mode?
*/
static void _enable_hwsup(struct clockdomain *clkdm)
{
if (cpu_is_omap24xx())
omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
else if (cpu_is_omap34xx())
omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
else if (cpu_is_omap44xx())
return omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
clkdm->cm_inst,
clkdm->clkdm_offs);
else
BUG();
}
/**
* _disable_hwsup - place a clockdomain into software-supervised idle
* @clkdm: struct clockdomain *
*
* Place the clockdomain @clkdm into software-supervised idle mode.
* Iterates through @clkdm_deps, looking up the struct clockdomain named by
* clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
* No return value.
*
* XXX Should this return an error if the clockdomain does not support
* software-supervised idle mode?
*/
static void _disable_hwsup(struct clockdomain *clkdm)
static void _resolve_clkdm_deps(struct clockdomain *clkdm,
struct clkdm_dep *clkdm_deps)
{
if (cpu_is_omap24xx())
omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
else if (cpu_is_omap34xx())
omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
else if (cpu_is_omap44xx())
return omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
clkdm->cm_inst,
clkdm->clkdm_offs);
else
BUG();
struct clkdm_dep *cd;
for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (cd->clkdm)
continue;
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen",
clkdm->name, cd->clkdm_name);
}
}
/* Public functions */
@ -292,6 +258,7 @@ static void _disable_hwsup(struct clockdomain *clkdm)
* clkdm_init - set up the clockdomain layer
* @clkdms: optional pointer to an array of clockdomains to register
* @init_autodeps: optional pointer to an array of autodeps to register
* @custom_funcs: func pointers for arch specfic implementations
*
* Set up internal state. If a pointer to an array of clockdomains
* @clkdms was supplied, loop through the list of clockdomains,
@ -300,12 +267,18 @@ static void _disable_hwsup(struct clockdomain *clkdm)
* @init_autodeps was provided, register those. No return value.
*/
void clkdm_init(struct clockdomain **clkdms,
struct clkdm_autodep *init_autodeps)
struct clkdm_autodep *init_autodeps,
struct clkdm_ops *custom_funcs)
{
struct clockdomain **c = NULL;
struct clockdomain *clkdm;
struct clkdm_autodep *autodep = NULL;
if (!custom_funcs)
WARN(1, "No custom clkdm functions registered\n");
else
arch_clkdm = custom_funcs;
if (clkdms)
for (c = clkdms; *c; c++)
_clkdm_register(*c);
@ -321,11 +294,14 @@ void clkdm_init(struct clockdomain **clkdms,
*/
list_for_each_entry(clkdm, &clkdm_list, node) {
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
omap2_clkdm_wakeup(clkdm);
clkdm_wakeup(clkdm);
else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
omap2_clkdm_deny_idle(clkdm);
clkdm_deny_idle(clkdm);
_resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
clkdm_clear_all_wkdeps(clkdm);
_resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
clkdm_clear_all_sleepdeps(clkdm);
}
}
@ -422,32 +398,32 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
clkdm1->name, clkdm2->name, __func__);
return -EINVAL;
}
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
if (IS_ERR(cd)) {
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear wake up of "
"%s when %s wakes up\n", clkdm1->name, clkdm2->name);
return PTR_ERR(cd);
return ret;
}
if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
pr_debug("clockdomain: hardware will wake up %s when %s wakes "
"up\n", clkdm1->name, clkdm2->name);
omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
}
return 0;
return ret;
}
/**
@ -463,32 +439,32 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
clkdm1->name, clkdm2->name, __func__);
return -EINVAL;
}
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
if (IS_ERR(cd)) {
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear wake up of "
"%s when %s wakes up\n", clkdm1->name, clkdm2->name);
return PTR_ERR(cd);
return ret;
}
if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
pr_debug("clockdomain: hardware will no longer wake up %s "
"after %s wakes up\n", clkdm1->name, clkdm2->name);
omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
}
return 0;
return ret;
}
/**
@ -508,26 +484,26 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
clkdm1->name, clkdm2->name, __func__);
return -EINVAL;
}
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
if (IS_ERR(cd)) {
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_read_wkdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear wake up of "
"%s when %s wakes up\n", clkdm1->name, clkdm2->name);
return PTR_ERR(cd);
return ret;
}
/* XXX It's faster to return the atomic wkdep_usecount */
return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
(1 << clkdm2->dep_bit));
return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
}
/**
@ -542,33 +518,13 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
*/
int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
{
struct clkdm_dep *cd;
u32 mask = 0;
if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
pr_err("clockdomain: %s: %s: not yet implemented\n",
clkdm->name, __func__);
return -EINVAL;
}
if (!clkdm)
return -EINVAL;
for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_wkdeps)
return -EINVAL;
if (!cd->clkdm && cd->clkdm_name)
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
/* PRM accesses are slow, so minimize them */
mask |= 1 << cd->clkdm->dep_bit;
atomic_set(&cd->wkdep_usecount, 0);
}
omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
return 0;
return arch_clkdm->clkdm_clear_all_wkdeps(clkdm);
}
/**
@ -586,31 +542,33 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
if (!cpu_is_omap34xx())
return -EINVAL;
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
if (IS_ERR(cd)) {
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear sleep "
"dependency affecting %s from %s\n", clkdm1->name,
clkdm2->name);
return PTR_ERR(cd);
return ret;
}
if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
pr_debug("clockdomain: will prevent %s from sleeping if %s "
"is active\n", clkdm1->name, clkdm2->name);
omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP);
ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
}
return 0;
return ret;
}
/**
@ -628,19 +586,23 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
if (!cpu_is_omap34xx())
return -EINVAL;
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
if (IS_ERR(cd)) {
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear sleep "
"dependency affecting %s from %s\n", clkdm1->name,
clkdm2->name);
return PTR_ERR(cd);
return ret;
}
if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
@ -648,12 +610,10 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
"sleeping if %s is active\n", clkdm1->name,
clkdm2->name);
omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP);
ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
}
return 0;
return ret;
}
/**
@ -675,25 +635,27 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
{
struct clkdm_dep *cd;
if (!cpu_is_omap34xx())
return -EINVAL;
int ret = 0;
if (!clkdm1 || !clkdm2)
return -EINVAL;
cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
if (IS_ERR(cd)) {
if (IS_ERR(cd))
ret = PTR_ERR(cd);
if (!arch_clkdm || !arch_clkdm->clkdm_read_sleepdep)
ret = -EINVAL;
if (ret) {
pr_debug("clockdomain: hardware cannot set/clear sleep "
"dependency affecting %s from %s\n", clkdm1->name,
clkdm2->name);
return PTR_ERR(cd);
return ret;
}
/* XXX It's faster to return the atomic sleepdep_usecount */
return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP,
(1 << clkdm2->dep_bit));
return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
}
/**
@ -708,35 +670,17 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
*/
int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
{
struct clkdm_dep *cd;
u32 mask = 0;
if (!cpu_is_omap34xx())
return -EINVAL;
if (!clkdm)
return -EINVAL;
for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_sleepdeps)
return -EINVAL;
if (!cd->clkdm && cd->clkdm_name)
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
/* PRM accesses are slow, so minimize them */
mask |= 1 << cd->clkdm->dep_bit;
atomic_set(&cd->sleepdep_usecount, 0);
}
omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP);
return 0;
return arch_clkdm->clkdm_clear_all_sleepdeps(clkdm);
}
/**
* omap2_clkdm_sleep - force clockdomain sleep transition
* clkdm_sleep - force clockdomain sleep transition
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a sleep transition on the specified
@ -744,7 +688,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
* clockdomain does not support software-initiated sleep; 0 upon
* success.
*/
int omap2_clkdm_sleep(struct clockdomain *clkdm)
int clkdm_sleep(struct clockdomain *clkdm)
{
if (!clkdm)
return -EINVAL;
@ -755,33 +699,16 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
return -EINVAL;
}
if (!arch_clkdm || !arch_clkdm->clkdm_sleep)
return -EINVAL;
pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
if (cpu_is_omap24xx()) {
omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
} else if (cpu_is_omap34xx()) {
omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
} else if (cpu_is_omap44xx()) {
omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
clkdm->cm_inst,
clkdm->clkdm_offs);
} else {
BUG();
};
return 0;
return arch_clkdm->clkdm_sleep(clkdm);
}
/**
* omap2_clkdm_wakeup - force clockdomain wakeup transition
* clkdm_wakeup - force clockdomain wakeup transition
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a wakeup transition on the specified
@ -789,7 +716,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
* clockdomain does not support software-controlled wakeup; 0 upon
* success.
*/
int omap2_clkdm_wakeup(struct clockdomain *clkdm)
int clkdm_wakeup(struct clockdomain *clkdm)
{
if (!clkdm)
return -EINVAL;
@ -800,33 +727,16 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
return -EINVAL;
}
if (!arch_clkdm || !arch_clkdm->clkdm_wakeup)
return -EINVAL;
pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
if (cpu_is_omap24xx()) {
omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
} else if (cpu_is_omap34xx()) {
omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
} else if (cpu_is_omap44xx()) {
omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
clkdm->cm_inst,
clkdm->clkdm_offs);
} else {
BUG();
};
return 0;
return arch_clkdm->clkdm_wakeup(clkdm);
}
/**
* omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm
* clkdm_allow_idle - enable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
* Allow the hardware to automatically switch the clockdomain @clkdm into
@ -835,7 +745,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
* framework, wkdep/sleepdep autodependencies are added; this is so
* device drivers can read and write to the device. No return value.
*/
void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
void clkdm_allow_idle(struct clockdomain *clkdm)
{
if (!clkdm)
return;
@ -846,27 +756,18 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
return;
}
if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle)
return;
pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
clkdm->name);
/*
* XXX This should be removed once TI adds wakeup/sleep
* dependency code and data for OMAP4.
*/
if (cpu_is_omap44xx()) {
pr_err("clockdomain: %s: OMAP4 wakeup/sleep dependency support: not yet implemented\n", clkdm->name);
} else {
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_add_autodeps(clkdm);
}
_enable_hwsup(clkdm);
arch_clkdm->clkdm_allow_idle(clkdm);
pwrdm_clkdm_state_switch(clkdm);
}
/**
* omap2_clkdm_deny_idle - disable hwsup idle transitions for clkdm
* clkdm_deny_idle - disable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
* Prevent the hardware from automatically switching the clockdomain
@ -874,7 +775,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
* downstream clocks enabled in the clock framework, wkdep/sleepdep
* autodependencies are removed. No return value.
*/
void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
void clkdm_deny_idle(struct clockdomain *clkdm)
{
if (!clkdm)
return;
@ -885,28 +786,20 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
return;
}
if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle)
return;
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
clkdm->name);
_disable_hwsup(clkdm);
/*
* XXX This should be removed once TI adds wakeup/sleep
* dependency code and data for OMAP4.
*/
if (cpu_is_omap44xx()) {
pr_err("clockdomain: %s: OMAP4 wakeup/sleep dependency support: not yet implemented\n", clkdm->name);
} else {
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_del_autodeps(clkdm);
}
arch_clkdm->clkdm_deny_idle(clkdm);
}
/* Clockdomain-to-clock framework interface code */
/**
* omap2_clkdm_clk_enable - add an enabled downstream clock to this clkdm
* clkdm_clk_enable - add an enabled downstream clock to this clkdm
* @clkdm: struct clockdomain *
* @clk: struct clk * of the enabled downstream clock
*
@ -919,10 +812,8 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
* by on-chip processors. Returns -EINVAL if passed null pointers;
* returns 0 upon success or if the clockdomain is in hwsup idle mode.
*/
int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
{
bool hwsup = false;
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream clocks for debugging purposes?
@ -931,6 +822,9 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
if (!clkdm || !clk)
return -EINVAL;
if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable)
return -EINVAL;
if (atomic_inc_return(&clkdm->usecount) > 1)
return 0;
@ -939,31 +833,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
clk->name);
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
if (!clkdm->clktrctrl_mask)
return 0;
hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
} else if (cpu_is_omap44xx()) {
hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
clkdm->cm_inst,
clkdm->clkdm_offs);
}
if (hwsup) {
/* Disable HW transitions when we are changing deps */
_disable_hwsup(clkdm);
_clkdm_add_autodeps(clkdm);
_enable_hwsup(clkdm);
} else {
omap2_clkdm_wakeup(clkdm);
}
arch_clkdm->clkdm_clk_enable(clkdm);
pwrdm_wait_transition(clkdm->pwrdm.ptr);
pwrdm_clkdm_state_switch(clkdm);
@ -971,7 +841,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
}
/**
* omap2_clkdm_clk_disable - remove an enabled downstream clock from this clkdm
* clkdm_clk_disable - remove an enabled downstream clock from this clkdm
* @clkdm: struct clockdomain *
* @clk: struct clk * of the disabled downstream clock
*
@ -984,10 +854,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
* is enabled; or returns 0 upon success or if the clockdomain is in
* hwsup idle mode.
*/
int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
{
bool hwsup = false;
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream clocks for debugging purposes?
@ -996,6 +864,9 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
if (!clkdm || !clk)
return -EINVAL;
if (!arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
#ifdef DEBUG
if (atomic_read(&clkdm->usecount) == 0) {
WARN_ON(1); /* underflow */
@ -1011,31 +882,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
clk->name);
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
if (!clkdm->clktrctrl_mask)
return 0;
hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
} else if (cpu_is_omap44xx()) {
hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
clkdm->cm_inst,
clkdm->clkdm_offs);
}
if (hwsup) {
/* Disable HW transitions when we are changing deps */
_disable_hwsup(clkdm);
_clkdm_del_autodeps(clkdm);
_enable_hwsup(clkdm);
} else {
omap2_clkdm_sleep(clkdm);
}
arch_clkdm->clkdm_clk_disable(clkdm);
pwrdm_clkdm_state_switch(clkdm);
return 0;

70
arch/arm/mach-omap2/clockdomain.h
View File

@ -4,7 +4,7 @@
* OMAP2/3 clockdomain framework functions
*
* Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008-2010 Nokia Corporation
* Copyright (C) 2008-2011 Nokia Corporation
*
* Paul Walmsley
*
@ -22,11 +22,19 @@
#include <plat/clock.h>
#include <plat/cpu.h>
/* Clockdomain capability flags */
/*
* Clockdomain flags
*
* XXX Document CLKDM_CAN_* flags
*
* CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
* clockdomain. (Currently, this applies to OMAP3 clockdomains only.)
*/
#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
#define CLKDM_NO_AUTODEPS (1 << 4)
#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
@ -116,7 +124,42 @@ struct clockdomain {
struct list_head node;
};
void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps);
/**
* struct clkdm_ops - Arch specfic function implementations
* @clkdm_add_wkdep: Add a wakeup dependency between clk domains
* @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
* @clkdm_read_wkdep: Read wakeup dependency state between clk domains
* @clkdm_clear_all_wkdeps: Remove all wakeup dependencies from the clk domain
* @clkdm_add_sleepdep: Add a sleep dependency between clk domains
* @clkdm_del_sleepdep: Delete a sleep dependency between clk domains
* @clkdm_read_sleepdep: Read sleep dependency state between clk domains
* @clkdm_clear_all_sleepdeps: Remove all sleep dependencies from the clk domain
* @clkdm_sleep: Force a clockdomain to sleep
* @clkdm_wakeup: Force a clockdomain to wakeup
* @clkdm_allow_idle: Enable hw supervised idle transitions for clock domain
* @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain
* @clkdm_clk_enable: Put the clkdm in right state for a clock enable
* @clkdm_clk_disable: Put the clkdm in right state for a clock disable
*/
struct clkdm_ops {
int (*clkdm_add_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
int (*clkdm_del_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
int (*clkdm_read_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
int (*clkdm_clear_all_wkdeps)(struct clockdomain *clkdm);
int (*clkdm_add_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
int (*clkdm_del_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
int (*clkdm_read_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
int (*clkdm_clear_all_sleepdeps)(struct clockdomain *clkdm);
int (*clkdm_sleep)(struct clockdomain *clkdm);
int (*clkdm_wakeup)(struct clockdomain *clkdm);
void (*clkdm_allow_idle)(struct clockdomain *clkdm);
void (*clkdm_deny_idle)(struct clockdomain *clkdm);
int (*clkdm_clk_enable)(struct clockdomain *clkdm);
int (*clkdm_clk_disable)(struct clockdomain *clkdm);
};
void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps,
struct clkdm_ops *custom_funcs);
struct clockdomain *clkdm_lookup(const char *name);
int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
@ -132,16 +175,23 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
void clkdm_allow_idle(struct clockdomain *clkdm);
void clkdm_deny_idle(struct clockdomain *clkdm);
int omap2_clkdm_wakeup(struct clockdomain *clkdm);
int omap2_clkdm_sleep(struct clockdomain *clkdm);
int clkdm_wakeup(struct clockdomain *clkdm);
int clkdm_sleep(struct clockdomain *clkdm);
int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
extern void __init omap2_clockdomains_init(void);
extern void __init omap2xxx_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
extern struct clkdm_ops omap4_clkdm_operations;
#endif

274
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c Normal file
View File

@ -0,0 +1,274 @@
/*
* OMAP2 and OMAP3 clockdomain control
*
* Copyright (C) 2008-2010 Texas Instruments, Inc.
* Copyright (C) 2008-2010 Nokia Corporation
*
* Derived from mach-omap2/clockdomain.c written by Paul Walmsley
* Rajendra Nayak <rnayak@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <plat/prcm.h>
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
#include "prm-regbits-24xx.h"
#include "clockdomain.h"
static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
return 0;
}
static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
return 0;
}
static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
PM_WKDEP, (1 << clkdm2->dep_bit));
}
static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
{
struct clkdm_dep *cd;
u32 mask = 0;
for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!cd->clkdm)
continue; /* only happens if data is erroneous */
/* PRM accesses are slow, so minimize them */
mask |= 1 << cd->clkdm->dep_bit;
atomic_set(&cd->wkdep_usecount, 0);
}
omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
PM_WKDEP);
return 0;
}
static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP);
return 0;
}
static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP);
return 0;
}
static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
}
static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
{
struct clkdm_dep *cd;
u32 mask = 0;
for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!cd->clkdm)
continue; /* only happens if data is erroneous */
/* PRM accesses are slow, so minimize them */
mask |= 1 << cd->clkdm->dep_bit;
atomic_set(&cd->sleepdep_usecount, 0);
}
omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP);
return 0;
}
static int omap2_clkdm_sleep(struct clockdomain *clkdm)
{
omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
clkdm->pwrdm.ptr->prcm_offs,
OMAP2_PM_PWSTCTRL);
return 0;
}
static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
{
omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
clkdm->pwrdm.ptr->prcm_offs,
OMAP2_PM_PWSTCTRL);
return 0;
}
static void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
{
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_add_autodeps(clkdm);
omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
}
static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
{
omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_del_autodeps(clkdm);
}
static void _enable_hwsup(struct clockdomain *clkdm)
{
if (cpu_is_omap24xx())
omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
else if (cpu_is_omap34xx())
omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
}
static void _disable_hwsup(struct clockdomain *clkdm)
{
if (cpu_is_omap24xx())
omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
else if (cpu_is_omap34xx())
omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
}
static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
{
bool hwsup = false;
if (!clkdm->clktrctrl_mask)
return 0;
hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
if (hwsup) {
/* Disable HW transitions when we are changing deps */
_disable_hwsup(clkdm);
_clkdm_add_autodeps(clkdm);
_enable_hwsup(clkdm);
} else {
clkdm_wakeup(clkdm);
}
return 0;
}
static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
{
bool hwsup = false;
if (!clkdm->clktrctrl_mask)
return 0;
hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
if (hwsup) {
/* Disable HW transitions when we are changing deps */
_disable_hwsup(clkdm);
_clkdm_del_autodeps(clkdm);
_enable_hwsup(clkdm);
} else {
clkdm_sleep(clkdm);
}
return 0;
}
static int omap3_clkdm_sleep(struct clockdomain *clkdm)
{
omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
return 0;
}
static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
{
omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
return 0;
}
static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
{
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_add_autodeps(clkdm);
omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
}
static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
{
omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
clkdm->clktrctrl_mask);
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_del_autodeps(clkdm);
}
struct clkdm_ops omap2_clkdm_operations = {
.clkdm_add_wkdep = omap2_clkdm_add_wkdep,
.clkdm_del_wkdep = omap2_clkdm_del_wkdep,
.clkdm_read_wkdep = omap2_clkdm_read_wkdep,
.clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
.clkdm_sleep = omap2_clkdm_sleep,
.clkdm_wakeup = omap2_clkdm_wakeup,
.clkdm_allow_idle = omap2_clkdm_allow_idle,
.clkdm_deny_idle = omap2_clkdm_deny_idle,
.clkdm_clk_enable = omap2_clkdm_clk_enable,
.clkdm_clk_disable = omap2_clkdm_clk_disable,
};
struct clkdm_ops omap3_clkdm_operations = {
.clkdm_add_wkdep = omap2_clkdm_add_wkdep,
.clkdm_del_wkdep = omap2_clkdm_del_wkdep,
.clkdm_read_wkdep = omap2_clkdm_read_wkdep,
.clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
.clkdm_add_sleepdep = omap3_clkdm_add_sleepdep,
.clkdm_del_sleepdep = omap3_clkdm_del_sleepdep,
.clkdm_read_sleepdep = omap3_clkdm_read_sleepdep,
.clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps,
.clkdm_sleep = omap3_clkdm_sleep,
.clkdm_wakeup = omap3_clkdm_wakeup,
.clkdm_allow_idle = omap3_clkdm_allow_idle,
.clkdm_deny_idle = omap3_clkdm_deny_idle,
.clkdm_clk_enable = omap2_clkdm_clk_enable,
.clkdm_clk_disable = omap2_clkdm_clk_disable,
};

137
arch/arm/mach-omap2/clockdomain44xx.c Normal file
View File

@ -0,0 +1,137 @@
/*
* OMAP4 clockdomain control
*
* Copyright (C) 2008-2010 Texas Instruments, Inc.
* Copyright (C) 2008-2010 Nokia Corporation
*
* Derived from mach-omap2/clockdomain.c written by Paul Walmsley
* Rajendra Nayak <rnayak@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include "clockdomain.h"
#include "cminst44xx.h"
#include "cm44xx.h"
static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
clkdm1->prcm_partition,
clkdm1->cm_inst, clkdm1->clkdm_offs +
OMAP4_CM_STATICDEP);
return 0;
}
static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
clkdm1->prcm_partition,
clkdm1->cm_inst, clkdm1->clkdm_offs +
OMAP4_CM_STATICDEP);
return 0;
}
static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
struct clockdomain *clkdm2)
{
return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
clkdm1->cm_inst, clkdm1->clkdm_offs +
OMAP4_CM_STATICDEP,
(1 << clkdm2->dep_bit));
}
static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
{
struct clkdm_dep *cd;
u32 mask = 0;
for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!cd->clkdm)
continue; /* only happens if data is erroneous */
mask |= 1 << cd->clkdm->dep_bit;
atomic_set(&cd->wkdep_usecount, 0);
}
omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs +
OMAP4_CM_STATICDEP);
return 0;
}
static int omap4_clkdm_sleep(struct clockdomain *clkdm)
{
omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);
return 0;
}
static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
{
omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);
return 0;
}
static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
{
omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);
}
static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
{
omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);
}
static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
{
bool hwsup = false;
hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);
if (!hwsup)
clkdm_wakeup(clkdm);
return 0;
}
static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
{
bool hwsup = false;
hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);
if (!hwsup)
clkdm_sleep(clkdm);
return 0;
}
struct clkdm_ops omap4_clkdm_operations = {
.clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep,
.clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep,
.clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep,
.clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
.clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep,
.clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep,
.clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep,
.clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
.clkdm_sleep = omap4_clkdm_sleep,
.clkdm_wakeup = omap4_clkdm_wakeup,
.clkdm_allow_idle = omap4_clkdm_allow_idle,
.clkdm_deny_idle = omap4_clkdm_deny_idle,
.clkdm_clk_enable = omap4_clkdm_clk_enable,
.clkdm_clk_disable = omap4_clkdm_clk_disable,
};

28
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
View File

@ -89,6 +89,8 @@ static struct clkdm_dep gfx_sgx_wkdeps[] = {
/* 24XX-specific possible dependencies */
#ifdef CONFIG_ARCH_OMAP2
/* Wakeup dependency source arrays */
/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
@ -168,10 +170,11 @@ static struct clkdm_dep core_24xx_wkdeps[] = {
{ NULL },
};
#endif /* CONFIG_ARCH_OMAP2 */
/* 2430-specific possible wakeup dependencies */
#ifdef CONFIG_ARCH_OMAP2430
#ifdef CONFIG_SOC_OMAP2430
/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
static struct clkdm_dep mdm_2430_wkdeps[] = {
@ -194,7 +197,7 @@ static struct clkdm_dep mdm_2430_wkdeps[] = {
{ NULL },
};
#endif /* CONFIG_ARCH_OMAP2430 */
#endif /* CONFIG_SOC_OMAP2430 */
/* OMAP3-specific possible dependencies */
@ -450,7 +453,7 @@ static struct clockdomain cm_clkdm = {
* 2420-only clockdomains
*/
#if defined(CONFIG_ARCH_OMAP2420)
#if defined(CONFIG_SOC_OMAP2420)
static struct clockdomain mpu_2420_clkdm = {
.name = "mpu_clkdm",
@ -514,14 +517,14 @@ static struct clockdomain dss_2420_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
#endif /* CONFIG_ARCH_OMAP2420 */
#endif /* CONFIG_SOC_OMAP2420 */
/*
* 2430-only clockdomains
*/
#if defined(CONFIG_ARCH_OMAP2430)
#if defined(CONFIG_SOC_OMAP2430)
static struct clockdomain mpu_2430_clkdm = {
.name = "mpu_clkdm",
@ -600,7 +603,7 @@ static struct clockdomain dss_2430_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
#endif /* CONFIG_ARCH_OMAP2430 */
#endif /* CONFIG_SOC_OMAP2430 */
/*
@ -811,7 +814,7 @@ static struct clockdomain *clockdomains_omap2[] __initdata = {
&cm_clkdm,
&prm_clkdm,
#ifdef CONFIG_ARCH_OMAP2420
#ifdef CONFIG_SOC_OMAP2420
&mpu_2420_clkdm,
&iva1_2420_clkdm,
&dsp_2420_clkdm,
@ -821,7 +824,7 @@ static struct clockdomain *clockdomains_omap2[] __initdata = {
&dss_2420_clkdm,
#endif
#ifdef CONFIG_ARCH_OMAP2430
#ifdef CONFIG_SOC_OMAP2430
&mpu_2430_clkdm,
&mdm_clkdm,
&dsp_2430_clkdm,
@ -854,7 +857,12 @@ static struct clockdomain *clockdomains_omap2[] __initdata = {
NULL,
};
void __init omap2_clockdomains_init(void)
void __init omap2xxx_clockdomains_init(void)
{
clkdm_init(clockdomains_omap2, clkdm_autodeps);
clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
}
void __init omap3xxx_clockdomains_init(void)
{
clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
}

396
arch/arm/mach-omap2/clockdomains44xx_data.c
View File

@ -18,11 +18,6 @@
* published by the Free Software Foundation.
*/
/*
* To-Do List
* -> Populate the Sleep/Wakeup dependencies for the domains
*/
#include <linux/kernel.h>
#include <linux/io.h>
@ -35,6 +30,355 @@
#include "prcm44xx.h"
#include "prcm_mpu44xx.h"
/* Static Dependencies for OMAP4 Clock Domains */
static struct clkdm_dep ducati_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_dss_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_gfx_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_secure_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "tesla_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep iss_wkup_sleep_deps[] = {
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ducati_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_dss_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_secure_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_secure_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ducati_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_dss_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_gfx_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_secure_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "tesla_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep tesla_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clockdomain l4_cefuse_44xx_clkdm = {
.name = "l4_cefuse_clkdm",
@ -52,6 +396,7 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
.dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -62,6 +407,9 @@ static struct clockdomain tesla_44xx_clkdm = {
.prcm_partition = OMAP4430_CM1_PARTITION,
.cm_inst = OMAP4430_CM1_TESLA_INST,
.clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
.dep_bit = OMAP4430_TESLA_STATDEP_SHIFT,
.wkdep_srcs = tesla_wkup_sleep_deps,
.sleepdep_srcs = tesla_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -72,6 +420,9 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_GFX_INST,
.clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
.dep_bit = OMAP4430_GFX_STATDEP_SHIFT,
.wkdep_srcs = l3_gfx_wkup_sleep_deps,
.sleepdep_srcs = l3_gfx_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -82,6 +433,9 @@ static struct clockdomain ivahd_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_IVAHD_INST,
.clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
.dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT,
.wkdep_srcs = ivahd_wkup_sleep_deps,
.sleepdep_srcs = ivahd_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -92,6 +446,9 @@ static struct clockdomain l4_secure_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_L4PER_INST,
.clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
.dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
.wkdep_srcs = l4_secure_wkup_sleep_deps,
.sleepdep_srcs = l4_secure_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -102,6 +459,7 @@ static struct clockdomain l4_per_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_L4PER_INST,
.clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
.dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -112,6 +470,7 @@ static struct clockdomain abe_44xx_clkdm = {
.prcm_partition = OMAP4430_CM1_PARTITION,
.cm_inst = OMAP4430_CM1_ABE_INST,
.clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
.dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -131,6 +490,9 @@ static struct clockdomain l3_init_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_L3INIT_INST,
.clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
.dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT,
.wkdep_srcs = l3_init_wkup_sleep_deps,
.sleepdep_srcs = l3_init_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -141,6 +503,8 @@ static struct clockdomain mpuss_44xx_clkdm = {
.prcm_partition = OMAP4430_CM1_PARTITION,
.cm_inst = OMAP4430_CM1_MPU_INST,
.clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
.wkdep_srcs = mpuss_wkup_sleep_deps,
.sleepdep_srcs = mpuss_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -150,7 +514,7 @@ static struct clockdomain mpu0_44xx_clkdm = {
.pwrdm = { .name = "cpu0_pwrdm" },
.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
.cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
.clkdm_offs = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS,
.clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -160,7 +524,7 @@ static struct clockdomain mpu1_44xx_clkdm = {
.pwrdm = { .name = "cpu1_pwrdm" },
.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
.cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
.clkdm_offs = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS,
.clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -171,6 +535,7 @@ static struct clockdomain l3_emif_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
.dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -191,6 +556,9 @@ static struct clockdomain ducati_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
.dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT,
.wkdep_srcs = ducati_wkup_sleep_deps,
.sleepdep_srcs = ducati_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -201,6 +569,7 @@ static struct clockdomain l3_2_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
.dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -211,6 +580,7 @@ static struct clockdomain l3_1_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
.dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -221,6 +591,8 @@ static struct clockdomain l3_d2d_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
.wkdep_srcs = l3_d2d_wkup_sleep_deps,
.sleepdep_srcs = l3_d2d_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -231,6 +603,8 @@ static struct clockdomain iss_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CAM_INST,
.clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
.wkdep_srcs = iss_wkup_sleep_deps,
.sleepdep_srcs = iss_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -241,6 +615,9 @@ static struct clockdomain l3_dss_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_DSS_INST,
.clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
.dep_bit = OMAP4430_DSS_STATDEP_SHIFT,
.wkdep_srcs = l3_dss_wkup_sleep_deps,
.sleepdep_srcs = l3_dss_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -251,6 +628,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
.prcm_partition = OMAP4430_PRM_PARTITION,
.cm_inst = OMAP4430_PRM_WKUP_CM_INST,
.clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
.dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -271,6 +649,8 @@ static struct clockdomain l3_dma_44xx_clkdm = {
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
.wkdep_srcs = l3_dma_wkup_sleep_deps,
.sleepdep_srcs = l3_dma_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -305,5 +685,5 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
void __init omap44xx_clockdomains_init(void)
{
clkdm_init(clockdomains_omap44xx, NULL);
clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
}

3
arch/arm/mach-omap2/cm-regbits-24xx.h
View File

@ -210,8 +210,11 @@
#define OMAP24XX_AUTO_USB_MASK (1 << 0)
/* CM_AUTOIDLE3_CORE */
#define OMAP24XX_AUTO_SDRC_SHIFT 2
#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
#define OMAP24XX_AUTO_GPMC_SHIFT 1
#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
#define OMAP24XX_AUTO_SDMA_SHIFT 0
#define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
/* CM_AUTOIDLE4_CORE */

69
arch/arm/mach-omap2/cm2xxx_3xxx.c
View File

@ -25,6 +25,14 @@
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
#define DPLL_AUTOIDLE_DISABLE 0x0
#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
static const u8 cm_idlest_offs[] = {
CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
};
@ -125,6 +133,67 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
}
/*
* DPLL autoidle control
*/
static void _omap2xxx_set_dpll_autoidle(u8 m)
{
u32 v;
v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
v &= ~OMAP24XX_AUTO_DPLL_MASK;
v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
}
void omap2xxx_cm_set_dpll_disable_autoidle(void)
{
_omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
}
void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
{
_omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
}
/*
* APLL autoidle control
*/
static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
{
u32 v;
v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
v &= ~mask;
v |= m << __ffs(mask);
omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
}
void omap2xxx_cm_set_apll54_disable_autoidle(void)
{
_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
OMAP24XX_AUTO_54M_MASK);
}
void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
{
_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
OMAP24XX_AUTO_54M_MASK);
}
void omap2xxx_cm_set_apll96_disable_autoidle(void)
{
_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
OMAP24XX_AUTO_96M_MASK);
}
void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
{
_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
OMAP24XX_AUTO_96M_MASK);
}
/*
*

8
arch/arm/mach-omap2/cm2xxx_3xxx.h
View File

@ -122,6 +122,14 @@ extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
#endif
/* CM register bits shared between 24XX and 3430 */

1
arch/arm/mach-omap2/cm44xx.h
View File

@ -21,6 +21,7 @@
#include "cm.h"
#define OMAP4_CM_CLKSTCTRL 0x0000
#define OMAP4_CM_STATICDEP 0x0004
/* Function prototypes */
# ifndef __ASSEMBLER__

21
arch/arm/mach-omap2/cminst44xx.c
View File

@ -73,6 +73,27 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
return v;
}
u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
{
return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
}
u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
{
return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
}
u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
{
u32 v;
v = omap4_cminst_read_inst_reg(part, inst, idx);
v &= mask;
v >>= __ffs(mask);
return v;
}
/*
*
*/

6
arch/arm/mach-omap2/cminst44xx.h
View File

@ -25,6 +25,12 @@ extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
s16 inst, s16 idx);
extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst,
s16 idx);
extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
s16 idx);
extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
u32 mask);
extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);

39
arch/arm/mach-omap2/common.c
View File

@ -40,7 +40,7 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
#endif
#if defined(CONFIG_ARCH_OMAP2420)
#if defined(CONFIG_SOC_OMAP2420)
static struct omap_globals omap242x_globals = {
.class = OMAP242X_CLASS,
@ -50,9 +50,6 @@ static struct omap_globals omap242x_globals = {
.ctrl = OMAP242X_CTRL_BASE,
.prm = OMAP2420_PRM_BASE,
.cm = OMAP2420_CM_BASE,
.uart1_phys = OMAP2_UART1_BASE,
.uart2_phys = OMAP2_UART2_BASE,
.uart3_phys = OMAP2_UART3_BASE,
};
void __init omap2_set_globals_242x(void)
@ -61,7 +58,7 @@ void __init omap2_set_globals_242x(void)
}
#endif
#if defined(CONFIG_ARCH_OMAP2430)
#if defined(CONFIG_SOC_OMAP2430)
static struct omap_globals omap243x_globals = {
.class = OMAP243X_CLASS,
@ -71,9 +68,6 @@ static struct omap_globals omap243x_globals = {
.ctrl = OMAP243X_CTRL_BASE,
.prm = OMAP2430_PRM_BASE,
.cm = OMAP2430_CM_BASE,
.uart1_phys = OMAP2_UART1_BASE,
.uart2_phys = OMAP2_UART2_BASE,
.uart3_phys = OMAP2_UART3_BASE,
};
void __init omap2_set_globals_243x(void)
@ -92,10 +86,6 @@ static struct omap_globals omap3_globals = {
.ctrl = OMAP343X_CTRL_BASE,
.prm = OMAP3430_PRM_BASE,
.cm = OMAP3430_CM_BASE,
.uart1_phys = OMAP3_UART1_BASE,
.uart2_phys = OMAP3_UART2_BASE,
.uart3_phys = OMAP3_UART3_BASE,
.uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */
};
void __init omap2_set_globals_3xxx(void)
@ -108,6 +98,27 @@ void __init omap3_map_io(void)
omap2_set_globals_3xxx();
omap34xx_map_common_io();
}
/*
* Adjust TAP register base such that omap3_check_revision accesses the correct
* TI816X register for checking device ID (it adds 0x204 to tap base while
* TI816X DEVICE ID register is at offset 0x600 from control base).
*/
#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \
TI816X_CONTROL_DEVICE_ID - 0x204)
static struct omap_globals ti816x_globals = {
.class = OMAP343X_CLASS,
.tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
.ctrl = TI816X_CTRL_BASE,
.prm = TI816X_PRCM_BASE,
.cm = TI816X_PRCM_BASE,
};
void __init omap2_set_globals_ti816x(void)
{
__omap2_set_globals(&ti816x_globals);
}
#endif
#if defined(CONFIG_ARCH_OMAP4)
@ -119,10 +130,6 @@ static struct omap_globals omap4_globals = {
.prm = OMAP4430_PRM_BASE,
.cm = OMAP4430_CM_BASE,
.cm2 = OMAP4430_CM2_BASE,
.uart1_phys = OMAP4_UART1_BASE,
.uart2_phys = OMAP4_UART2_BASE,
.uart3_phys = OMAP4_UART3_BASE,
.uart4_phys = OMAP4_UART4_BASE,
};
void __init omap2_set_globals_443x(void)

6
arch/arm/mach-omap2/control.h
View File

@ -52,6 +52,9 @@
#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
/* TI816X spefic control submodules */
#define TI816X_CONTROL_DEVCONF 0x600
/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
@ -241,6 +244,9 @@
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
/* TI816X CONTROL_DEVCONF register offsets */
#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000)
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.

15
arch/arm/mach-omap2/cpuidle34xx.c
View File

@ -58,6 +58,7 @@ struct omap3_processor_cx {
u32 core_state;
u32 threshold;
u32 flags;
const char *desc;
};
struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
@ -99,14 +100,14 @@ static int omap3_idle_bm_check(void)
static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
struct clockdomain *clkdm)
{
omap2_clkdm_allow_idle(clkdm);
clkdm_allow_idle(clkdm);
return 0;
}
static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
struct clockdomain *clkdm)
{
omap2_clkdm_deny_idle(clkdm);
clkdm_deny_idle(clkdm);
return 0;
}
@ -365,6 +366,7 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
omap3_power_states[OMAP3_STATE_C1].desc = "MPU ON + CORE ON";
/* C2 . MPU WFI + Core inactive */
omap3_power_states[OMAP3_STATE_C2].valid =
@ -380,6 +382,7 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
omap3_power_states[OMAP3_STATE_C2].desc = "MPU ON + CORE ON";
/* C3 . MPU CSWR + Core inactive */
omap3_power_states[OMAP3_STATE_C3].valid =
@ -395,6 +398,7 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
omap3_power_states[OMAP3_STATE_C3].desc = "MPU RET + CORE ON";
/* C4 . MPU OFF + Core inactive */
omap3_power_states[OMAP3_STATE_C4].valid =
@ -410,6 +414,7 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
omap3_power_states[OMAP3_STATE_C4].desc = "MPU OFF + CORE ON";
/* C5 . MPU CSWR + Core CSWR*/
omap3_power_states[OMAP3_STATE_C5].valid =
@ -425,6 +430,7 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
omap3_power_states[OMAP3_STATE_C5].desc = "MPU RET + CORE RET";
/* C6 . MPU OFF + Core CSWR */
omap3_power_states[OMAP3_STATE_C6].valid =
@ -440,6 +446,7 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
omap3_power_states[OMAP3_STATE_C6].desc = "MPU OFF + CORE RET";
/* C7 . MPU OFF + Core OFF */
omap3_power_states[OMAP3_STATE_C7].valid =
@ -455,6 +462,7 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
omap3_power_states[OMAP3_STATE_C7].desc = "MPU OFF + CORE OFF";
/*
* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
@ -464,7 +472,7 @@ void omap_init_power_states(void)
if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
omap3_power_states[OMAP3_STATE_C7].valid = 0;
cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n",
pr_warn("%s: core off state C7 disabled due to i583\n",
__func__);
}
}
@ -512,6 +520,7 @@ int __init omap3_idle_init(void)
if (cx->type == OMAP3_STATE_C1)
dev->safe_state = state;
sprintf(state->name, "C%d", count+1);
strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
count++;
}

639
arch/arm/mach-omap2/devices.c
View File

@ -15,6 +15,7 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
@ -30,10 +31,75 @@
#include <plat/dma.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/omap4-keypad.h>
#include "mux.h"
#include "control.h"
#define L3_MODULES_MAX_LEN 12
#define L3_MODULES 3
static int __init omap3_l3_init(void)
{
int l;
struct omap_hwmod *oh;
struct omap_device *od;
char oh_name[L3_MODULES_MAX_LEN];
/*
* To avoid code running on other OMAPs in
* multi-omap builds
*/
if (!(cpu_is_omap34xx()))
return -ENODEV;
l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
oh = omap_hwmod_lookup(oh_name);
if (!oh)
pr_err("could not look up %s\n", oh_name);
od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
NULL, 0, 0);
WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
return PTR_ERR(od);
}
postcore_initcall(omap3_l3_init);
static int __init omap4_l3_init(void)
{
int l, i;
struct omap_hwmod *oh[3];
struct omap_device *od;
char oh_name[L3_MODULES_MAX_LEN];
/*
* To avoid code running on other OMAPs in
* multi-omap builds
*/
if (!(cpu_is_omap44xx()))
return -ENODEV;
for (i = 0; i < L3_MODULES; i++) {
l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
oh[i] = omap_hwmod_lookup(oh_name);
if (!(oh[i]))
pr_err("could not look up %s\n", oh_name);
}
od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
0, NULL, 0, 0);
WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
return PTR_ERR(od);
}
postcore_initcall(omap4_l3_init);
#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
static struct resource cam_resources[] = {
@ -141,96 +207,70 @@ static inline void omap_init_camera(void)
}
#endif
struct omap_device_pm_latency omap_keyboard_latency[] = {
{
.deactivate_func = omap_device_idle_hwmods,
.activate_func = omap_device_enable_hwmods,
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
};
int __init omap4_keyboard_init(struct omap4_keypad_platform_data
*sdp4430_keypad_data)
{
struct omap_device *od;
struct omap_hwmod *oh;
struct omap4_keypad_platform_data *keypad_data;
unsigned int id = -1;
char *oh_name = "kbd";
char *name = "omap4-keypad";
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
return -ENODEV;
}
keypad_data = sdp4430_keypad_data;
od = omap_device_build(name, id, oh, keypad_data,
sizeof(struct omap4_keypad_platform_data),
omap_keyboard_latency,
ARRAY_SIZE(omap_keyboard_latency), 0);
if (IS_ERR(od)) {
WARN(1, "Cant build omap_device for %s:%s.\n",
name, oh->name);
return PTR_ERR(od);
}
return 0;
}
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
#define MBOX_REG_SIZE 0x120
#ifdef CONFIG_ARCH_OMAP2
static struct resource omap2_mbox_resources[] = {
{
.start = OMAP24XX_MAILBOX_BASE,
.end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
.flags = IORESOURCE_MEM,
static struct omap_device_pm_latency mbox_latencies[] = {
[0] = {
.activate_func = omap_device_enable_hwmods,
.deactivate_func = omap_device_idle_hwmods,
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
{
.start = INT_24XX_MAIL_U0_MPU,
.flags = IORESOURCE_IRQ,
.name = "dsp",
},
{
.start = INT_24XX_MAIL_U3_MPU,
.flags = IORESOURCE_IRQ,
.name = "iva",
},
};
static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
#else
#define omap2_mbox_resources NULL
#define omap2_mbox_resources_sz 0
#endif
#ifdef CONFIG_ARCH_OMAP3
static struct resource omap3_mbox_resources[] = {
{
.start = OMAP34XX_MAILBOX_BASE,
.end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_24XX_MAIL_U0_MPU,
.flags = IORESOURCE_IRQ,
.name = "dsp",
},
};
static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
#else
#define omap3_mbox_resources NULL
#define omap3_mbox_resources_sz 0
#endif
#ifdef CONFIG_ARCH_OMAP4
#define OMAP4_MBOX_REG_SIZE 0x130
static struct resource omap4_mbox_resources[] = {
{
.start = OMAP44XX_MAILBOX_BASE,
.end = OMAP44XX_MAILBOX_BASE +
OMAP4_MBOX_REG_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP44XX_IRQ_MAIL_U0,
.flags = IORESOURCE_IRQ,
.name = "mbox",
},
};
static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
#else
#define omap4_mbox_resources NULL
#define omap4_mbox_resources_sz 0
#endif
static struct platform_device mbox_device = {
.name = "omap-mailbox",
.id = -1,
};
static inline void omap_init_mbox(void)
{
if (cpu_is_omap24xx()) {
mbox_device.resource = omap2_mbox_resources;
mbox_device.num_resources = omap2_mbox_resources_sz;
} else if (cpu_is_omap34xx()) {
mbox_device.resource = omap3_mbox_resources;
mbox_device.num_resources = omap3_mbox_resources_sz;
} else if (cpu_is_omap44xx()) {
mbox_device.resource = omap4_mbox_resources;
mbox_device.num_resources = omap4_mbox_resources_sz;
} else {
pr_err("%s: platform not supported\n", __func__);
struct omap_hwmod *oh;
struct omap_device *od;
oh = omap_hwmod_lookup("mailbox");
if (!oh) {
pr_err("%s: unable to find hwmod\n", __func__);
return;
}
platform_device_register(&mbox_device);
od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
__func__, PTR_ERR(od));
}
#else
static inline void omap_init_mbox(void) { }
@ -279,163 +319,55 @@ static inline void omap_init_audio(void) {}
#include <plat/mcspi.h>
#define OMAP2_MCSPI1_BASE 0x48098000
#define OMAP2_MCSPI2_BASE 0x4809a000
#define OMAP2_MCSPI3_BASE 0x480b8000
#define OMAP2_MCSPI4_BASE 0x480ba000
#define OMAP4_MCSPI1_BASE 0x48098100
#define OMAP4_MCSPI2_BASE 0x4809a100
#define OMAP4_MCSPI3_BASE 0x480b8100
#define OMAP4_MCSPI4_BASE 0x480ba100
static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
.num_cs = 4,
};
static struct resource omap2_mcspi1_resources[] = {
{
.start = OMAP2_MCSPI1_BASE,
.end = OMAP2_MCSPI1_BASE + 0xff,
.flags = IORESOURCE_MEM,
struct omap_device_pm_latency omap_mcspi_latency[] = {
[0] = {
.deactivate_func = omap_device_idle_hwmods,
.activate_func = omap_device_enable_hwmods,
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
};
static struct platform_device omap2_mcspi1 = {
.name = "omap2_mcspi",
.id = 1,
.num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
.resource = omap2_mcspi1_resources,
.dev = {
.platform_data = &omap2_mcspi1_config,
},
};
static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
.num_cs = 2,
};
static struct resource omap2_mcspi2_resources[] = {
{
.start = OMAP2_MCSPI2_BASE,
.end = OMAP2_MCSPI2_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap2_mcspi2 = {
.name = "omap2_mcspi",
.id = 2,
.num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
.resource = omap2_mcspi2_resources,
.dev = {
.platform_data = &omap2_mcspi2_config,
},
};
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
.num_cs = 2,
};
static struct resource omap2_mcspi3_resources[] = {
{
.start = OMAP2_MCSPI3_BASE,
.end = OMAP2_MCSPI3_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap2_mcspi3 = {
.name = "omap2_mcspi",
.id = 3,
.num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
.resource = omap2_mcspi3_resources,
.dev = {
.platform_data = &omap2_mcspi3_config,
},
};
#endif
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
.num_cs = 1,
};
static struct resource omap2_mcspi4_resources[] = {
{
.start = OMAP2_MCSPI4_BASE,
.end = OMAP2_MCSPI4_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap2_mcspi4 = {
.name = "omap2_mcspi",
.id = 4,
.num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
.resource = omap2_mcspi4_resources,
.dev = {
.platform_data = &omap2_mcspi4_config,
},
};
#endif
#ifdef CONFIG_ARCH_OMAP4
static inline void omap4_mcspi_fixup(void)
static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
{
omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
}
#else
static inline void omap4_mcspi_fixup(void)
{
}
#endif
struct omap_device *od;
char *name = "omap2_mcspi";
struct omap2_mcspi_platform_config *pdata;
static int spi_num;
struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
static inline void omap2_mcspi3_init(void)
{
platform_device_register(&omap2_mcspi3);
}
#else
static inline void omap2_mcspi3_init(void)
{
}
#endif
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
if (!pdata) {
pr_err("Memory allocation for McSPI device failed\n");
return -ENOMEM;
}
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
static inline void omap2_mcspi4_init(void)
{
platform_device_register(&omap2_mcspi4);
pdata->num_cs = mcspi_attrib->num_chipselect;
switch (oh->class->rev) {
case OMAP2_MCSPI_REV:
case OMAP3_MCSPI_REV:
pdata->regs_offset = 0;
break;
case OMAP4_MCSPI_REV:
pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
break;
default:
pr_err("Invalid McSPI Revision value\n");
return -EINVAL;
}
spi_num++;
od = omap_device_build(name, spi_num, oh, pdata,
sizeof(*pdata), omap_mcspi_latency,
ARRAY_SIZE(omap_mcspi_latency), 0);
WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n",
name, oh->name);
kfree(pdata);
return 0;
}
#else
static inline void omap2_mcspi4_init(void)
{
}
#endif
static void omap_init_mcspi(void)
{
if (cpu_is_omap44xx())
omap4_mcspi_fixup();
platform_device_register(&omap2_mcspi1);
platform_device_register(&omap2_mcspi2);
if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
omap2_mcspi3_init();
if (cpu_is_omap343x() || cpu_is_omap44xx())
omap2_mcspi4_init();
omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
}
#else
@ -610,117 +542,10 @@ static inline void omap_init_aes(void) { }
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
#define MMCHS_SYSCONFIG 0x0010
#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
#define MMCHS_SYSSTATUS 0x0014
#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
static struct platform_device dummy_pdev = {
.dev = {
.bus = &platform_bus_type,
},
};
/**
* omap_hsmmc_reset() - Full reset of each HS-MMC controller
*
* Ensure that each MMC controller is fully reset. Controllers
* left in an unknown state (by bootloader) may prevent retention
* or OFF-mode. This is especially important in cases where the
* MMC driver is not enabled, _or_ built as a module.
*
* In order for reset to work, interface, functional and debounce
* clocks must be enabled. The debounce clock comes from func_32k_clk
* and is not under SW control, so we only enable i- and f-clocks.
**/
static void __init omap_hsmmc_reset(void)
{
u32 i, nr_controllers;
struct clk *iclk, *fclk;
if (cpu_is_omap242x())
return;
nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
(cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
for (i = 0; i < nr_controllers; i++) {
u32 v, base = 0;
struct device *dev = &dummy_pdev.dev;
switch (i) {
case 0:
base = OMAP2_MMC1_BASE;
break;
case 1:
base = OMAP2_MMC2_BASE;
break;
case 2:
base = OMAP3_MMC3_BASE;
break;
case 3:
if (!cpu_is_omap44xx())
return;
base = OMAP4_MMC4_BASE;
break;
case 4:
if (!cpu_is_omap44xx())
return;
base = OMAP4_MMC5_BASE;
break;
}
if (cpu_is_omap44xx())
base += OMAP4_MMC_REG_OFFSET;
dummy_pdev.id = i;
dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
iclk = clk_get(dev, "ick");
if (IS_ERR(iclk))
goto err1;
if (clk_enable(iclk))
goto err2;
fclk = clk_get(dev, "fck");
if (IS_ERR(fclk))
goto err3;
if (clk_enable(fclk))
goto err4;
omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
v = omap_readl(base + MMCHS_SYSSTATUS);
while (!(omap_readl(base + MMCHS_SYSSTATUS) &
MMCHS_SYSSTATUS_RESETDONE))
cpu_relax();
clk_disable(fclk);
clk_put(fclk);
clk_disable(iclk);
clk_put(iclk);
}
return;
err4:
clk_put(fclk);
err3:
clk_disable(iclk);
err2:
clk_put(iclk);
err1:
printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
"cannot reset.\n", __func__, i);
}
#else
static inline void omap_hsmmc_reset(void) {}
#endif
#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
int controller_nr)
static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
*mmc_controller)
{
if ((mmc_controller->slots[0].switch_pin > 0) && \
(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
@ -731,7 +556,6 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
OMAP_PIN_INPUT_PULLUP);
if (cpu_is_omap2420() && controller_nr == 0) {
omap_mux_init_signal("sdmmc_cmd", 0);
omap_mux_init_signal("sdmmc_clki", 0);
omap_mux_init_signal("sdmmc_clko", 0);
@ -756,138 +580,20 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
v |= (1 << 24);
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
}
}
if (cpu_is_omap34xx()) {
if (controller_nr == 0) {
omap_mux_init_signal("sdmmc1_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat0",
OMAP_PIN_INPUT_PULLUP);
if (mmc_controller->slots[0].caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc1_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc1_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
if (controller_nr == 1) {
/* MMC2 */
omap_mux_init_signal("sdmmc2_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat0",
OMAP_PIN_INPUT_PULLUP);
/*
* For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
* in the board-*.c files
*/
if (mmc_controller->slots[0].caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc2_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
/*
* For MMC3 the pins need to be muxed in the board-*.c files
*/
}
}
void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
int nr_controllers)
void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
{
int i;
char *name;
char *name = "mmci-omap";
for (i = 0; i < nr_controllers; i++) {
unsigned long base, size;
unsigned int irq = 0;
if (!mmc_data[i])
continue;
omap2_mmc_mux(mmc_data[i], i);
switch (i) {
case 0:
base = OMAP2_MMC1_BASE;
irq = INT_24XX_MMC_IRQ;
break;
case 1:
base = OMAP2_MMC2_BASE;
irq = INT_24XX_MMC2_IRQ;
break;
case 2:
if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
if (!mmc_data[0]) {
pr_err("%s fails: Incomplete platform data\n", __func__);
return;
base = OMAP3_MMC3_BASE;
irq = INT_34XX_MMC3_IRQ;
break;
case 3:
if (!cpu_is_omap44xx())
return;
base = OMAP4_MMC4_BASE;
irq = OMAP44XX_IRQ_MMC4;
break;
case 4:
if (!cpu_is_omap44xx())
return;
base = OMAP4_MMC5_BASE;
irq = OMAP44XX_IRQ_MMC5;
break;
default:
continue;
}
if (cpu_is_omap2420()) {
size = OMAP2420_MMC_SIZE;
name = "mmci-omap";
} else if (cpu_is_omap44xx()) {
if (i < 3)
irq += OMAP44XX_IRQ_GIC_START;
size = OMAP4_HSMMC_SIZE;
name = "mmci-omap-hs";
} else {
size = OMAP3_HSMMC_SIZE;
name = "mmci-omap-hs";
}
omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
};
omap242x_mmc_mux(mmc_data[0]);
omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
INT_24XX_MMC_IRQ, mmc_data[0]);
}
#endif
@ -895,7 +601,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
#define OMAP_HDQ_BASE 0x480B2000
#endif
static struct resource omap_hdq_resources[] = {
@ -961,7 +667,6 @@ static int __init omap2_init_devices(void)
* please keep these calls, and their implementations above,
* in alphabetical order so they're easier to sort through.
*/
omap_hsmmc_reset();
omap_init_audio();
omap_init_camera();
omap_init_mbox();

45
arch/arm/mach-omap2/display.c Normal file
View File

@ -0,0 +1,45 @@
/*
* OMAP2plus display device setup / initialization.
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Senthilvadivu Guruswamy
* Sumit Semwal
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <plat/display.h>
static struct platform_device omap_display_device = {
.name = "omapdss",
.id = -1,
.dev = {
.platform_data = NULL,
},
};
int __init omap_display_init(struct omap_dss_board_info *board_data)
{
int r = 0;
omap_display_device.dev.platform_data = board_data;
r = platform_device_register(&omap_display_device);
if (r < 0)
printk(KERN_ERR "Unable to register OMAP-Display device\n");
return r;
}

84
arch/arm/mach-omap2/dpll44xx.c Normal file
View File

@ -0,0 +1,84 @@
/*
* OMAP4-specific DPLL control functions
*
* Copyright (C) 2011 Texas Instruments, Inc.
* Rajendra Nayak
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include "clock.h"
#include "cm-regbits-44xx.h"
/* Supported only on OMAP4 */
int omap4_dpllmx_gatectrl_read(struct clk *clk)
{
u32 v;
u32 mask;
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
return -EINVAL;
mask = clk->flags & CLOCK_CLKOUTX2 ?
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
v = __raw_readl(clk->clksel_reg);
v &= mask;
v >>= __ffs(mask);
return v;
}
void omap4_dpllmx_allow_gatectrl(struct clk *clk)
{
u32 v;
u32 mask;
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
return;
mask = clk->flags & CLOCK_CLKOUTX2 ?
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
v = __raw_readl(clk->clksel_reg);
/* Clear the bit to allow gatectrl */
v &= ~mask;
__raw_writel(v, clk->clksel_reg);
}
void omap4_dpllmx_deny_gatectrl(struct clk *clk)
{
u32 v;
u32 mask;
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
return;
mask = clk->flags & CLOCK_CLKOUTX2 ?
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
v = __raw_readl(clk->clksel_reg);
/* Set the bit to deny gatectrl */
v |= mask;
__raw_writel(v, clk->clksel_reg);
}
const struct clkops clkops_omap4_dpllmx_ops = {
.allow_idle = omap4_dpllmx_allow_gatectrl,
.deny_idle = omap4_dpllmx_deny_gatectrl,
};

7
arch/arm/mach-omap2/gpmc-nand.c
View File

@ -12,6 +12,7 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mtd/nand.h>
#include <asm/mach/flash.h>
@ -69,8 +70,10 @@ static int omap2_nand_gpmc_retime(void)
t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
/* Configure GPMC */
gpmc_cs_configure(gpmc_nand_data->cs,
GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize);
if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
else
gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
gpmc_cs_configure(gpmc_nand_data->cs,
GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);

125
arch/arm/mach-omap2/gpmc-onenand.c
View File

@ -94,7 +94,7 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
}
static void set_onenand_cfg(void __iomem *onenand_base, int latency,
int sync_read, int sync_write, int hf)
int sync_read, int sync_write, int hf, int vhf)
{
u32 reg;
@ -114,42 +114,31 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
reg |= ONENAND_SYS_CFG1_HF;
else
reg &= ~ONENAND_SYS_CFG1_HF;
if (vhf)
reg |= ONENAND_SYS_CFG1_VHF;
else
reg &= ~ONENAND_SYS_CFG1_VHF;
writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
}
static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
void __iomem *onenand_base,
int freq)
static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
void __iomem *onenand_base, bool *clk_dep)
{
struct gpmc_timings t;
const int t_cer = 15;
const int t_avdp = 12;
const int t_cez = 20; /* max of t_cez, t_oez */
const int t_ds = 30;
const int t_wpl = 40;
const int t_wph = 30;
int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
int first_time = 0, hf = 0, sync_read = 0, sync_write = 0;
int err, ticks_cez;
int cs = cfg->cs;
u32 reg;
u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
int freq = 0;
if (cfg->flags & ONENAND_SYNC_READ) {
sync_read = 1;
} else if (cfg->flags & ONENAND_SYNC_READWRITE) {
sync_read = 1;
sync_write = 1;
} else
return omap2_onenand_set_async_mode(cs, onenand_base);
if (cfg->get_freq) {
struct onenand_freq_info fi;
if (!freq) {
/* Very first call freq is not known */
err = omap2_onenand_set_async_mode(cs, onenand_base);
if (err)
return err;
reg = readw(onenand_base + ONENAND_REG_VERSION_ID);
switch ((reg >> 4) & 0xf) {
fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
fi.ver_id = ver;
freq = cfg->get_freq(&fi, clk_dep);
if (freq)
return freq;
}
switch ((ver >> 4) & 0xf) {
case 0:
freq = 40;
break;
@ -169,6 +158,43 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
freq = 54;
break;
}
return freq;
}
static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
void __iomem *onenand_base,
int *freq_ptr)
{
struct gpmc_timings t;
const int t_cer = 15;
const int t_avdp = 12;
const int t_cez = 20; /* max of t_cez, t_oez */
const int t_ds = 30;
const int t_wpl = 40;
const int t_wph = 30;
int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
int err, ticks_cez;
int cs = cfg->cs, freq = *freq_ptr;
u32 reg;
bool clk_dep = false;
if (cfg->flags & ONENAND_SYNC_READ) {
sync_read = 1;
} else if (cfg->flags & ONENAND_SYNC_READWRITE) {
sync_read = 1;
sync_write = 1;
} else
return omap2_onenand_set_async_mode(cs, onenand_base);
if (!freq) {
/* Very first call freq is not known */
err = omap2_onenand_set_async_mode(cs, onenand_base);
if (err)
return err;
freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
first_time = 1;
}
@ -180,7 +206,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
t_avdh = 2;
t_ach = 3;
t_aavdh = 6;
t_rdyo = 9;
t_rdyo = 6;
break;
case 83:
min_gpmc_clk_period = 12000; /* 83 MHz */
@ -217,16 +243,36 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
gpmc_clk_ns = gpmc_ticks_to_ns(div);
if (gpmc_clk_ns < 15) /* >66Mhz */
hf = 1;
if (hf)
if (gpmc_clk_ns < 12) /* >83Mhz */
vhf = 1;
if (vhf)
latency = 8;
else if (hf)
latency = 6;
else if (gpmc_clk_ns >= 25) /* 40 MHz*/
latency = 3;
else
latency = 4;
if (clk_dep) {
if (gpmc_clk_ns < 12) { /* >83Mhz */
t_ces = 3;
t_avds = 4;
} else if (gpmc_clk_ns < 15) { /* >66Mhz */
t_ces = 5;
t_avds = 4;
} else if (gpmc_clk_ns < 25) { /* >40Mhz */
t_ces = 6;
t_avds = 5;
} else {
t_ces = 7;
t_avds = 7;
}
}
if (first_time)
set_onenand_cfg(onenand_base, latency,
sync_read, sync_write, hf);
sync_read, sync_write, hf, vhf);
if (div == 1) {
reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@ -264,6 +310,9 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
/* Read */
t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
/* Force at least 1 clk between AVD High to OE Low */
if (t.oe_on <= t.adv_rd_off)
t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
t.cs_rd_off = t.oe_off;
@ -317,18 +366,20 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
if (err)
return err;
set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf);
set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
*freq_ptr = freq;
return 0;
}
static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
{
struct device *dev = &gpmc_onenand_device.dev;
/* Set sync timings in GPMC */
if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
freq) < 0) {
freq_ptr) < 0) {
dev_err(dev, "Unable to set synchronous mode\n");
return -EINVAL;
}

56
arch/arm/mach-omap2/gpmc.c
View File

@ -14,6 +14,7 @@
*/
#undef DEBUG
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
@ -22,6 +23,7 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <asm/mach-types.h>
#include <plat/gpmc.h>
@ -58,7 +60,6 @@
#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
#define GPMC_SECTION_SHIFT 28 /* 128 MB */
#define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
#define CS_NUM_SHIFT 24
#define ENABLE_PREFETCH (0x1 << 7)
#define DMA_MPU_MODE 2
@ -100,6 +101,8 @@ static void __iomem *gpmc_base;
static struct clk *gpmc_l3_clk;
static irqreturn_t gpmc_handle_irq(int irq, void *dev);
static void gpmc_write_reg(int idx, u32 val)
{
__raw_writel(val, gpmc_base + idx);
@ -497,6 +500,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
u32 regval = 0;
switch (cmd) {
case GPMC_ENABLE_IRQ:
gpmc_write_reg(GPMC_IRQENABLE, wval);
break;
case GPMC_SET_IRQ_STATUS:
gpmc_write_reg(GPMC_IRQSTATUS, wval);
break;
@ -598,15 +605,19 @@ EXPORT_SYMBOL(gpmc_nand_write);
/**
* gpmc_prefetch_enable - configures and starts prefetch transfer
* @cs: cs (chip select) number
* @fifo_th: fifo threshold to be used for read/ write
* @dma_mode: dma mode enable (1) or disable (0)
* @u32_count: number of bytes to be transferred
* @is_write: prefetch read(0) or write post(1) mode
*/
int gpmc_prefetch_enable(int cs, int dma_mode,
int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
unsigned int u32_count, int is_write)
{
if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
pr_err("gpmc: fifo threshold is not supported\n");
return -1;
} else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
/* Set the amount of bytes to be prefetched */
gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
@ -614,7 +625,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
* enable the engine. Set which cs is has requested for.
*/
gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
PREFETCH_FIFOTHRESHOLD |
PREFETCH_FIFOTHRESHOLD(fifo_th) |
ENABLE_PREFETCH |
(dma_mode << DMA_MPU_MODE) |
(0x1 & is_write)));
@ -678,9 +689,10 @@ static void __init gpmc_mem_init(void)
}
}
void __init gpmc_init(void)
static int __init gpmc_init(void)
{
u32 l;
u32 l, irq;
int cs, ret = -EINVAL;
char *ck = NULL;
if (cpu_is_omap24xx()) {
@ -698,7 +710,7 @@ void __init gpmc_init(void)
}
if (WARN_ON(!ck))
return;
return ret;
gpmc_l3_clk = clk_get(NULL, ck);
if (IS_ERR(gpmc_l3_clk)) {
@ -723,6 +735,36 @@ void __init gpmc_init(void)
l |= (0x02 << 3) | (1 << 0);
gpmc_write_reg(GPMC_SYSCONFIG, l);
gpmc_mem_init();
/* initalize the irq_chained */
irq = OMAP_GPMC_IRQ_BASE;
for (cs = 0; cs < GPMC_CS_NUM; cs++) {
set_irq_handler(irq, handle_simple_irq);
set_irq_flags(irq, IRQF_VALID);
irq++;
}
ret = request_irq(INT_34XX_GPMC_IRQ,
gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
if (ret)
pr_err("gpmc: irq-%d could not claim: err %d\n",
INT_34XX_GPMC_IRQ, ret);
return ret;
}
postcore_initcall(gpmc_init);
static irqreturn_t gpmc_handle_irq(int irq, void *dev)
{
u8 cs;
if (irq != INT_34XX_GPMC_IRQ)
return IRQ_HANDLED;
/* check cs to invoke the irq */
cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
return IRQ_HANDLED;
}
#ifdef CONFIG_ARCH_OMAP3

273
arch/arm/mach-omap2/hsmmc.c
View File

@ -16,7 +16,10 @@
#include <mach/hardware.h>
#include <plat/mmc.h>
#include <plat/omap-pm.h>
#include <plat/mux.h>
#include <plat/omap_device.h>
#include "mux.h"
#include "hsmmc.h"
#include "control.h"
@ -28,10 +31,6 @@ static u16 control_mmc1;
#define HSMMC_NAME_LEN 9
static struct hsmmc_controller {
char name[HSMMC_NAME_LEN + 1];
} hsmmc[OMAP34XX_NR_MMC];
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
static int hsmmc_get_context_loss(struct device *dev)
@ -204,64 +203,105 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
return 0;
}
static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
int controller_nr)
{
struct omap2_hsmmc_info *c;
int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
int i;
u32 reg;
if (!cpu_is_omap44xx()) {
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
} else {
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
if ((mmc_controller->slots[0].switch_pin > 0) && \
(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
OMAP_PIN_INPUT_PULLUP);
if ((mmc_controller->slots[0].gpio_wp > 0) && \
(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
OMAP_PIN_INPUT_PULLUP);
if (cpu_is_omap34xx()) {
if (controller_nr == 0) {
omap_mux_init_signal("sdmmc1_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat0",
OMAP_PIN_INPUT_PULLUP);
if (mmc_controller->slots[0].caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc1_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc1_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
if (controller_nr == 1) {
/* MMC2 */
omap_mux_init_signal("sdmmc2_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat0",
OMAP_PIN_INPUT_PULLUP);
/*
* For 8 wire configurations, Lines DAT4, 5, 6 and 7
* need to be muxed in the board-*.c files
*/
if (mmc_controller->slots[0].caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc2_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
OMAP_PIN_INPUT_PULLUP);
}
} else {
control_pbias_offset =
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
}
for (c = controllers; c->mmc; c++) {
struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
if (!c->mmc || c->mmc > nr_hsmmc) {
pr_debug("MMC%d: no such controller\n", c->mmc);
continue;
}
if (mmc) {
pr_debug("MMC%d: already configured\n", c->mmc);
continue;
/*
* For MMC3 the pins need to be muxed in the board-*.c files
*/
}
}
mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
GFP_KERNEL);
if (!mmc) {
pr_err("Cannot allocate memory for mmc device!\n");
goto done;
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
struct omap_mmc_platform_data *mmc)
{
char *hc_name;
hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
if (!hc_name) {
pr_err("Cannot allocate memory for controller slot name\n");
kfree(hc_name);
return -ENOMEM;
}
if (c->name)
strncpy(hc->name, c->name, HSMMC_NAME_LEN);
strncpy(hc_name, c->name, HSMMC_NAME_LEN);
else
snprintf(hc->name, ARRAY_SIZE(hc->name),
"mmc%islot%i", c->mmc, 1);
mmc->slots[0].name = hc->name;
snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
c->mmc, 1);
mmc->slots[0].name = hc_name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
mmc->slots[0].internal_clock = !c->ext_clock;
@ -294,7 +334,8 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
if (c->vcc_aux_disable_is_sleep)
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
/* NOTE: MMC slots should have a Vcc regulator set up.
/*
* NOTE: MMC slots should have a Vcc regulator set up.
* This may be from a TWL4030-family chip, another
* controllable regulator, or a fixed supply.
*
@ -327,7 +368,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
}
}
/* Omap3630 HSMMC1 supports only 4-bit */
/* OMAP3630 HSMMC1 supports only 4-bit */
if (cpu_is_omap3630() &&
(c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
@ -350,28 +391,124 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
mmc->slots[0].after_set_reg = NULL;
}
break;
case 4:
case 5:
mmc->slots[0].before_set_reg = NULL;
mmc->slots[0].after_set_reg = NULL;
break;
default:
pr_err("MMC%d configuration not supported!\n", c->mmc);
kfree(mmc);
continue;
kfree(hc_name);
return -ENODEV;
}
hsmmc_data[c->mmc - 1] = mmc;
return 0;
}
static struct omap_device_pm_latency omap_hsmmc_latency[] = {
[0] = {
.deactivate_func = omap_device_idle_hwmods,
.activate_func = omap_device_enable_hwmods,
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
/*
* XXX There should also be an entry here to power off/on the
* MMC regulators/PBIAS cells, etc.
*/
};
#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
{
struct omap_hwmod *oh;
struct omap_device *od;
struct omap_device_pm_latency *ohl;
char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
struct omap_mmc_platform_data *mmc_data;
struct omap_mmc_dev_attr *mmc_dev_attr;
char *name;
int l;
int ohl_cnt = 0;
mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
if (!mmc_data) {
pr_err("Cannot allocate memory for mmc device!\n");
goto done;
}
omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
/* pass the device nodes back to board setup code */
for (c = controllers; c->mmc; c++) {
struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
if (!c->mmc || c->mmc > nr_hsmmc)
continue;
c->dev = mmc->dev;
if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
pr_err("%s fails!\n", __func__);
goto done;
}
omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
name = "omap_hsmmc";
ohl = omap_hsmmc_latency;
ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
"mmc%d", ctrl_nr);
WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
"String buffer overflow in MMC%d device setup\n", ctrl_nr);
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
kfree(mmc_data->slots[0].name);
goto done;
}
if (oh->dev_attr != NULL) {
mmc_dev_attr = oh->dev_attr;
mmc_data->controller_flags = mmc_dev_attr->flags;
}
od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
if (IS_ERR(od)) {
WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name);
kfree(mmc_data->slots[0].name);
goto done;
}
/*
* return device handle to board setup code
* required to populate for regulator framework structure
*/
hsmmcinfo->dev = &od->pdev.dev;
done:
for (i = 0; i < nr_hsmmc; i++)
kfree(hsmmc_data[i]);
kfree(mmc_data);
}
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
u32 reg;
if (!cpu_is_omap44xx()) {
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
} else {
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
} else {
control_pbias_offset =
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
}
for (; controllers->mmc; controllers++)
omap_init_hsmmc(controllers, controllers->mmc);
}
#endif

63
arch/arm/mach-omap2/hwspinlock.c Normal file
View File

@ -0,0 +1,63 @@
/*
* OMAP hardware spinlock device initialization
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
*
* Contact: Simon Que <sque@ti.com>
* Hari Kanigeri <h-kanigeri2@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
struct omap_device_pm_latency omap_spinlock_latency[] = {
{
.deactivate_func = omap_device_idle_hwmods,
.activate_func = omap_device_enable_hwmods,
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
}
};
int __init hwspinlocks_init(void)
{
int retval = 0;
struct omap_hwmod *oh;
struct omap_device *od;
const char *oh_name = "spinlock";
const char *dev_name = "omap_hwspinlock";
/*
* Hwmod lookup will fail in case our platform doesn't support the
* hardware spinlock module, so it is safe to run this initcall
* on all omaps
*/
oh = omap_hwmod_lookup(oh_name);
if (oh == NULL)
return -EINVAL;
od = omap_device_build(dev_name, 0, oh, NULL, 0,
omap_spinlock_latency,
ARRAY_SIZE(omap_spinlock_latency), false);
if (IS_ERR(od)) {
pr_err("Can't build omap_device for %s:%s\n", dev_name,
oh_name);
retval = PTR_ERR(od);
}
return retval;
}
/* early board code might need to reserve specific hwspinlock instances */
postcore_initcall(hwspinlocks_init);

73
arch/arm/mach-omap2/id.c
View File

@ -6,7 +6,7 @@
* Copyright (C) 2005 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
*
* Copyright (C) 2009 Texas Instruments
* Copyright (C) 2009-11 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
@ -84,6 +84,11 @@ EXPORT_SYMBOL(omap_type);
#define OMAP_TAP_DIE_ID_2 0x0220
#define OMAP_TAP_DIE_ID_3 0x0224
#define OMAP_TAP_DIE_ID_44XX_0 0x0200
#define OMAP_TAP_DIE_ID_44XX_1 0x0208
#define OMAP_TAP_DIE_ID_44XX_2 0x020c
#define OMAP_TAP_DIE_ID_44XX_3 0x0210
#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
struct omap_id {
@ -107,6 +112,14 @@ static u16 tap_prod_id;
void omap_get_die_id(struct omap_die_id *odi)
{
if (cpu_is_omap44xx()) {
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
return;
}
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
@ -191,12 +204,19 @@ static void __init omap3_check_features(void)
if (!cpu_is_omap3505() && !cpu_is_omap3517())
omap3_features |= OMAP3_HAS_IO_WAKEUP;
omap3_features |= OMAP3_HAS_SDRC;
/*
* TODO: Get additional info (where applicable)
* e.g. Size of L2 cache.
*/
}
static void __init ti816x_check_features(void)
{
omap3_features = OMAP3_HAS_NEON;
}
static void __init omap3_check_revision(void)
{
u32 cpuid, idcode;
@ -287,6 +307,20 @@ static void __init omap3_check_revision(void)
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
}
break;
case 0xb81e:
omap_chip.oc = CHIP_IS_TI816X;
switch (rev) {
case 0:
omap_revision = TI8168_REV_ES1_0;
break;
case 1:
omap_revision = TI8168_REV_ES1_1;
break;
default:
omap_revision = TI8168_REV_ES1_1;
}
break;
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP3630_REV_ES1_2;
@ -307,7 +341,7 @@ static void __init omap4_check_revision(void)
*/
idcode = read_tap_reg(OMAP_TAP_IDCODE);
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0xff;
rev = (idcode >> 28) & 0xf;
/*
* Few initial ES2.0 samples IDCODE is same as ES1.0
@ -326,22 +360,31 @@ static void __init omap4_check_revision(void)
omap_chip.oc |= CHIP_IS_OMAP4430ES1;
break;
case 1:
omap_revision = OMAP4430_REV_ES2_0;
omap_chip.oc |= CHIP_IS_OMAP4430ES2;
break;
default:
omap_revision = OMAP4430_REV_ES2_0;
omap_chip.oc |= CHIP_IS_OMAP4430ES2;
}
break;
case 0xb95c:
switch (rev) {
case 3:
omap_revision = OMAP4430_REV_ES2_1;
omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
break;
case 4:
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP4430_REV_ES2_0;
omap_chip.oc |= CHIP_IS_OMAP4430ES2;
omap_revision = OMAP4430_REV_ES2_2;
omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
}
break;
default:
/* Unknown default to latest silicon rev as default */
omap_revision = OMAP4430_REV_ES2_2;
omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
}
pr_info("OMAP%04x ES%d.0\n",
omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
}
#define OMAP3_SHOW_FEATURE(feat) \
@ -372,6 +415,8 @@ static void __init omap3_cpuinfo(void)
/* Already set in omap3_check_revision() */
strcpy(cpu_name, "AM3505");
}
} else if (cpu_is_ti816x()) {
strcpy(cpu_name, "TI816X");
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
strcpy(cpu_name, "OMAP3430/3530");
@ -386,7 +431,7 @@ static void __init omap3_cpuinfo(void)
strcpy(cpu_name, "OMAP3503");
}
if (cpu_is_omap3630()) {
if (cpu_is_omap3630() || cpu_is_ti816x()) {
switch (rev) {
case OMAP_REVBITS_00:
strcpy(cpu_rev, "1.0");
@ -462,7 +507,13 @@ void __init omap2_check_revision(void)
omap24xx_check_revision();
} else if (cpu_is_omap34xx()) {
omap3_check_revision();
/* TI816X doesn't have feature register */
if (!cpu_is_ti816x())
omap3_check_features();
else
ti816x_check_features();
omap3_cpuinfo();
return;
} else if (cpu_is_omap44xx()) {

12
arch/arm/mach-omap2/include/mach/debug-macro.S
View File

@ -72,6 +72,12 @@ omap_uart_lsr: .word 0
beq 34f @ configure OMAP3UART4
cmp \rp, #OMAP4UART4 @ only on 44xx
beq 44f @ configure OMAP4UART4
cmp \rp, #TI816XUART1 @ ti816x UART offsets different
beq 81f @ configure UART1
cmp \rp, #TI816XUART2 @ ti816x UART offsets different
beq 82f @ configure UART2
cmp \rp, #TI816XUART3 @ ti816x UART offsets different
beq 83f @ configure UART3
cmp \rp, #ZOOM_UART @ only on zoom2/3
beq 95f @ configure ZOOM_UART
@ -94,6 +100,12 @@ omap_uart_lsr: .word 0
b 98f
44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
b 98f
81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE)
b 98f
82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE)
b 98f
83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE)
b 98f
95: ldr \rp, =ZOOM_UART_BASE
mrc p15, 0, \rv, c1, c0
tst \rv, #1 @ MMU enabled?

13
arch/arm/mach-omap2/include/mach/entry-macro.S
View File

@ -61,6 +61,14 @@
bne 9998f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
bne 9998f
/*
* ti816x has additional IRQ pending register. Checking this
* register on omap2 & omap3 has no effect (read as 0).
*/
ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
cmp \irqnr, #0x0
9998:
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
@ -133,6 +141,11 @@
bne 9999f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
#ifdef CONFIG_SOC_OMAPTI816X
bne 9999f
ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
cmp \irqnr, #0x0
#endif
9999:
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */

4
arch/arm/mach-omap2/include/mach/omap4-common.h
View File

@ -17,8 +17,12 @@
* wfi used in low power code. Directly opcode is used instead
* of instruction to avoid mulit-omap build break
*/
#ifdef CONFIG_THUMB2_KERNEL
#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
#else
#define do_wfi() \
__asm__ __volatile__ (".word 0xe320f003" : : : "memory")
#endif
#ifdef CONFIG_CACHE_L2X0
extern void __iomem *l2cache_base;

42
arch/arm/mach-omap2/io.c
View File

@ -30,7 +30,6 @@
#include <plat/sram.h>
#include <plat/sdrc.h>
#include <plat/gpmc.h>
#include <plat/serial.h>
#include "clock2xxx.h"
@ -66,7 +65,7 @@ static struct map_desc omap24xx_io_desc[] __initdata = {
},
};
#ifdef CONFIG_ARCH_OMAP2420
#ifdef CONFIG_SOC_OMAP2420
static struct map_desc omap242x_io_desc[] __initdata = {
{
.virtual = DSP_MEM_2420_VIRT,
@ -90,7 +89,7 @@ static struct map_desc omap242x_io_desc[] __initdata = {
#endif
#ifdef CONFIG_ARCH_OMAP2430
#ifdef CONFIG_SOC_OMAP2430
static struct map_desc omap243x_io_desc[] __initdata = {
{
.virtual = L4_WK_243X_VIRT,
@ -175,6 +174,18 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
#endif
};
#endif
#ifdef CONFIG_SOC_OMAPTI816X
static struct map_desc omapti816x_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
},
};
#endif
#ifdef CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
{
@ -241,7 +252,7 @@ static void __init _omap2_map_common_io(void)
omap_sram_init();
}
#ifdef CONFIG_ARCH_OMAP2420
#ifdef CONFIG_SOC_OMAP2420
void __init omap242x_map_common_io(void)
{
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
@ -250,7 +261,7 @@ void __init omap242x_map_common_io(void)
}
#endif
#ifdef CONFIG_ARCH_OMAP2430
#ifdef CONFIG_SOC_OMAP2430
void __init omap243x_map_common_io(void)
{
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
@ -267,6 +278,14 @@ void __init omap34xx_map_common_io(void)
}
#endif
#ifdef CONFIG_SOC_OMAPTI816X
void __init omapti816x_map_common_io(void)
{
iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
_omap2_map_common_io();
}
#endif
#ifdef CONFIG_ARCH_OMAP4
void __init omap44xx_map_common_io(void)
{
@ -337,15 +356,15 @@ void __init omap2_init_common_infrastructure(void)
if (cpu_is_omap242x()) {
omap2xxx_powerdomains_init();
omap2_clockdomains_init();
omap2xxx_clockdomains_init();
omap2420_hwmod_init();
} else if (cpu_is_omap243x()) {
omap2xxx_powerdomains_init();
omap2_clockdomains_init();
omap2xxx_clockdomains_init();
omap2430_hwmod_init();
} else if (cpu_is_omap34xx()) {
omap3xxx_powerdomains_init();
omap2_clockdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
} else if (cpu_is_omap44xx()) {
omap44xx_powerdomains_init();
@ -398,15 +417,10 @@ void __init omap2_init_common_infrastructure(void)
void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
omap_serial_early_init();
omap_hwmod_late_init();
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
if (cpu_is_omap24xx() || omap3_has_sdrc()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
gpmc_init();
omap_irq_base_init();
}

33
arch/arm/mach-omap2/iommu2.c
View File

@ -145,35 +145,32 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on)
static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
{
int i;
u32 stat, da;
const char *err_msg[] = {
"tlb miss",
"translation fault",
"emulation miss",
"table walk fault",
"multi hit fault",
};
u32 errs = 0;
stat = iommu_read_reg(obj, MMU_IRQSTATUS);
stat &= MMU_IRQ_MASK;
if (!stat)
if (!stat) {
*ra = 0;
return 0;
}
da = iommu_read_reg(obj, MMU_FAULT_AD);
*ra = da;
dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
if (stat & (1 << i))
printk("%s ", err_msg[i]);
}
printk("\n");
if (stat & MMU_IRQ_TLBMISS)
errs |= OMAP_IOMMU_ERR_TLB_MISS;
if (stat & MMU_IRQ_TRANSLATIONFAULT)
errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
if (stat & MMU_IRQ_EMUMISS)
errs |= OMAP_IOMMU_ERR_EMU_MISS;
if (stat & MMU_IRQ_TABLEWALKFAULT)
errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
if (stat & MMU_IRQ_MULTIHITFAULT)
errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
iommu_write_reg(obj, stat, MMU_IRQSTATUS);
return stat;
return errs;
}
static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)

9
arch/arm/mach-omap2/irq.c
View File

@ -61,8 +61,6 @@ struct omap3_intc_regs {
u32 mir[INTCPS_NR_MIR_REGS];
};
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
/* INTC bank register get/set */
static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
@ -110,7 +108,7 @@ static void omap_mask_irq(struct irq_data *d)
unsigned int irq = d->irq;
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
if (cpu_is_omap34xx()) {
if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
int spurious = 0;
/*
@ -205,6 +203,9 @@ void __init omap_init_irq(void)
BUG_ON(!base);
if (cpu_is_ti816x())
bank->nr_irqs = 128;
/* Static mapping, never released */
bank->base_reg = ioremap(base, SZ_4K);
if (!bank->base_reg) {
@ -229,6 +230,8 @@ void __init omap_init_irq(void)
}
#ifdef CONFIG_ARCH_OMAP3
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
void omap_intc_save_context(void)
{
int ind = 0, i = 0;

74
arch/arm/mach-omap2/mailbox.c
View File

@ -14,12 +14,11 @@
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <plat/mailbox.h>
#include <mach/irqs.h>
#define MAILBOX_REVISION 0x000
#define MAILBOX_SYSCONFIG 0x010
#define MAILBOX_SYSSTATUS 0x014
#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
@ -33,17 +32,6 @@
#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
/* SYSCONFIG: register bit definition */
#define AUTOIDLE (1 << 0)
#define SOFTRESET (1 << 1)
#define SMARTIDLE (2 << 3)
#define OMAP4_SOFTRESET (1 << 0)
#define OMAP4_NOIDLE (1 << 2)
#define OMAP4_SMARTIDLE (2 << 2)
/* SYSSTATUS: register bit definition */
#define RESETDONE (1 << 0)
#define MBOX_REG_SIZE 0x120
#define OMAP4_MBOX_REG_SIZE 0x130
@ -70,8 +58,6 @@ struct omap_mbox2_priv {
unsigned long irqdisable;
};
static struct clk *mbox_ick_handle;
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
@ -89,53 +75,13 @@ static inline void mbox_write_reg(u32 val, size_t ofs)
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
u32 l;
unsigned long timeout;
mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
if (IS_ERR(mbox_ick_handle)) {
printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
PTR_ERR(mbox_ick_handle));
return PTR_ERR(mbox_ick_handle);
}
clk_enable(mbox_ick_handle);
if (cpu_is_omap44xx()) {
mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
timeout = jiffies + msecs_to_jiffies(20);
do {
l = mbox_read_reg(MAILBOX_SYSCONFIG);
if (!(l & OMAP4_SOFTRESET))
break;
} while (!time_after(jiffies, timeout));
if (l & OMAP4_SOFTRESET) {
pr_err("Can't take mailbox out of reset\n");
return -ENODEV;
}
} else {
mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
timeout = jiffies + msecs_to_jiffies(20);
do {
l = mbox_read_reg(MAILBOX_SYSSTATUS);
if (l & RESETDONE)
break;
} while (!time_after(jiffies, timeout));
if (!(l & RESETDONE)) {
pr_err("Can't take mailbox out of reset\n");
return -ENODEV;
}
}
pm_runtime_enable(mbox->dev->parent);
pm_runtime_get_sync(mbox->dev->parent);
l = mbox_read_reg(MAILBOX_REVISION);
pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
if (cpu_is_omap44xx())
l = OMAP4_SMARTIDLE;
else
l = SMARTIDLE | AUTOIDLE;
mbox_write_reg(l, MAILBOX_SYSCONFIG);
omap2_mbox_enable_irq(mbox, IRQ_RX);
return 0;
@ -143,9 +89,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
clk_disable(mbox_ick_handle);
clk_put(mbox_ick_handle);
mbox_ick_handle = NULL;
pm_runtime_put_sync(mbox->dev->parent);
pm_runtime_disable(mbox->dev->parent);
}
/* Mailbox FIFO handle functions */
@ -312,7 +257,7 @@ struct omap_mbox mbox_dsp_info = {
struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
#endif
#if defined(CONFIG_ARCH_OMAP2420)
#if defined(CONFIG_SOC_OMAP2420)
/* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
.tx_fifo = {
@ -400,14 +345,14 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
else if (cpu_is_omap34xx()) {
list = omap3_mboxes;
list[0]->irq = platform_get_irq_byname(pdev, "dsp");
list[0]->irq = platform_get_irq(pdev, 0);
}
#endif
#if defined(CONFIG_ARCH_OMAP2)
else if (cpu_is_omap2430()) {
list = omap2_mboxes;
list[0]->irq = platform_get_irq_byname(pdev, "dsp");
list[0]->irq = platform_get_irq(pdev, 0);
} else if (cpu_is_omap2420()) {
list = omap2_mboxes;
@ -419,8 +364,7 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
else if (cpu_is_omap44xx()) {
list = omap4_mboxes;
list[0]->irq = list[1]->irq =
platform_get_irq_byname(pdev, "mbox");
list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
}
#endif
else {

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