MIPS: uasm: Add div, mul and sel instructions for mipsr6
Add the following instructions for use by eBPF on mipsr6: insn_ddivu_r6, insn_divu_r6, insn_dmodu, insn_dmulu, insn_modu, insn_mulu, insn_seleqz, insn_selnez Signed-off-by: Hassan Naveed <hnaveed@wavecomp.com> Reviewed-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: kafai@fb.com Cc: songliubraving@fb.com Cc: yhs@fb.com Cc: netdev@vger.kernel.org Cc: bpf@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Alexei Starovoitov <ast@kernel.org> Cc: Daniel Borkmann <daniel@iogearbox.net> Cc: open list:MIPS <linux-mips@linux-mips.org> Cc: open list <linux-kernel@vger.kernel.org>
This commit is contained in:
Hassan Naveed
Paul Burton
parent
b8f3b15a7b
commit
0d1d17b9ff
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@ -86,14 +86,18 @@ Ip_u2u1(_ctcmsa);
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Ip_u2u1s3(_daddiu);
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Ip_u3u1u2(_daddu);
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Ip_u1u2(_ddivu);
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Ip_u3u1u2(_ddivu_r6);
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Ip_u1(_di);
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Ip_u2u1msbu3(_dins);
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Ip_u2u1msbu3(_dinsm);
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Ip_u2u1msbu3(_dinsu);
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Ip_u1u2(_divu);
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Ip_u3u1u2(_divu_r6);
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Ip_u1u2u3(_dmfc0);
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Ip_u3u1u2(_dmodu);
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Ip_u1u2u3(_dmtc0);
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Ip_u1u2(_dmultu);
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Ip_u3u1u2(_dmulu);
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Ip_u2u1u3(_drotr);
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Ip_u2u1u3(_drotr32);
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Ip_u2u1(_dsbh);
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@ -131,6 +135,7 @@ Ip_u1u2u3(_mfc0);
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Ip_u1u2u3(_mfhc0);
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Ip_u1(_mfhi);
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Ip_u1(_mflo);
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Ip_u3u1u2(_modu);
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Ip_u3u1u2(_movn);
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Ip_u3u1u2(_movz);
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Ip_u1u2u3(_mtc0);
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@ -139,6 +144,7 @@ Ip_u1(_mthi);
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Ip_u1(_mtlo);
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Ip_u3u1u2(_mul);
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Ip_u1u2(_multu);
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Ip_u3u1u2(_mulu);
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Ip_u3u1u2(_nor);
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Ip_u3u1u2(_or);
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Ip_u2u1u3(_ori);
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@ -149,6 +155,8 @@ Ip_u2s3u1(_sb);
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Ip_u2s3u1(_sc);
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Ip_u2s3u1(_scd);
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Ip_u2s3u1(_sd);
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Ip_u3u1u2(_seleqz);
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Ip_u3u1u2(_selnez);
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Ip_u2s3u1(_sh);
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Ip_u2u1u3(_sll);
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Ip_u3u2u1(_sllv);
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@ -55,9 +55,9 @@ enum spec_op {
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spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
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dadd_op, daddu_op, dsub_op, dsubu_op,
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tge_op, tgeu_op, tlt_op, tltu_op,
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teq_op, spec5_unused_op, tne_op, spec6_unused_op,
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dsll_op, spec7_unused_op, dsrl_op, dsra_op,
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dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
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teq_op, seleqz_op, tne_op, selnez_op,
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dsll_op, spec5_unused_op, dsrl_op, dsra_op,
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dsll32_op, spec6_unused_op, dsrl32_op, dsra32_op
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};
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/*
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@ -76,14 +76,22 @@ static const struct insn insn_table[insn_invalid] = {
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[insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
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[insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
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[insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},
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[insn_ddivu_r6] = {M(spec_op, 0, 0, 0, ddivu_ddivu6_op, ddivu_op),
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RS | RT | RD},
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[insn_di] = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT},
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[insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
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[insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
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[insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
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[insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},
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[insn_divu_r6] = {M(spec_op, 0, 0, 0, divu_divu6_op, divu_op),
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RS | RT | RD},
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[insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
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[insn_dmodu] = {M(spec_op, 0, 0, 0, ddivu_dmodu_op, ddivu_op),
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RS | RT | RD},
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[insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
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[insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
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[insn_dmulu] = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op),
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RS | RT | RD},
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[insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
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[insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
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[insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD},
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@ -132,12 +140,16 @@ static const struct insn insn_table[insn_invalid] = {
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[insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET},
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[insn_mfhi] = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD},
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[insn_mflo] = {M(spec_op, 0, 0, 0, 0, mflo_op), RD},
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[insn_modu] = {M(spec_op, 0, 0, 0, divu_modu_op, divu_op),
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RS | RT | RD},
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[insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},
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[insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},
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[insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
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[insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET},
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[insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS},
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[insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
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[insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),
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RS | RT | RD},
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#ifndef CONFIG_CPU_MIPSR6
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[insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
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#else
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@ -163,6 +175,8 @@ static const struct insn insn_table[insn_invalid] = {
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[insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9},
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#endif
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[insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
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[insn_seleqz] = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD},
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[insn_selnez] = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD},
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[insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
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[insn_sll] = {M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE},
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[insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD},
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@ -50,21 +50,22 @@ enum opcode {
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insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
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insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
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insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
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insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, insn_dmfc0,
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insn_dmtc0, insn_dmultu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd,
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insn_dsll, insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav,
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insn_dsrl, insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext,
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insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu,
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insn_ld, insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu,
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insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0,
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insn_mfhc0, insn_mfhi, insn_mflo, insn_movn, insn_movz, insn_mtc0,
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insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,
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insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,
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insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,
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insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srav,
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insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
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insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
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insn_xor, insn_xori, insn_yield,
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insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu,
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insn_divu_r6, insn_dmfc0, insn_dmodu, insn_dmtc0, insn_dmultu,
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insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll,
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insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl,
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insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins,
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insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld,
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insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,
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insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,
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insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,
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insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor,
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insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,
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insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,
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insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
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insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,
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insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,
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insn_wsbh, insn_xor, insn_xori, insn_yield,
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insn_invalid /* insn_invalid must be last */
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};
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@ -287,13 +288,17 @@ I_u2u1(_cfcmsa)
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I_u1u2(_ctc1)
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I_u2u1(_ctcmsa)
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I_u1u2(_ddivu)
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I_u3u1u2(_ddivu_r6)
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I_u1u2u3(_dmfc0)
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I_u3u1u2(_dmodu)
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I_u1u2u3(_dmtc0)
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I_u1u2(_dmultu)
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I_u3u1u2(_dmulu)
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I_u2u1s3(_daddiu)
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I_u3u1u2(_daddu)
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I_u1(_di);
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I_u1u2(_divu)
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I_u3u1u2(_divu_r6)
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I_u2u1(_dsbh);
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I_u2u1(_dshd);
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I_u2u1u3(_dsll)
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@ -327,6 +332,7 @@ I_u2s3u1(_lw)
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I_u2s3u1(_lwu)
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I_u1u2u3(_mfc0)
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I_u1u2u3(_mfhc0)
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I_u3u1u2(_modu)
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I_u3u1u2(_movn)
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I_u3u1u2(_movz)
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I_u1(_mfhi)
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@ -337,6 +343,7 @@ I_u1(_mthi)
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I_u1(_mtlo)
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I_u3u1u2(_mul)
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I_u1u2(_multu)
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I_u3u1u2(_mulu)
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I_u3u1u2(_nor)
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I_u3u1u2(_or)
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I_u2u1u3(_ori)
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@ -345,6 +352,8 @@ I_u2s3u1(_sb)
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I_u2s3u1(_sc)
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I_u2s3u1(_scd)
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I_u2s3u1(_sd)
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I_u3u1u2(_seleqz)
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I_u3u1u2(_selnez)
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I_u2s3u1(_sh)
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I_u2u1u3(_sll)
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I_u3u2u1(_sllv)
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