[PATCH] ppc32 8xx: Added setbitsXX/clrbitsXX macro for read-modify-write operations
This adds setbitsXX/clrbitsXX macro for read-modify-write operations and converts the 8xx core and drivers to use them. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -73,7 +73,7 @@ cpm_mask_irq(unsigned int irq)
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{
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int cpm_vec = irq - CPM_IRQ_OFFSET;
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out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr) & ~(1 << cpm_vec));
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clrbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, (1 << cpm_vec));
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}
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static void
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@ -81,7 +81,7 @@ cpm_unmask_irq(unsigned int irq)
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{
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int cpm_vec = irq - CPM_IRQ_OFFSET;
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out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr) | (1 << cpm_vec));
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setbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, (1 << cpm_vec));
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}
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static void
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@ -198,7 +198,7 @@ cpm_interrupt_init(void)
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if (setup_irq(CPM_IRQ_OFFSET + CPMVEC_ERROR, &cpm_error_irqaction))
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panic("Could not allocate CPM error IRQ!");
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out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr) | CICR_IEN);
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setbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, CICR_IEN);
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}
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/*
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@ -140,9 +140,11 @@ void __init __attribute__ ((weak))
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init_internal_rtc(void)
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{
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/* Disable the RTC one second and alarm interrupts. */
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out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) & ~(RTCSC_SIE | RTCSC_ALE));
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clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
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/* Enable the RTC */
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out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) | (RTCSC_RTF | RTCSC_RTE));
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setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
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}
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/* The decrementer counts at the system (internal) clock frequency divided by
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@ -159,8 +161,7 @@ void __init m8xx_calibrate_decr(void)
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out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
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/* Force all 8xx processors to use divide by 16 processor clock. */
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out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr,
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in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr)|0x02000000);
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setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000);
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/* Processor frequency is MHz.
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* The value 'fp' is the number of decrementer ticks per second.
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*/
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@ -239,8 +240,8 @@ m8xx_restart(char *cmd)
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__volatile__ unsigned char dummy;
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local_irq_disable();
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out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr) | 0x00000080);
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setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080);
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/* Clear the ME bit in MSR to cause checkstop on machine check
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*/
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mtmsr(mfmsr() & ~0x1000);
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@ -310,8 +311,8 @@ m8xx_init_IRQ(void)
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i8259_init(0);
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/* The i8259 cascade interrupt must be level sensitive. */
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out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel & ~(0x80000000 >> ISA_BRIDGE_INT)));
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clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT));
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if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
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enable_irq(ISA_BRIDGE_INT);
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#endif /* CONFIG_PCI */
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@ -41,8 +41,7 @@ static irqreturn_t m8xx_wdt_interrupt(int irq, void *dev, struct pt_regs *regs)
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m8xx_wdt_reset();
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out_be16(&imap->im_sit.sit_piscr, in_be16(&imap->im_sit.sit_piscr) | PISCR_PS); /* clear irq */
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setbits16(&imap->im_sit.sit_piscr, PISCR_PS);
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return IRQ_HANDLED;
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}
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@ -575,4 +575,11 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
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*/
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#define xlate_dev_kmem_ptr(p) p
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/* access ports */
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#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
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#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
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#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
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#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
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#endif /* __KERNEL__ */
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