i2c-i801: Handle multiple instances instead of keeping global state
It's poor form to keep driver state in global variables rather than per-instance. It never really mattered in practice when there was only one controller on the chipset, but the latest chipsets do have more than one controller, so now we care. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
This commit is contained in:
David Woodhouse
Jean Delvare
parent
e30d9859cf
commit
0cd96eb0a7
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@ -3,6 +3,8 @@
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Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
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<mdsxyz123@yahoo.com>
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Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
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Copyright (C) 2010 Intel Corporation,
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David Woodhouse <dwmw2@infradead.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -55,8 +57,6 @@
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See the file Documentation/i2c/busses/i2c-i801 for details.
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*/
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/* Note: we assume there can only be one I801, with one SMBus interface */
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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@ -70,16 +70,16 @@
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#include <linux/dmi.h>
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/* I801 SMBus address offsets */
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#define SMBHSTSTS (0 + i801_smba)
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#define SMBHSTCNT (2 + i801_smba)
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#define SMBHSTCMD (3 + i801_smba)
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#define SMBHSTADD (4 + i801_smba)
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#define SMBHSTDAT0 (5 + i801_smba)
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#define SMBHSTDAT1 (6 + i801_smba)
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#define SMBBLKDAT (7 + i801_smba)
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#define SMBPEC (8 + i801_smba) /* ICH3 and later */
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#define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
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#define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
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#define SMBHSTSTS(p) (0 + (p)->smba)
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#define SMBHSTCNT(p) (2 + (p)->smba)
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#define SMBHSTCMD(p) (3 + (p)->smba)
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#define SMBHSTADD(p) (4 + (p)->smba)
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#define SMBHSTDAT0(p) (5 + (p)->smba)
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#define SMBHSTDAT1(p) (6 + (p)->smba)
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#define SMBBLKDAT(p) (7 + (p)->smba)
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#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
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#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
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#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
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/* PCI Address Constants */
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#define SMBBAR 4
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@ -128,16 +128,20 @@
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SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
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SMBHSTSTS_INTR)
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static unsigned long i801_smba;
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static unsigned char i801_original_hstcfg;
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struct i801_priv {
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struct i2c_adapter adapter;
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unsigned long smba;
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unsigned char original_hstcfg;
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struct pci_dev *pci_dev;
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unsigned int features;
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};
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static struct pci_driver i801_driver;
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static struct pci_dev *I801_dev;
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#define FEATURE_SMBUS_PEC (1 << 0)
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#define FEATURE_BLOCK_BUFFER (1 << 1)
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#define FEATURE_BLOCK_PROC (1 << 2)
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#define FEATURE_I2C_BLOCK_READ (1 << 3)
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static unsigned int i801_features;
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static const char *i801_feature_names[] = {
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"SMBus PEC",
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@ -152,24 +156,24 @@ MODULE_PARM_DESC(disable_features, "Disable selected driver features");
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/* Make sure the SMBus host is ready to start transmitting.
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Return 0 if it is, -EBUSY if it is not. */
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static int i801_check_pre(void)
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static int i801_check_pre(struct i801_priv *priv)
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{
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int status;
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status = inb_p(SMBHSTSTS);
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status = inb_p(SMBHSTSTS(priv));
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if (status & SMBHSTSTS_HOST_BUSY) {
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dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n");
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dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
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return -EBUSY;
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}
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status &= STATUS_FLAGS;
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if (status) {
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dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n",
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dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
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status);
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outb_p(status, SMBHSTSTS);
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status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
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outb_p(status, SMBHSTSTS(priv));
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status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
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if (status) {
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dev_err(&I801_dev->dev,
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dev_err(&priv->pci_dev->dev,
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"Failed clearing status flags (%02x)\n",
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status);
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return -EBUSY;
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@ -180,48 +184,50 @@ static int i801_check_pre(void)
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}
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/* Convert the status register to an error code, and clear it. */
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static int i801_check_post(int status, int timeout)
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static int i801_check_post(struct i801_priv *priv, int status, int timeout)
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{
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int result = 0;
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/* If the SMBus is still busy, we give up */
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if (timeout) {
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dev_err(&I801_dev->dev, "Transaction timeout\n");
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dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
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/* try to stop the current command */
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dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
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outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
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dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
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outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
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SMBHSTCNT(priv));
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msleep(1);
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outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
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outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
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SMBHSTCNT(priv));
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/* Check if it worked */
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status = inb_p(SMBHSTSTS);
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status = inb_p(SMBHSTSTS(priv));
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if ((status & SMBHSTSTS_HOST_BUSY) ||
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!(status & SMBHSTSTS_FAILED))
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dev_err(&I801_dev->dev,
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dev_err(&priv->pci_dev->dev,
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"Failed terminating the transaction\n");
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outb_p(STATUS_FLAGS, SMBHSTSTS);
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outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
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return -ETIMEDOUT;
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}
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if (status & SMBHSTSTS_FAILED) {
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result = -EIO;
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dev_err(&I801_dev->dev, "Transaction failed\n");
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dev_err(&priv->pci_dev->dev, "Transaction failed\n");
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}
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if (status & SMBHSTSTS_DEV_ERR) {
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result = -ENXIO;
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dev_dbg(&I801_dev->dev, "No response\n");
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dev_dbg(&priv->pci_dev->dev, "No response\n");
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}
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if (status & SMBHSTSTS_BUS_ERR) {
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result = -EAGAIN;
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dev_dbg(&I801_dev->dev, "Lost arbitration\n");
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dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
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}
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if (result) {
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/* Clear error flags */
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outb_p(status & STATUS_FLAGS, SMBHSTSTS);
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status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
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outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
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status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
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if (status) {
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dev_warn(&I801_dev->dev, "Failed clearing status "
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dev_warn(&priv->pci_dev->dev, "Failed clearing status "
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"flags at end of transaction (%02x)\n",
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status);
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}
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@ -230,86 +236,88 @@ static int i801_check_post(int status, int timeout)
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return result;
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}
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static int i801_transaction(int xact)
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static int i801_transaction(struct i801_priv *priv, int xact)
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{
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int status;
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int result;
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int timeout = 0;
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result = i801_check_pre();
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result = i801_check_pre(priv);
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if (result < 0)
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return result;
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/* the current contents of SMBHSTCNT can be overwritten, since PEC,
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* INTREN, SMBSCMD are passed in xact */
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outb_p(xact | I801_START, SMBHSTCNT);
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outb_p(xact | I801_START, SMBHSTCNT(priv));
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/* We will always wait for a fraction of a second! */
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do {
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msleep(1);
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status = inb_p(SMBHSTSTS);
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status = inb_p(SMBHSTSTS(priv));
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} while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
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result = i801_check_post(status, timeout > MAX_TIMEOUT);
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result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
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if (result < 0)
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return result;
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outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
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outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
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return 0;
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}
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/* wait for INTR bit as advised by Intel */
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static void i801_wait_hwpec(void)
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static void i801_wait_hwpec(struct i801_priv *priv)
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{
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int timeout = 0;
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int status;
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do {
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msleep(1);
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status = inb_p(SMBHSTSTS);
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status = inb_p(SMBHSTSTS(priv));
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} while ((!(status & SMBHSTSTS_INTR))
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&& (timeout++ < MAX_TIMEOUT));
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if (timeout > MAX_TIMEOUT)
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dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
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dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
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outb_p(status, SMBHSTSTS);
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outb_p(status, SMBHSTSTS(priv));
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}
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static int i801_block_transaction_by_block(union i2c_smbus_data *data,
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static int i801_block_transaction_by_block(struct i801_priv *priv,
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union i2c_smbus_data *data,
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char read_write, int hwpec)
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{
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int i, len;
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int status;
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inb_p(SMBHSTCNT); /* reset the data buffer index */
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inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
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/* Use 32-byte buffer to process this transaction */
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if (read_write == I2C_SMBUS_WRITE) {
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len = data->block[0];
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outb_p(len, SMBHSTDAT0);
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outb_p(len, SMBHSTDAT0(priv));
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for (i = 0; i < len; i++)
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outb_p(data->block[i+1], SMBBLKDAT);
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outb_p(data->block[i+1], SMBBLKDAT(priv));
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}
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status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
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status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
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I801_PEC_EN * hwpec);
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if (status)
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return status;
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if (read_write == I2C_SMBUS_READ) {
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len = inb_p(SMBHSTDAT0);
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len = inb_p(SMBHSTDAT0(priv));
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if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
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return -EPROTO;
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data->block[0] = len;
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for (i = 0; i < len; i++)
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data->block[i + 1] = inb_p(SMBBLKDAT);
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data->block[i + 1] = inb_p(SMBBLKDAT(priv));
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}
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return 0;
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}
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static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
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static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
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union i2c_smbus_data *data,
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char read_write, int command,
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int hwpec)
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{
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@ -319,15 +327,15 @@ static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
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int result;
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int timeout;
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result = i801_check_pre();
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result = i801_check_pre(priv);
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if (result < 0)
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return result;
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len = data->block[0];
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if (read_write == I2C_SMBUS_WRITE) {
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outb_p(len, SMBHSTDAT0);
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outb_p(data->block[1], SMBBLKDAT);
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outb_p(len, SMBHSTDAT0(priv));
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outb_p(data->block[1], SMBBLKDAT(priv));
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}
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for (i = 1; i <= len; i++) {
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@ -343,34 +351,37 @@ static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
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else
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smbcmd = I801_BLOCK_DATA;
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}
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outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
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outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
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if (i == 1)
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outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
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outb_p(inb(SMBHSTCNT(priv)) | I801_START,
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SMBHSTCNT(priv));
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/* We will always wait for a fraction of a second! */
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timeout = 0;
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do {
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msleep(1);
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status = inb_p(SMBHSTSTS);
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status = inb_p(SMBHSTSTS(priv));
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} while ((!(status & SMBHSTSTS_BYTE_DONE))
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&& (timeout++ < MAX_TIMEOUT));
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result = i801_check_post(status, timeout > MAX_TIMEOUT);
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result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
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if (result < 0)
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return result;
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if (i == 1 && read_write == I2C_SMBUS_READ
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&& command != I2C_SMBUS_I2C_BLOCK_DATA) {
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len = inb_p(SMBHSTDAT0);
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len = inb_p(SMBHSTDAT0(priv));
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if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
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dev_err(&I801_dev->dev,
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dev_err(&priv->pci_dev->dev,
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"Illegal SMBus block read size %d\n",
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len);
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/* Recover */
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while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
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outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS);
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outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
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while (inb_p(SMBHSTSTS(priv)) &
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SMBHSTSTS_HOST_BUSY)
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outb_p(SMBHSTSTS_BYTE_DONE,
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SMBHSTSTS(priv));
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outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
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return -EPROTO;
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}
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data->block[0] = len;
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@ -378,27 +389,28 @@ static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
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/* Retrieve/store value in SMBBLKDAT */
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if (read_write == I2C_SMBUS_READ)
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data->block[i] = inb_p(SMBBLKDAT);
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data->block[i] = inb_p(SMBBLKDAT(priv));
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if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
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outb_p(data->block[i+1], SMBBLKDAT);
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outb_p(data->block[i+1], SMBBLKDAT(priv));
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/* signals SMBBLKDAT ready */
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outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS);
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outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
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}
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return 0;
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}
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static int i801_set_block_buffer_mode(void)
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static int i801_set_block_buffer_mode(struct i801_priv *priv)
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{
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outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
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if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
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outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
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if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
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return -EIO;
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return 0;
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}
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/* Block transaction function */
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static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
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static int i801_block_transaction(struct i801_priv *priv,
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union i2c_smbus_data *data, char read_write,
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int command, int hwpec)
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{
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int result = 0;
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@ -407,11 +419,11 @@ static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
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if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
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if (read_write == I2C_SMBUS_WRITE) {
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/* set I2C_EN bit in configuration register */
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pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
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pci_write_config_byte(I801_dev, SMBHSTCFG,
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pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
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pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
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hostc | SMBHSTCFG_I2C_EN);
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} else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
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dev_err(&I801_dev->dev,
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} else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
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dev_err(&priv->pci_dev->dev,
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"I2C block read is unsupported!\n");
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return -EOPNOTSUPP;
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}
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@ -430,22 +442,23 @@ static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
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/* Experience has shown that the block buffer can only be used for
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SMBus (not I2C) block transactions, even though the datasheet
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doesn't mention this limitation. */
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if ((i801_features & FEATURE_BLOCK_BUFFER)
|
||||
if ((priv->features & FEATURE_BLOCK_BUFFER)
|
||||
&& command != I2C_SMBUS_I2C_BLOCK_DATA
|
||||
&& i801_set_block_buffer_mode() == 0)
|
||||
result = i801_block_transaction_by_block(data, read_write,
|
||||
hwpec);
|
||||
&& i801_set_block_buffer_mode(priv) == 0)
|
||||
result = i801_block_transaction_by_block(priv, data,
|
||||
read_write, hwpec);
|
||||
else
|
||||
result = i801_block_transaction_byte_by_byte(data, read_write,
|
||||
result = i801_block_transaction_byte_by_byte(priv, data,
|
||||
read_write,
|
||||
command, hwpec);
|
||||
|
||||
if (result == 0 && hwpec)
|
||||
i801_wait_hwpec();
|
||||
i801_wait_hwpec(priv);
|
||||
|
||||
if (command == I2C_SMBUS_I2C_BLOCK_DATA
|
||||
&& read_write == I2C_SMBUS_WRITE) {
|
||||
/* restore saved configuration register value */
|
||||
pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
|
||||
pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
|
@ -458,81 +471,85 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr,
|
|||
int hwpec;
|
||||
int block = 0;
|
||||
int ret, xact = 0;
|
||||
struct i801_priv *priv = i2c_get_adapdata(adap);
|
||||
|
||||
hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
|
||||
hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
|
||||
&& size != I2C_SMBUS_QUICK
|
||||
&& size != I2C_SMBUS_I2C_BLOCK_DATA;
|
||||
|
||||
switch (size) {
|
||||
case I2C_SMBUS_QUICK:
|
||||
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
|
||||
SMBHSTADD);
|
||||
SMBHSTADD(priv));
|
||||
xact = I801_QUICK;
|
||||
break;
|
||||
case I2C_SMBUS_BYTE:
|
||||
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
|
||||
SMBHSTADD);
|
||||
SMBHSTADD(priv));
|
||||
if (read_write == I2C_SMBUS_WRITE)
|
||||
outb_p(command, SMBHSTCMD);
|
||||
outb_p(command, SMBHSTCMD(priv));
|
||||
xact = I801_BYTE;
|
||||
break;
|
||||
case I2C_SMBUS_BYTE_DATA:
|
||||
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
|
||||
SMBHSTADD);
|
||||
outb_p(command, SMBHSTCMD);
|
||||
SMBHSTADD(priv));
|
||||
outb_p(command, SMBHSTCMD(priv));
|
||||
if (read_write == I2C_SMBUS_WRITE)
|
||||
outb_p(data->byte, SMBHSTDAT0);
|
||||
outb_p(data->byte, SMBHSTDAT0(priv));
|
||||
xact = I801_BYTE_DATA;
|
||||
break;
|
||||
case I2C_SMBUS_WORD_DATA:
|
||||
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
|
||||
SMBHSTADD);
|
||||
outb_p(command, SMBHSTCMD);
|
||||
SMBHSTADD(priv));
|
||||
outb_p(command, SMBHSTCMD(priv));
|
||||
if (read_write == I2C_SMBUS_WRITE) {
|
||||
outb_p(data->word & 0xff, SMBHSTDAT0);
|
||||
outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
|
||||
outb_p(data->word & 0xff, SMBHSTDAT0(priv));
|
||||
outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
|
||||
}
|
||||
xact = I801_WORD_DATA;
|
||||
break;
|
||||
case I2C_SMBUS_BLOCK_DATA:
|
||||
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
|
||||
SMBHSTADD);
|
||||
outb_p(command, SMBHSTCMD);
|
||||
SMBHSTADD(priv));
|
||||
outb_p(command, SMBHSTCMD(priv));
|
||||
block = 1;
|
||||
break;
|
||||
case I2C_SMBUS_I2C_BLOCK_DATA:
|
||||
/* NB: page 240 of ICH5 datasheet shows that the R/#W
|
||||
* bit should be cleared here, even when reading */
|
||||
outb_p((addr & 0x7f) << 1, SMBHSTADD);
|
||||
outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
|
||||
if (read_write == I2C_SMBUS_READ) {
|
||||
/* NB: page 240 of ICH5 datasheet also shows
|
||||
* that DATA1 is the cmd field when reading */
|
||||
outb_p(command, SMBHSTDAT1);
|
||||
outb_p(command, SMBHSTDAT1(priv));
|
||||
} else
|
||||
outb_p(command, SMBHSTCMD);
|
||||
outb_p(command, SMBHSTCMD(priv));
|
||||
block = 1;
|
||||
break;
|
||||
default:
|
||||
dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
|
||||
dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
|
||||
size);
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
if (hwpec) /* enable/disable hardware PEC */
|
||||
outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
|
||||
outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
|
||||
else
|
||||
outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
|
||||
outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
|
||||
SMBAUXCTL(priv));
|
||||
|
||||
if (block)
|
||||
ret = i801_block_transaction(data, read_write, size, hwpec);
|
||||
ret = i801_block_transaction(priv, data, read_write, size,
|
||||
hwpec);
|
||||
else
|
||||
ret = i801_transaction(xact | ENABLE_INT9);
|
||||
ret = i801_transaction(priv, xact | ENABLE_INT9);
|
||||
|
||||
/* Some BIOSes don't like it when PEC is enabled at reboot or resume
|
||||
time, so we forcibly disable it after every transaction. Turn off
|
||||
E32B for the same reason. */
|
||||
if (hwpec || block)
|
||||
outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
|
||||
SMBAUXCTL);
|
||||
outb_p(inb_p(SMBAUXCTL(priv)) &
|
||||
~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
|
||||
|
||||
if (block)
|
||||
return ret;
|
||||
|
|
@ -544,10 +561,11 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr,
|
|||
switch (xact & 0x7f) {
|
||||
case I801_BYTE: /* Result put in SMBHSTDAT0 */
|
||||
case I801_BYTE_DATA:
|
||||
data->byte = inb_p(SMBHSTDAT0);
|
||||
data->byte = inb_p(SMBHSTDAT0(priv));
|
||||
break;
|
||||
case I801_WORD_DATA:
|
||||
data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
|
||||
data->word = inb_p(SMBHSTDAT0(priv)) +
|
||||
(inb_p(SMBHSTDAT1(priv)) << 8);
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -556,11 +574,13 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr,
|
|||
|
||||
static u32 i801_func(struct i2c_adapter *adapter)
|
||||
{
|
||||
struct i801_priv *priv = i2c_get_adapdata(adapter);
|
||||
|
||||
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
|
||||
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
|
||||
I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
|
||||
((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
|
||||
((i801_features & FEATURE_I2C_BLOCK_READ) ?
|
||||
((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
|
||||
((priv->features & FEATURE_I2C_BLOCK_READ) ?
|
||||
I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
|
||||
}
|
||||
|
||||
|
|
@ -569,12 +589,6 @@ static const struct i2c_algorithm smbus_algorithm = {
|
|||
.functionality = i801_func,
|
||||
};
|
||||
|
||||
static struct i2c_adapter i801_adapter = {
|
||||
.owner = THIS_MODULE,
|
||||
.class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
|
||||
.algo = &smbus_algorithm,
|
||||
};
|
||||
|
||||
static const struct pci_device_id i801_ids[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
|
||||
|
|
@ -706,16 +720,25 @@ static int __devinit i801_probe(struct pci_dev *dev,
|
|||
{
|
||||
unsigned char temp;
|
||||
int err, i;
|
||||
struct i801_priv *priv;
|
||||
|
||||
I801_dev = dev;
|
||||
i801_features = 0;
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
i2c_set_adapdata(&priv->adapter, priv);
|
||||
priv->adapter.owner = THIS_MODULE;
|
||||
priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
||||
priv->adapter.algo = &smbus_algorithm;
|
||||
|
||||
priv->pci_dev = dev;
|
||||
switch (dev->device) {
|
||||
default:
|
||||
i801_features |= FEATURE_I2C_BLOCK_READ;
|
||||
priv->features |= FEATURE_I2C_BLOCK_READ;
|
||||
/* fall through */
|
||||
case PCI_DEVICE_ID_INTEL_82801DB_3:
|
||||
i801_features |= FEATURE_SMBUS_PEC;
|
||||
i801_features |= FEATURE_BLOCK_BUFFER;
|
||||
priv->features |= FEATURE_SMBUS_PEC;
|
||||
priv->features |= FEATURE_BLOCK_BUFFER;
|
||||
/* fall through */
|
||||
case PCI_DEVICE_ID_INTEL_82801CA_3:
|
||||
case PCI_DEVICE_ID_INTEL_82801BA_2:
|
||||
|
|
@ -726,11 +749,11 @@ static int __devinit i801_probe(struct pci_dev *dev,
|
|||
|
||||
/* Disable features on user request */
|
||||
for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
|
||||
if (i801_features & disable_features & (1 << i))
|
||||
if (priv->features & disable_features & (1 << i))
|
||||
dev_notice(&dev->dev, "%s disabled by user\n",
|
||||
i801_feature_names[i]);
|
||||
}
|
||||
i801_features &= ~disable_features;
|
||||
priv->features &= ~disable_features;
|
||||
|
||||
err = pci_enable_device(dev);
|
||||
if (err) {
|
||||
|
|
@ -740,8 +763,8 @@ static int __devinit i801_probe(struct pci_dev *dev,
|
|||
}
|
||||
|
||||
/* Determine the address of the SMBus area */
|
||||
i801_smba = pci_resource_start(dev, SMBBAR);
|
||||
if (!i801_smba) {
|
||||
priv->smba = pci_resource_start(dev, SMBBAR);
|
||||
if (!priv->smba) {
|
||||
dev_err(&dev->dev, "SMBus base address uninitialized, "
|
||||
"upgrade BIOS\n");
|
||||
err = -ENODEV;
|
||||
|
|
@ -757,19 +780,19 @@ static int __devinit i801_probe(struct pci_dev *dev,
|
|||
err = pci_request_region(dev, SMBBAR, i801_driver.name);
|
||||
if (err) {
|
||||
dev_err(&dev->dev, "Failed to request SMBus region "
|
||||
"0x%lx-0x%Lx\n", i801_smba,
|
||||
"0x%lx-0x%Lx\n", priv->smba,
|
||||
(unsigned long long)pci_resource_end(dev, SMBBAR));
|
||||
goto exit;
|
||||
}
|
||||
|
||||
pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
|
||||
i801_original_hstcfg = temp;
|
||||
pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
|
||||
priv->original_hstcfg = temp;
|
||||
temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
|
||||
if (!(temp & SMBHSTCFG_HST_EN)) {
|
||||
dev_info(&dev->dev, "Enabling SMBus device\n");
|
||||
temp |= SMBHSTCFG_HST_EN;
|
||||
}
|
||||
pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
|
||||
pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
|
||||
|
||||
if (temp & SMBHSTCFG_SMB_SMI_EN)
|
||||
dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
|
||||
|
|
@ -777,19 +800,19 @@ static int __devinit i801_probe(struct pci_dev *dev,
|
|||
dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
|
||||
|
||||
/* Clear special mode bits */
|
||||
if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
|
||||
outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
|
||||
SMBAUXCTL);
|
||||
if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
|
||||
outb_p(inb_p(SMBAUXCTL(priv)) &
|
||||
~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
|
||||
|
||||
/* set up the sysfs linkage to our parent device */
|
||||
i801_adapter.dev.parent = &dev->dev;
|
||||
priv->adapter.dev.parent = &dev->dev;
|
||||
|
||||
/* Retry up to 3 times on lost arbitration */
|
||||
i801_adapter.retries = 3;
|
||||
priv->adapter.retries = 3;
|
||||
|
||||
snprintf(i801_adapter.name, sizeof(i801_adapter.name),
|
||||
"SMBus I801 adapter at %04lx", i801_smba);
|
||||
err = i2c_add_adapter(&i801_adapter);
|
||||
snprintf(priv->adapter.name, sizeof(priv->adapter.name),
|
||||
"SMBus I801 adapter at %04lx", priv->smba);
|
||||
err = i2c_add_adapter(&priv->adapter);
|
||||
if (err) {
|
||||
dev_err(&dev->dev, "Failed to add SMBus adapter\n");
|
||||
goto exit_release;
|
||||
|
|
@ -803,27 +826,33 @@ static int __devinit i801_probe(struct pci_dev *dev,
|
|||
memset(&info, 0, sizeof(struct i2c_board_info));
|
||||
info.addr = apanel_addr;
|
||||
strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
|
||||
i2c_new_device(&i801_adapter, &info);
|
||||
i2c_new_device(&priv->adapter, &info);
|
||||
}
|
||||
#endif
|
||||
#if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
|
||||
if (dmi_name_in_vendors("FUJITSU"))
|
||||
dmi_walk(dmi_check_onboard_devices, &i801_adapter);
|
||||
dmi_walk(dmi_check_onboard_devices, &priv->adapter);
|
||||
#endif
|
||||
|
||||
pci_set_drvdata(dev, priv);
|
||||
return 0;
|
||||
|
||||
exit_release:
|
||||
pci_release_region(dev, SMBBAR);
|
||||
exit:
|
||||
kfree(priv);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void __devexit i801_remove(struct pci_dev *dev)
|
||||
{
|
||||
i2c_del_adapter(&i801_adapter);
|
||||
pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
|
||||
struct i801_priv *priv = pci_get_drvdata(dev);
|
||||
|
||||
i2c_del_adapter(&priv->adapter);
|
||||
pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
|
||||
pci_release_region(dev, SMBBAR);
|
||||
pci_set_drvdata(dev, NULL);
|
||||
kfree(priv);
|
||||
/*
|
||||
* do not call pci_disable_device(dev) since it can cause hard hangs on
|
||||
* some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
|
||||
|
|
@ -833,8 +862,10 @@ static void __devexit i801_remove(struct pci_dev *dev)
|
|||
#ifdef CONFIG_PM
|
||||
static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
|
||||
{
|
||||
struct i801_priv *priv = pci_get_drvdata(dev);
|
||||
|
||||
pci_save_state(dev);
|
||||
pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
|
||||
pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
|
||||
pci_set_power_state(dev, pci_choose_state(dev, mesg));
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue