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arm64: tegra: Add ethernet support for Tegra186 

The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC
ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data
transfer rates.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2017-02-23 18:30:44 +01:00
parent 73bf90d4d4
commit 0caafbde07
1 changed files with 31 additions and 0 deletions
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31
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@ -27,6 +27,37 @@
gpio-controller;
};
ethernet@2490000 {
compatible = "nvidia,tegra186-eqos",
"snps,dwc-qos-ethernet-4.10";
reg = <0x0 0x02490000 0x0 0x10000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
<&bpmp TEGRA186_CLK_EQOS_AXI>,
<&bpmp TEGRA186_CLK_EQOS_RX>,
<&bpmp TEGRA186_CLK_EQOS_TX>,
<&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
resets = <&bpmp TEGRA186_RESET_EQOS>;
reset-names = "eqos";
status = "disabled";
snps,write-requests = <1>;
snps,read-requests = <3>;
snps,burst-map = <0x7>;
snps,txpbl = <32>;
snps,rxpbl = <8>;
};
uarta: serial@3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x40>;