[ARM] ohci-pxa27x: use ioremap() and offset for register access
This avoid the pre-mapping of OHCI controller register space, and the mapping is made only when necessary (OHCI is probed). Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Eric Miao
Russell King
parent
0cb0b0d3c6
commit
0c392ed9a7
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@ -88,11 +88,6 @@ static struct map_desc standard_io_desc[] __initdata = {
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.pfn = __phys_to_pfn(0x48000000),
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.length = 0x00200000,
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.type = MT_DEVICE
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}, { /* USB host */
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.virtual = 0xf8000000,
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.pfn = __phys_to_pfn(0x4c000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, { /* Camera */
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.virtual = 0xfa000000,
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.pfn = __phys_to_pfn(0x50000000),
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@ -23,46 +23,43 @@
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#include <linux/signal.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <mach/hardware.h>
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#include <mach/ohci.h>
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/*
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* UHC: USB Host Controller (OHCI-like) register definitions
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*/
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#define UHC_BASE_PHYS (0x4C000000)
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#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
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#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
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#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
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#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
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#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
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#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
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#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
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#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
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#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
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#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
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#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
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#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
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#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
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#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
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#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
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#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
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#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
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#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
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#define UHCREV (0x0000) /* UHC HCI Spec Revision */
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#define UHCHCON (0x0004) /* UHC Host Control Register */
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#define UHCCOMS (0x0008) /* UHC Command Status Register */
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#define UHCINTS (0x000C) /* UHC Interrupt Status Register */
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#define UHCINTE (0x0010) /* UHC Interrupt Enable */
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#define UHCINTD (0x0014) /* UHC Interrupt Disable */
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#define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
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#define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
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#define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
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#define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
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#define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
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#define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
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#define UHCDHEAD (0x0030) /* UHC Done Head */
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#define UHCFMI (0x0034) /* UHC Frame Interval */
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#define UHCFMR (0x0038) /* UHC Frame Remaining */
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#define UHCFMN (0x003C) /* UHC Frame Number */
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#define UHCPERS (0x0040) /* UHC Periodic Start */
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#define UHCLS (0x0044) /* UHC Low Speed Threshold */
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#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
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#define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
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#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
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#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
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#define UHCRHDA_POTPGT(x) \
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(((x) & 0xff) << 24) /* Power On To Power Good Time */
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#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
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#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
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#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
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#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
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#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
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#define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
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#define UHCRHS (0x0050) /* UHC Root Hub Status */
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#define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
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#define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
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#define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
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#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
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#define UHCSTAT (0x0060) /* UHC Status Register */
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#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
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#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
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#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
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@ -73,7 +70,7 @@
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#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
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#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
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#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
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#define UHCHR (0x0064) /* UHC Reset Register */
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#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
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#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
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#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
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@ -86,7 +83,7 @@
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#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
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#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
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#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
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#define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
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#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
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#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
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#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
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@ -96,14 +93,20 @@
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#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
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#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
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#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
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#define UHCHIT (0x006C) /* UHC Interrupt Test register */
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#define PXA_UHC_MAX_PORTNUM 3
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#define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 )
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struct pxa27x_ohci {
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/* must be 1st member here for hcd_to_ohci() to work */
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struct ohci_hcd ohci;
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static struct clk *usb_clk;
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struct device *dev;
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struct clk *clk;
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void __iomem *mmio_base;
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};
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#define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd)
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/*
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PMM_NPS_MODE -- PMM Non-power switching mode
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@ -115,30 +118,35 @@ static struct clk *usb_clk;
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PMM_PERPORT_MODE -- PMM per port switching mode
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Ports are powered individually.
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*/
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static int pxa27x_ohci_select_pmm( int mode )
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static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
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{
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switch ( mode ) {
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uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
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uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);
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switch (mode) {
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case PMM_NPS_MODE:
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UHCRHDA |= RH_A_NPS;
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uhcrhda |= RH_A_NPS;
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break;
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case PMM_GLOBAL_MODE:
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UHCRHDA &= ~(RH_A_NPS & RH_A_PSM);
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uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
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break;
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case PMM_PERPORT_MODE:
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UHCRHDA &= ~(RH_A_NPS);
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UHCRHDA |= RH_A_PSM;
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uhcrhda &= ~(RH_A_NPS);
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uhcrhda |= RH_A_PSM;
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/* Set port power control mask bits, only 3 ports. */
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UHCRHDB |= (0x7<<17);
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uhcrhdb |= (0x7<<17);
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break;
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default:
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printk( KERN_ERR
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"Invalid mode %d, set to non-power switch mode.\n",
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mode );
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UHCRHDA |= RH_A_NPS;
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uhcrhda |= RH_A_NPS;
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}
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__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
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__raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
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return 0;
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}
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@ -146,10 +154,11 @@ extern int usb_disabled(void);
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/*-------------------------------------------------------------------------*/
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static inline void pxa27x_setup_hc(struct pxaohci_platform_data *inf)
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static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
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struct pxaohci_platform_data *inf)
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{
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uint32_t uhchr = UHCHR;
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uint32_t uhcrhda = UHCRHDA;
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uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
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uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
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if (inf->flags & ENABLE_PORT1)
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uhchr &= ~UHCHR_SSEP1;
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@ -177,8 +186,17 @@ static inline void pxa27x_setup_hc(struct pxaohci_platform_data *inf)
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uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
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}
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UHCHR = uhchr;
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UHCRHDA = uhcrhda;
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__raw_writel(uhchr, ohci->mmio_base + UHCHR);
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__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
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}
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static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
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{
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uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
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__raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR);
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udelay(11);
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__raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
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}
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#ifdef CONFIG_CPU_PXA27x
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@ -187,24 +205,25 @@ extern void pxa27x_clear_otgph(void);
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#define pxa27x_clear_otgph() do {} while (0)
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#endif
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static int pxa27x_start_hc(struct device *dev)
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static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
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{
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int retval = 0;
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struct pxaohci_platform_data *inf;
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uint32_t uhchr;
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inf = dev->platform_data;
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clk_enable(usb_clk);
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clk_enable(ohci->clk);
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UHCHR |= UHCHR_FHR;
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udelay(11);
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UHCHR &= ~UHCHR_FHR;
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pxa27x_reset_hc(ohci);
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UHCHR |= UHCHR_FSBIR;
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while (UHCHR & UHCHR_FSBIR)
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uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
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__raw_writel(uhchr, ohci->mmio_base + UHCHR);
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while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
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cpu_relax();
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pxa27x_setup_hc(inf);
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pxa27x_setup_hc(ohci, inf);
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if (inf->init)
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retval = inf->init(dev);
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@ -212,32 +231,33 @@ static int pxa27x_start_hc(struct device *dev)
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if (retval < 0)
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return retval;
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UHCHR &= ~UHCHR_SSE;
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UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
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uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
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__raw_writel(uhchr, ohci->mmio_base + UHCHR);
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__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
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/* Clear any OTG Pin Hold */
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pxa27x_clear_otgph();
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return 0;
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}
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static void pxa27x_stop_hc(struct device *dev)
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static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
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{
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struct pxaohci_platform_data *inf;
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uint32_t uhccoms;
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inf = dev->platform_data;
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if (inf->exit)
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inf->exit(dev);
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UHCHR |= UHCHR_FHR;
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udelay(11);
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UHCHR &= ~UHCHR_FHR;
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pxa27x_reset_hc(ohci);
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UHCCOMS |= 1;
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/* Host Controller Reset */
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uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
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__raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
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udelay(10);
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clk_disable(usb_clk);
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clk_disable(ohci->clk);
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}
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@ -261,7 +281,9 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
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int retval, irq;
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struct usb_hcd *hcd;
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struct pxaohci_platform_data *inf;
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struct pxa27x_ohci *ohci;
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struct resource *r;
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struct clk *usb_clk;
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inf = pdev->dev.platform_data;
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@ -305,13 +327,19 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
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goto err2;
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}
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if ((retval = pxa27x_start_hc(&pdev->dev)) < 0) {
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/* initialize "struct pxa27x_ohci" */
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ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
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ohci->dev = &pdev->dev;
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ohci->clk = usb_clk;
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ohci->mmio_base = (void __iomem *)hcd->regs;
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if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
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pr_debug("pxa27x_start_hc failed");
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goto err3;
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}
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/* Select Power Management Mode */
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pxa27x_ohci_select_pmm(inf->port_mode);
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pxa27x_ohci_select_pmm(ohci, inf->port_mode);
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if (inf->power_budget)
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hcd->power_budget = inf->power_budget;
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@ -322,7 +350,7 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
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if (retval == 0)
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return retval;
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pxa27x_stop_hc(&pdev->dev);
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pxa27x_stop_hc(ohci, &pdev->dev);
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err3:
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iounmap(hcd->regs);
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err2:
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@ -349,12 +377,14 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
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*/
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void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
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{
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struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
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usb_remove_hcd(hcd);
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pxa27x_stop_hc(&pdev->dev);
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pxa27x_stop_hc(ohci, &pdev->dev);
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iounmap(hcd->regs);
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release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
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usb_put_hcd(hcd);
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clk_put(usb_clk);
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clk_put(ohci->clk);
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}
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/*-------------------------------------------------------------------------*/
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@ -387,7 +417,7 @@ ohci_pxa27x_start (struct usb_hcd *hcd)
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static const struct hc_driver ohci_pxa27x_hc_driver = {
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.description = hcd_name,
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.product_desc = "PXA27x OHCI",
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.hcd_priv_size = sizeof(struct ohci_hcd),
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.hcd_priv_size = sizeof(struct pxa27x_ohci),
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/*
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* generic hardware linkage
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@ -451,13 +481,13 @@ static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
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static int ohci_hcd_pxa27x_drv_suspend(struct platform_device *pdev, pm_message_t state)
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{
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struct usb_hcd *hcd = platform_get_drvdata(pdev);
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struct ohci_hcd *ohci = hcd_to_ohci(hcd);
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struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
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if (time_before(jiffies, ohci->next_statechange))
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if (time_before(jiffies, ohci->ohci.next_statechange))
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msleep(5);
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ohci->next_statechange = jiffies;
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ohci->ohci.next_statechange = jiffies;
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pxa27x_stop_hc(&pdev->dev);
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pxa27x_stop_hc(ohci, &pdev->dev);
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hcd->state = HC_STATE_SUSPENDED;
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return 0;
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@ -466,14 +496,14 @@ static int ohci_hcd_pxa27x_drv_suspend(struct platform_device *pdev, pm_message_
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static int ohci_hcd_pxa27x_drv_resume(struct platform_device *pdev)
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{
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struct usb_hcd *hcd = platform_get_drvdata(pdev);
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||||
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
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||||
struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
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int status;
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if (time_before(jiffies, ohci->next_statechange))
|
||||
if (time_before(jiffies, ohci->ohci.next_statechange))
|
||||
msleep(5);
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||||
ohci->next_statechange = jiffies;
|
||||
ohci->ohci.next_statechange = jiffies;
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||||
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||||
if ((status = pxa27x_start_hc(&pdev->dev)) < 0)
|
||||
if ((status = pxa27x_start_hc(ohci, &pdev->dev)) < 0)
|
||||
return status;
|
||||
|
||||
ohci_finish_controller_resume(hcd);
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||||
|
|
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Reference in New Issue