- ARM: mediatek: Add regmap to mediatek Kconfig
- soc: mediatek: Drop owner assignment from platform_driver - soc: Mediatek: Add SCPSYS power domain driver - dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit - soc: mediatek: Add infracfg misc driver support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVt2EHAAoJELQ5Ylss8dNDHA0QAIqW6e/OIKNyJm1ykGEYHqtx 1fKyQmjRPN1/VEl13UaXOg/Ke2JdeloJr0Yi/0NI0Si/Sy0i1dtnNcUIkgUZ9hYc WbeSSydQWoj8+023BsuXy07+xXnnrJbN4XRVcFfAMagKYJhlewVZi6x1avPmrlJC 8XGck4D1M6qyW9nbdIBr1qx71kunzZQkHJ/bVg0kt/0nYYF+FkrFXEWcGa+Cc8IC QbCe1X7GhsVRnEelwcXK6J6k964mhhKhTmdvK5oMJDNvtNF7+KiH3luLJSY4XTlI Ao8aBvsNSnAt6qYOoojG1MwohdR/X1vvxhi+hLJ1vV1Znp4wmJmSFyYZKaaiX+/d M5/q3Ve3b7kfEPpliqikSYV1X3cC7twEKsER3egvy+NheAdyhQDJUA7HDfKiPT41 HVWXZB0na7SiNT54cWagGjPH3KNTcttnhhzx1dHrkgT9FD+2HCX5qlqB9E7OEWgD kgSh/yHPqc5jyjmqvKhCS87Pq9Usik6n8XsLdn/Kx5eOQhv6sp+y8GP1x1bINXfP lwEeBc4tzjHujGsRz6fJRmsvvj+ZvB2bHig+XxnSWz+RXJiRPtHswSb5MimAjrhE Eie03qavgV5PW1dmK0+I/DTsi6J6IbxmlE670HGWqRZyoF9cITf8CnjS+b5bgOVO qQqnKEUIbnJwjYiSP2Y0 =sRus -----END PGP SIGNATURE----- Merge tag 'v4.2-next-soc' of https://github.com/mbgg/linux-mediatek into next/soc - ARM: mediatek: Add regmap to mediatek Kconfig - soc: mediatek: Drop owner assignment from platform_driver - soc: Mediatek: Add SCPSYS power domain driver - dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit - soc: mediatek: Add infracfg misc driver support * tag 'v4.2-next-soc' of https://github.com/mbgg/linux-mediatek: ARM: mediatek: Add regmap to mediatek Kconfig soc: mediatek: Drop owner assignment from platform_driver soc: Mediatek: Add SCPSYS power domain driver dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit soc: mediatek: Add infracfg misc driver support Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
0c21bcb616
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@ -0,0 +1,41 @@
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MediaTek SCPSYS
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===============
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The System Control Processor System (SCPSYS) has several power management
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related tasks in the system. The tasks include thermal measurement, dynamic
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voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
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The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power
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domain control.
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The driver implements the Generic PM domain bindings described in
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power/power_domain.txt. It provides the power domains defined in
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include/dt-bindings/power/mt8173-power.h.
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Required properties:
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- compatible: Must be "mediatek,mt8173-scpsys"
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- #power-domain-cells: Must be 1
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- reg: Address range of the SCPSYS unit
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- infracfg: must contain a phandle to the infracfg controller
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- clock, clock-names: clocks according to the common clock binding.
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The clocks needed "mm" and "mfg". These are the
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clocks which hardware needs to be enabled before
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enabling certain power domains.
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Example:
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scpsys: scpsys@10006000 {
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#power-domain-cells = <1>;
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compatible = "mediatek,mt8173-scpsys";
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reg = <0 0x10006000 0 0x1000>;
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infracfg = <&infracfg>;
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clocks = <&clk26m>,
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<&topckgen CLK_TOP_MM_SEL>;
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clock-names = "mfg", "mm";
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};
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Example consumer:
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afe: mt8173-afe-pcm@11220000 {
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compatible = "mediatek,mt8173-afe-pcm";
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power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
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};
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@ -3,6 +3,7 @@ menuconfig ARCH_MEDIATEK
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select ARM_GIC
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select PINCTRL
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select MTK_TIMER
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select MFD_SYSCON
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help
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Support for Mediatek MT65xx & MT81xx SoCs
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@ -1,6 +1,15 @@
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#
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# MediaTek SoC drivers
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#
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config MTK_INFRACFG
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bool "MediaTek INFRACFG Support"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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select REGMAP
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help
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Say yes here to add support for the MediaTek INFRACFG controller. The
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INFRACFG controller contains various infrastructure registers not
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directly associated to any device.
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config MTK_PMIC_WRAP
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tristate "MediaTek PMIC Wrapper Support"
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depends on ARCH_MEDIATEK
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@ -10,3 +19,13 @@ config MTK_PMIC_WRAP
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Say yes here to add support for MediaTek PMIC Wrapper found
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on different MediaTek SoCs. The PMIC wrapper is a proprietary
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hardware to connect the PMIC.
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config MTK_SCPSYS
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bool "MediaTek SCPSYS Support"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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select REGMAP
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select MTK_INFRACFG
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select PM_GENERIC_DOMAINS if PM
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help
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Say yes here to add support for the MediaTek SCPSYS power domain
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driver.
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@ -1 +1,3 @@
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obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
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obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
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obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
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@ -0,0 +1,91 @@
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/*
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* Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/export.h>
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#include <linux/jiffies.h>
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#include <linux/regmap.h>
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#include <linux/soc/mediatek/infracfg.h>
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#include <asm/processor.h>
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#define INFRA_TOPAXI_PROTECTEN 0x0220
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#define INFRA_TOPAXI_PROTECTSTA1 0x0228
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/**
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* mtk_infracfg_set_bus_protection - enable bus protection
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* @regmap: The infracfg regmap
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* @mask: The mask containing the protection bits to be enabled.
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*
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* This function enables the bus protection bits for disabled power
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* domains so that the system does not hang when some unit accesses the
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* bus while in power down.
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*/
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int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask)
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{
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unsigned long expired;
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u32 val;
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int ret;
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regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, mask);
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expired = jiffies + HZ;
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while (1) {
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ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
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if (ret)
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return ret;
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if ((val & mask) == mask)
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break;
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cpu_relax();
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if (time_after(jiffies, expired))
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return -EIO;
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}
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return 0;
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}
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/**
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* mtk_infracfg_clear_bus_protection - disable bus protection
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* @regmap: The infracfg regmap
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* @mask: The mask containing the protection bits to be disabled.
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*
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* This function disables the bus protection bits previously enabled with
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* mtk_infracfg_set_bus_protection.
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*/
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int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask)
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{
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unsigned long expired;
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int ret;
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regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
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expired = jiffies + HZ;
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while (1) {
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u32 val;
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ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
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if (ret)
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return ret;
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if (!(val & mask))
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break;
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cpu_relax();
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if (time_after(jiffies, expired))
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return -EIO;
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}
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return 0;
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}
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@ -926,7 +926,6 @@ err_out1:
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static struct platform_driver pwrap_drv = {
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.driver = {
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.name = "mt-pmic-pwrap",
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(of_pwrap_match_tbl),
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},
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.probe = pwrap_probe,
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|
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@ -0,0 +1,487 @@
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/*
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* Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/regmap.h>
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#include <linux/soc/mediatek/infracfg.h>
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#include <dt-bindings/power/mt8173-power.h>
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#define SPM_VDE_PWR_CON 0x0210
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#define SPM_MFG_PWR_CON 0x0214
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#define SPM_VEN_PWR_CON 0x0230
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#define SPM_ISP_PWR_CON 0x0238
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#define SPM_DIS_PWR_CON 0x023c
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#define SPM_VEN2_PWR_CON 0x0298
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#define SPM_AUDIO_PWR_CON 0x029c
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#define SPM_MFG_2D_PWR_CON 0x02c0
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#define SPM_MFG_ASYNC_PWR_CON 0x02c4
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#define SPM_USB_PWR_CON 0x02cc
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#define SPM_PWR_STATUS 0x060c
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#define SPM_PWR_STATUS_2ND 0x0610
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#define PWR_RST_B_BIT BIT(0)
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#define PWR_ISO_BIT BIT(1)
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#define PWR_ON_BIT BIT(2)
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#define PWR_ON_2ND_BIT BIT(3)
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#define PWR_CLK_DIS_BIT BIT(4)
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#define PWR_STATUS_DISP BIT(3)
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#define PWR_STATUS_MFG BIT(4)
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#define PWR_STATUS_ISP BIT(5)
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#define PWR_STATUS_VDEC BIT(7)
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#define PWR_STATUS_VENC_LT BIT(20)
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#define PWR_STATUS_VENC BIT(21)
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#define PWR_STATUS_MFG_2D BIT(22)
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#define PWR_STATUS_MFG_ASYNC BIT(23)
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#define PWR_STATUS_AUDIO BIT(24)
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#define PWR_STATUS_USB BIT(25)
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enum clk_id {
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MT8173_CLK_MM,
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MT8173_CLK_MFG,
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MT8173_CLK_NONE,
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MT8173_CLK_MAX = MT8173_CLK_NONE,
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};
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struct scp_domain_data {
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const char *name;
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u32 sta_mask;
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int ctl_offs;
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u32 sram_pdn_bits;
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u32 sram_pdn_ack_bits;
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u32 bus_prot_mask;
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enum clk_id clk_id;
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};
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static const struct scp_domain_data scp_domain_data[] __initconst = {
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[MT8173_POWER_DOMAIN_VDEC] = {
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.name = "vdec",
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.sta_mask = PWR_STATUS_VDEC,
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.ctl_offs = SPM_VDE_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.clk_id = MT8173_CLK_MM,
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},
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[MT8173_POWER_DOMAIN_VENC] = {
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.name = "venc",
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.sta_mask = PWR_STATUS_VENC,
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.ctl_offs = SPM_VEN_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.clk_id = MT8173_CLK_MM,
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},
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[MT8173_POWER_DOMAIN_ISP] = {
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.name = "isp",
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = SPM_ISP_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.clk_id = MT8173_CLK_MM,
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},
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[MT8173_POWER_DOMAIN_MM] = {
|
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.name = "mm",
|
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.sta_mask = PWR_STATUS_DISP,
|
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.ctl_offs = SPM_DIS_PWR_CON,
|
||||
.sram_pdn_bits = GENMASK(11, 8),
|
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.clk_id = MT8173_CLK_MM,
|
||||
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
|
||||
MT8173_TOP_AXI_PROT_EN_MM_M1,
|
||||
},
|
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[MT8173_POWER_DOMAIN_VENC_LT] = {
|
||||
.name = "venc_lt",
|
||||
.sta_mask = PWR_STATUS_VENC_LT,
|
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.ctl_offs = SPM_VEN2_PWR_CON,
|
||||
.sram_pdn_bits = GENMASK(11, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(15, 12),
|
||||
.clk_id = MT8173_CLK_MM,
|
||||
},
|
||||
[MT8173_POWER_DOMAIN_AUDIO] = {
|
||||
.name = "audio",
|
||||
.sta_mask = PWR_STATUS_AUDIO,
|
||||
.ctl_offs = SPM_AUDIO_PWR_CON,
|
||||
.sram_pdn_bits = GENMASK(11, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(15, 12),
|
||||
.clk_id = MT8173_CLK_NONE,
|
||||
},
|
||||
[MT8173_POWER_DOMAIN_USB] = {
|
||||
.name = "usb",
|
||||
.sta_mask = PWR_STATUS_USB,
|
||||
.ctl_offs = SPM_USB_PWR_CON,
|
||||
.sram_pdn_bits = GENMASK(11, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(15, 12),
|
||||
.clk_id = MT8173_CLK_NONE,
|
||||
},
|
||||
[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
|
||||
.name = "mfg_async",
|
||||
.sta_mask = PWR_STATUS_MFG_ASYNC,
|
||||
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
|
||||
.sram_pdn_bits = GENMASK(11, 8),
|
||||
.sram_pdn_ack_bits = 0,
|
||||
.clk_id = MT8173_CLK_MFG,
|
||||
},
|
||||
[MT8173_POWER_DOMAIN_MFG_2D] = {
|
||||
.name = "mfg_2d",
|
||||
.sta_mask = PWR_STATUS_MFG_2D,
|
||||
.ctl_offs = SPM_MFG_2D_PWR_CON,
|
||||
.sram_pdn_bits = GENMASK(11, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(13, 12),
|
||||
.clk_id = MT8173_CLK_NONE,
|
||||
},
|
||||
[MT8173_POWER_DOMAIN_MFG] = {
|
||||
.name = "mfg",
|
||||
.sta_mask = PWR_STATUS_MFG,
|
||||
.ctl_offs = SPM_MFG_PWR_CON,
|
||||
.sram_pdn_bits = GENMASK(13, 8),
|
||||
.sram_pdn_ack_bits = GENMASK(21, 16),
|
||||
.clk_id = MT8173_CLK_NONE,
|
||||
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
|
||||
MT8173_TOP_AXI_PROT_EN_MFG_M0 |
|
||||
MT8173_TOP_AXI_PROT_EN_MFG_M1 |
|
||||
MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
|
||||
},
|
||||
};
|
||||
|
||||
#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
|
||||
|
||||
struct scp;
|
||||
|
||||
struct scp_domain {
|
||||
struct generic_pm_domain genpd;
|
||||
struct scp *scp;
|
||||
struct clk *clk;
|
||||
u32 sta_mask;
|
||||
void __iomem *ctl_addr;
|
||||
u32 sram_pdn_bits;
|
||||
u32 sram_pdn_ack_bits;
|
||||
u32 bus_prot_mask;
|
||||
};
|
||||
|
||||
struct scp {
|
||||
struct scp_domain domains[NUM_DOMAINS];
|
||||
struct genpd_onecell_data pd_data;
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct regmap *infracfg;
|
||||
};
|
||||
|
||||
static int scpsys_domain_is_on(struct scp_domain *scpd)
|
||||
{
|
||||
struct scp *scp = scpd->scp;
|
||||
|
||||
u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask;
|
||||
u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask;
|
||||
|
||||
/*
|
||||
* A domain is on when both status bits are set. If only one is set
|
||||
* return an error. This happens while powering up a domain
|
||||
*/
|
||||
|
||||
if (status && status2)
|
||||
return true;
|
||||
if (!status && !status2)
|
||||
return false;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int scpsys_power_on(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
|
||||
struct scp *scp = scpd->scp;
|
||||
unsigned long timeout;
|
||||
bool expired;
|
||||
void __iomem *ctl_addr = scpd->ctl_addr;
|
||||
u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
if (scpd->clk) {
|
||||
ret = clk_prepare_enable(scpd->clk);
|
||||
if (ret)
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
val = readl(ctl_addr);
|
||||
val |= PWR_ON_BIT;
|
||||
writel(val, ctl_addr);
|
||||
val |= PWR_ON_2ND_BIT;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
/* wait until PWR_ACK = 1 */
|
||||
timeout = jiffies + HZ;
|
||||
expired = false;
|
||||
while (1) {
|
||||
ret = scpsys_domain_is_on(scpd);
|
||||
if (ret > 0)
|
||||
break;
|
||||
|
||||
if (expired) {
|
||||
ret = -ETIMEDOUT;
|
||||
goto err_pwr_ack;
|
||||
}
|
||||
|
||||
cpu_relax();
|
||||
|
||||
if (time_after(jiffies, timeout))
|
||||
expired = true;
|
||||
}
|
||||
|
||||
val &= ~PWR_CLK_DIS_BIT;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
val &= ~PWR_ISO_BIT;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
val |= PWR_RST_B_BIT;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
val &= ~scpd->sram_pdn_bits;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
/* wait until SRAM_PDN_ACK all 0 */
|
||||
timeout = jiffies + HZ;
|
||||
expired = false;
|
||||
while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
|
||||
|
||||
if (expired) {
|
||||
ret = -ETIMEDOUT;
|
||||
goto err_pwr_ack;
|
||||
}
|
||||
|
||||
cpu_relax();
|
||||
|
||||
if (time_after(jiffies, timeout))
|
||||
expired = true;
|
||||
}
|
||||
|
||||
if (scpd->bus_prot_mask) {
|
||||
ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
|
||||
scpd->bus_prot_mask);
|
||||
if (ret)
|
||||
goto err_pwr_ack;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_pwr_ack:
|
||||
clk_disable_unprepare(scpd->clk);
|
||||
err_clk:
|
||||
dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int scpsys_power_off(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
|
||||
struct scp *scp = scpd->scp;
|
||||
unsigned long timeout;
|
||||
bool expired;
|
||||
void __iomem *ctl_addr = scpd->ctl_addr;
|
||||
u32 pdn_ack = scpd->sram_pdn_ack_bits;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
if (scpd->bus_prot_mask) {
|
||||
ret = mtk_infracfg_set_bus_protection(scp->infracfg,
|
||||
scpd->bus_prot_mask);
|
||||
if (ret)
|
||||
goto out;
|
||||
}
|
||||
|
||||
val = readl(ctl_addr);
|
||||
val |= scpd->sram_pdn_bits;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
/* wait until SRAM_PDN_ACK all 1 */
|
||||
timeout = jiffies + HZ;
|
||||
expired = false;
|
||||
while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
|
||||
if (expired) {
|
||||
ret = -ETIMEDOUT;
|
||||
goto out;
|
||||
}
|
||||
|
||||
cpu_relax();
|
||||
|
||||
if (time_after(jiffies, timeout))
|
||||
expired = true;
|
||||
}
|
||||
|
||||
val |= PWR_ISO_BIT;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
val &= ~PWR_RST_B_BIT;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
val |= PWR_CLK_DIS_BIT;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
val &= ~PWR_ON_BIT;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
val &= ~PWR_ON_2ND_BIT;
|
||||
writel(val, ctl_addr);
|
||||
|
||||
/* wait until PWR_ACK = 0 */
|
||||
timeout = jiffies + HZ;
|
||||
expired = false;
|
||||
while (1) {
|
||||
ret = scpsys_domain_is_on(scpd);
|
||||
if (ret == 0)
|
||||
break;
|
||||
|
||||
if (expired) {
|
||||
ret = -ETIMEDOUT;
|
||||
goto out;
|
||||
}
|
||||
|
||||
cpu_relax();
|
||||
|
||||
if (time_after(jiffies, timeout))
|
||||
expired = true;
|
||||
}
|
||||
|
||||
if (scpd->clk)
|
||||
clk_disable_unprepare(scpd->clk);
|
||||
|
||||
return 0;
|
||||
|
||||
out:
|
||||
dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init scpsys_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct genpd_onecell_data *pd_data;
|
||||
struct resource *res;
|
||||
int i, ret;
|
||||
struct scp *scp;
|
||||
struct clk *clk[MT8173_CLK_MAX];
|
||||
|
||||
scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
|
||||
if (!scp)
|
||||
return -ENOMEM;
|
||||
|
||||
scp->dev = &pdev->dev;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
scp->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(scp->base))
|
||||
return PTR_ERR(scp->base);
|
||||
|
||||
pd_data = &scp->pd_data;
|
||||
|
||||
pd_data->domains = devm_kzalloc(&pdev->dev,
|
||||
sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
|
||||
if (!pd_data->domains)
|
||||
return -ENOMEM;
|
||||
|
||||
clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
|
||||
if (IS_ERR(clk[MT8173_CLK_MM]))
|
||||
return PTR_ERR(clk[MT8173_CLK_MM]);
|
||||
|
||||
clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
|
||||
if (IS_ERR(clk[MT8173_CLK_MFG]))
|
||||
return PTR_ERR(clk[MT8173_CLK_MFG]);
|
||||
|
||||
scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
||||
"infracfg");
|
||||
if (IS_ERR(scp->infracfg)) {
|
||||
dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
|
||||
PTR_ERR(scp->infracfg));
|
||||
return PTR_ERR(scp->infracfg);
|
||||
}
|
||||
|
||||
pd_data->num_domains = NUM_DOMAINS;
|
||||
|
||||
for (i = 0; i < NUM_DOMAINS; i++) {
|
||||
struct scp_domain *scpd = &scp->domains[i];
|
||||
struct generic_pm_domain *genpd = &scpd->genpd;
|
||||
const struct scp_domain_data *data = &scp_domain_data[i];
|
||||
|
||||
pd_data->domains[i] = genpd;
|
||||
scpd->scp = scp;
|
||||
|
||||
scpd->sta_mask = data->sta_mask;
|
||||
scpd->ctl_addr = scp->base + data->ctl_offs;
|
||||
scpd->sram_pdn_bits = data->sram_pdn_bits;
|
||||
scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
|
||||
scpd->bus_prot_mask = data->bus_prot_mask;
|
||||
if (data->clk_id != MT8173_CLK_NONE)
|
||||
scpd->clk = clk[data->clk_id];
|
||||
|
||||
genpd->name = data->name;
|
||||
genpd->power_off = scpsys_power_off;
|
||||
genpd->power_on = scpsys_power_on;
|
||||
|
||||
/*
|
||||
* Initially turn on all domains to make the domains usable
|
||||
* with !CONFIG_PM and to get the hardware in sync with the
|
||||
* software. The unused domains will be switched off during
|
||||
* late_init time.
|
||||
*/
|
||||
genpd->power_on(genpd);
|
||||
|
||||
pm_genpd_init(genpd, NULL, false);
|
||||
}
|
||||
|
||||
/*
|
||||
* We are not allowed to fail here since there is no way to unregister
|
||||
* a power domain. Once registered above we have to keep the domains
|
||||
* valid.
|
||||
*/
|
||||
|
||||
ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
|
||||
pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
|
||||
if (ret && IS_ENABLED(CONFIG_PM))
|
||||
dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
|
||||
|
||||
ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
|
||||
pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
|
||||
if (ret && IS_ENABLED(CONFIG_PM))
|
||||
dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
|
||||
|
||||
ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_scpsys_match_tbl[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8173-scpsys",
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_driver scpsys_drv = {
|
||||
.driver = {
|
||||
.name = "mtk-scpsys",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(of_scpsys_match_tbl),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver_probe(scpsys_drv, scpsys_probe);
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
|
||||
#define _DT_BINDINGS_POWER_MT8183_POWER_H
|
||||
|
||||
#define MT8173_POWER_DOMAIN_VDEC 0
|
||||
#define MT8173_POWER_DOMAIN_VENC 1
|
||||
#define MT8173_POWER_DOMAIN_ISP 2
|
||||
#define MT8173_POWER_DOMAIN_MM 3
|
||||
#define MT8173_POWER_DOMAIN_VENC_LT 4
|
||||
#define MT8173_POWER_DOMAIN_AUDIO 5
|
||||
#define MT8173_POWER_DOMAIN_USB 6
|
||||
#define MT8173_POWER_DOMAIN_MFG_ASYNC 7
|
||||
#define MT8173_POWER_DOMAIN_MFG_2D 8
|
||||
#define MT8173_POWER_DOMAIN_MFG 9
|
||||
|
||||
#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
#ifndef __SOC_MEDIATEK_INFRACFG_H
|
||||
#define __SOC_MEDIATEK_INFRACFG_H
|
||||
|
||||
#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
|
||||
#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
|
||||
#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
|
||||
#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
|
||||
#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
|
||||
#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
|
||||
#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
|
||||
#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
|
||||
#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
|
||||
#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
|
||||
#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
|
||||
#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
|
||||
|
||||
int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask);
|
||||
int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask);
|
||||
|
||||
#endif /* __SOC_MEDIATEK_INFRACFG_H */
|
||||
Loading…
Reference in New Issue