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drm/amd/display: change the max clock level to 16 

As the gfxclk for SMU11 can have at most 16 discrete levels.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2019-01-21 17:57:29 +08:00 committed by Alex Deucher
parent 8ce84d4341
commit 0bcaefa6bf
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/dm_services_types.h
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@ -92,7 +92,7 @@ enum dm_pp_clock_type {
(clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \ (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \
"Invalid" "Invalid"
#define DM_PP_MAX_CLOCK_LEVELS 8 #define DM_PP_MAX_CLOCK_LEVELS 16
struct dm_pp_clock_levels { struct dm_pp_clock_levels {
uint32_t num_levels; uint32_t num_levels;