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[XTENSA] Fix icache flush for cache aliasing 

Set the execution bit in the temporary TLB when we flush the
instruction cache.

Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Chris Zankel 2008-02-12 10:11:45 -08:00
parent 70e137eb48
commit 0b2c3afdaa
1 changed files with 1 additions and 1 deletions
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2
arch/xtensa/mm/misc.S
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@ -295,7 +295,7 @@ ENTRY(__tlbtemp_mapping_itlb)
ENTRY(__invalidate_icache_page_alias)
entry sp, 16
addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE)
mov a4, a2
witlb a6, a2
isync