From 828fcfe3c84ade68ecc3f1ba78baebc1654977f3 Mon Sep 17 00:00:00 2001 From: Zhou Wang Date: Wed, 25 Mar 2015 14:57:45 +0800 Subject: [PATCH 1/3] ARM: dts: hip04: add GPIO pieces Hisilicon Soc hip04 has four GPIO controllers, each one has 32 GPIOs and can be configured to be an interrupt controller.The GPIO controllers are compatible with the snps,dw-apb-gpio driver. This patch add the corresponding device tree nodes. Acked-by: Linus Walleij Signed-off-by: Zhou Wang Signed-off-by: Wei Xu --- arch/arm/boot/dts/hip04.dtsi | 75 ++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 44044f275115..4201ddd72477 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -269,6 +269,81 @@ interrupts = <0 372 4>; }; + gpio@4003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4003000 0x1000>; + + gpio3: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 392 4>; + }; + }; + + gpio@4002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4002000 0x1000>; + + gpio2: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 391 4>; + }; + }; + + gpio@4001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4001000 0x1000>; + + gpio1: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 390 4>; + }; + }; + + gpio@4000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4000000 0x1000>; + + gpio0: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 389 4>; + }; + }; }; etb@0,e3c42000 { From e42536140889eaf62a794c926cfb7c0f918bf788 Mon Sep 17 00:00:00 2001 From: Zhou Wang Date: Wed, 25 Mar 2015 15:04:51 +0800 Subject: [PATCH 2/3] mtd: hisilicon: add device tree node for NAND controller This patch adds dts support for NAND flash controller of Hisilicon Soc Hip04. Changes in v3: - Change E-mail address in signed-off-by to "wangzhou1@hisilicon.com" Changes in v2: - Base on v3.19-rc1 - Use nand-ecc-strength, nand-ecc-step-size to replace hisi,nand-ecc-bits Changes in v1: - Move partition and other board related information into board dts file: hip04-d01.dts Signed-off-by: Zhou Wang Acked-by: Haojian Zhuang Reviewed-by: Brian Norris Signed-off-by: Wei Xu --- arch/arm/boot/dts/hip04-d01.dts | 27 +++++++++++++++++++++++++++ arch/arm/boot/dts/hip04.dtsi | 8 ++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts index 40a9e33c2654..ba04dd5fba8b 100644 --- a/arch/arm/boot/dts/hip04-d01.dts +++ b/arch/arm/boot/dts/hip04-d01.dts @@ -28,5 +28,32 @@ uart0: uart@4007000 { status = "ok"; }; + + nand: nand@4020000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + + partition@0 { + label = "nand_text"; + reg = <0x00000000 0x00400000>; + }; + + partition@00400000 { + label = "nand_monitor"; + reg = <0x00400000 0x00400000>; + }; + + partition@00800000 { + label = "nand_kernel"; + reg = <0x00800000 0x00800000>; + }; + + partition@01000000 { + label = "nand_fs"; + reg = <0x01000000 0x1f000000>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 4201ddd72477..027d06c06322 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -344,6 +344,14 @@ interrupts = <0 389 4>; }; }; + + nand: nand@4020000 { + compatible = "hisilicon,504-nfc"; + reg = <0x4020000 0x10000>, <0x5000000 0x1000>; + interrupts = <0 379 4>; + #address-cells = <1>; + #size-cells = <1>; + }; }; etb@0,e3c42000 { From 9fac45c16c33f9f822ed7f9b9660890f68f16d8b Mon Sep 17 00:00:00 2001 From: Fathi Boudra Date: Fri, 10 Apr 2015 10:16:19 +0300 Subject: [PATCH 3/3] ARM: dts: add HiSilicon hip04 ethernet controller resource add the device tree binding for the HiSilicon hip04 ethernet controller based on Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt Signed-off-by: Zhangfei Gao Signed-off-by: Fathi Boudra Signed-off-by: Wei Xu --- arch/arm/boot/dts/hip04.dtsi | 50 ++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 027d06c06322..6434b7f91329 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -352,6 +352,56 @@ #address-cells = <1>; #size-cells = <1>; }; + + mdio { + compatible = "hisilicon,hip04-mdio"; + reg = <0x28f1000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + marvell,reg-init = <18 0x14 0 0x8001>; + }; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + marvell,reg-init = <18 0x14 0 0x8001>; + }; + }; + + ppe: ppe@28c0000 { + compatible = "hisilicon,hip04-ppe", "syscon"; + reg = <0x28c0000 0x10000>; + }; + + fe: ethernet@28b0000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x28b0000 0x10000>; + interrupts = <0 413 4>; + phy-mode = "mii"; + port-handle = <&ppe 31 0>; + }; + + ge0: ethernet@2800000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x2800000 0x10000>; + interrupts = <0 402 4>; + phy-mode = "sgmii"; + port-handle = <&ppe 0 1>; + phy-handle = <&phy0>; + }; + + ge8: ethernet@2880000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x2880000 0x10000>; + interrupts = <0 410 4>; + phy-mode = "sgmii"; + port-handle = <&ppe 8 2>; + phy-handle = <&phy1>; + }; }; etb@0,e3c42000 {