ARM: DT: Hisilicon hip04 soc and D01 board updates for 4.2
- Add hip04 GPIO nodes - Add NANDC nodes for hip04 and D01 board - Add hip04 ethernet related nodes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVTBseAAoJEAvIV27ZiWZcqjcP/iboUW/3RpbKafraJdUNBKV5 SIQvSdV1oNiWYjq+75ZZdp0Jk9lE1GAhefNmhGUET6oubu6jW3w8//uIO0/9ZhjN 3SyPuQIkYDGzonegvAUw+ffnpwEXP0yrdcBjsQRMmSf1tAHuxLK9e7pEH/G1jUou g8e3bmfkXXG2mMUQSGg+oEhzUpEuiPjTDD3BcWK1Cb3aJBoUBH6wtE/fy2clPwEP WXa6KjsBBUuONLH1za/usq+4jBzgOa7gfzRWRMCk5/uhcuJ3ojOGp6TgruLmg6q3 XiZVRaAp9Wjz8nA4nkP2SWRVkDUYbhvTNu3lPkfcCDiR2mbinWDdzdw1gk3Zadnr UYbpXWgkR9m0E+0WG8/LuE1eg+XmoSB5GiCkwPAYo513eUy73NUwTtcry4V7RkSJ V7tgRhhqN3M31PrRuYxImu092f/zR3xAxSfX2JchD2c/GQeEJ5XNuvTmRH7JgpCP 2Jo7BHXFMTFbodYPmaUlze7U1RaKw+Knt1MJCrJznpMX6m0S0DcWI6qtBWfATxJY lPL1jq9XDAlvz7+S5GwefS/ydR6nRJgQwb4UaWdKQodS6t3ahPodUte6dWFZ9gGN ANi4e+0YQl4xuqTHT2/154dlkpK4DSu8ZH9UaCf1c1GM9J3lLPTozFieqfq2XXhj f4o/Qbez4ZImuhfdJGoz =n1gB -----END PGP SIGNATURE----- Merge tag 'hip04-dt-for-4.2' of git://github.com/hisilicon/linux-hisi into next/dt Merge "ARM: DT: Hisilicon hip04 soc and D01 board updates for 4.2" from Wei Xu: - Add hip04 GPIO nodes - Add NANDC nodes for hip04 and D01 board - Add hip04 ethernet related nodes * tag 'hip04-dt-for-4.2' of git://github.com/hisilicon/linux-hisi: ARM: dts: add HiSilicon hip04 ethernet controller resource mtd: hisilicon: add device tree node for NAND controller ARM: dts: hip04: add GPIO pieces
This commit is contained in:
Arnd Bergmann
commit
0b1480103f
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@ -28,5 +28,32 @@
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uart0: uart@4007000 {
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status = "ok";
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};
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nand: nand@4020000 {
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <16>;
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nand-ecc-step-size = <1024>;
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partition@0 {
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label = "nand_text";
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reg = <0x00000000 0x00400000>;
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};
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partition@00400000 {
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label = "nand_monitor";
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reg = <0x00400000 0x00400000>;
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};
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partition@00800000 {
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label = "nand_kernel";
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reg = <0x00800000 0x00800000>;
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};
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partition@01000000 {
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label = "nand_fs";
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reg = <0x01000000 0x1f000000>;
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};
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};
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};
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};
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@ -269,6 +269,139 @@
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interrupts = <0 372 4>;
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};
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gpio@4003000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0x4003000 0x1000>;
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gpio3: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 392 4>;
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};
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};
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gpio@4002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0x4002000 0x1000>;
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gpio2: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 391 4>;
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};
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};
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gpio@4001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0x4001000 0x1000>;
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gpio1: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 390 4>;
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};
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};
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gpio@4000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0x4000000 0x1000>;
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gpio0: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 389 4>;
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};
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};
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nand: nand@4020000 {
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compatible = "hisilicon,504-nfc";
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reg = <0x4020000 0x10000>, <0x5000000 0x1000>;
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interrupts = <0 379 4>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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mdio {
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compatible = "hisilicon,hip04-mdio";
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reg = <0x28f1000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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marvell,reg-init = <18 0x14 0 0x8001>;
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};
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phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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marvell,reg-init = <18 0x14 0 0x8001>;
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};
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};
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ppe: ppe@28c0000 {
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compatible = "hisilicon,hip04-ppe", "syscon";
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reg = <0x28c0000 0x10000>;
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};
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fe: ethernet@28b0000 {
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compatible = "hisilicon,hip04-mac";
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reg = <0x28b0000 0x10000>;
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interrupts = <0 413 4>;
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phy-mode = "mii";
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port-handle = <&ppe 31 0>;
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};
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ge0: ethernet@2800000 {
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compatible = "hisilicon,hip04-mac";
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reg = <0x2800000 0x10000>;
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interrupts = <0 402 4>;
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phy-mode = "sgmii";
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port-handle = <&ppe 0 1>;
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phy-handle = <&phy0>;
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};
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ge8: ethernet@2880000 {
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compatible = "hisilicon,hip04-mac";
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reg = <0x2880000 0x10000>;
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interrupts = <0 410 4>;
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phy-mode = "sgmii";
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port-handle = <&ppe 8 2>;
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phy-handle = <&phy1>;
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};
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};
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etb@0,e3c42000 {
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