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More staging patches for 3.15-rc1 

Here are some more staging patches for 3.15-rc1.  They include a
 late-submission of a wireless driver that a bunch of people seem to have
 the hardware for now.  As it's stand-alone, it should be fine (now
 passes the 0-day random build bot tests.)  There are also some fixes for
 the unisys drivers, as they were causing havoc on a number of different
 machines.  To resolve all of those issues, we just mark the driver as
 BROKEN now, and we can fix it up "properly" over time.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iEYEABECAAYFAlNEO1sACgkQMUfUDdst+ymMegCgy/ZpC010cymW2ZYgDxqjEEss
 3xUAoLA0Psv1z59hZv4EwrfStxzTiYAQ
 =waW7
 -----END PGP SIGNATURE-----

Merge tag 'staging-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull more staging patches from Greg KH:
 "Here are some more staging patches for 3.15-rc1.

  They include a late-submission of a wireless driver that a bunch of
  people seem to have the hardware for now.  As it's stand-alone, it
  should be fine (now passes the 0-day random build bot tests).

  There are also some fixes for the unisys drivers, as they were causing
  havoc on a number of different machines.  To resolve all of those
  issues, we just mark the driver as BROKEN now, and we can fix it up
  "properly" over time"

* tag 'staging-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
  staging: rtl8723au: The 8723 only has two paths
  Staging: unisys: mark drivers as BROKEN
  Staging: unisys: verify that a control channel exists
  staging: unisys: Add missing close parentheses in filexfer.c
  staging: r8723au: Fix build problem when RFKILL is not selected
  staging: r8723au: Fix randconfig build errors
  staging: r8723au: Turn on build of new driver
  staging: r8723au: Additional source patches
  staging: r8723au: Add source files for new driver - part 4
  staging: r8723au: Add source files for new driver - part 3
  staging: r8723au: Add source files for new driver - part 2
  staging: r8723au: Add source files for new driver - part 1
This commit is contained in:
Linus Torvalds 2014-04-08 12:37:29 -07:00
parent e4f30545a2 dda26427bd
commit 0afccc4cce
136 changed files with 89854 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/staging/Kconfig
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@ -50,6 +50,8 @@ source "drivers/staging/rtl8712/Kconfig"
source "drivers/staging/rtl8188eu/Kconfig"
source "drivers/staging/rtl8723au/Kconfig"
source "drivers/staging/rtl8821ae/Kconfig"
source "drivers/staging/rts5139/Kconfig"

1
drivers/staging/Makefile
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@ -17,6 +17,7 @@ obj-$(CONFIG_RTL8192U) += rtl8192u/
obj-$(CONFIG_RTL8192E) += rtl8192e/
obj-$(CONFIG_R8712U) += rtl8712/
obj-$(CONFIG_R8188EU) += rtl8188eu/
obj-$(CONFIG_R8723AU) += rtl8723au/
obj-$(CONFIG_R8821AE) += rtl8821ae/
obj-$(CONFIG_RTS5139) += rts5139/
obj-$(CONFIG_RTS5208) += rts5208/

38
drivers/staging/rtl8723au/Kconfig Normal file
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@ -0,0 +1,38 @@
config R8723AU
tristate "Realtek RTL8723AU Wireless LAN NIC driver"
depends on USB && WLAN && RFKILL
select WIRELESS_EXT
select WEXT_PRIV
select CFG80211
default n
---help---
This option adds the Realtek RTL8723AU USB device such as found in
the Lenovo Yogi 13 tablet. If built as a module, it will be called r8723au.
if R8723AU
config 8723AU_AP_MODE
bool "Realtek RTL8723AU AP mode"
default y
---help---
This option enables Access Point mode. Unless you know that your system
will never be used as an AP, or the target system has limited memory,
"Y" should be selected.
config 8723AU_P2P
bool "Realtek RTL8723AU Peer-to-peer mode"
default y
---help---
This option enables peer-to-peer mode for the r8723au driver. Unless you
know that peer-to-peer (P2P) mode will never be used, or the target system has
limited memory, "Y" should be selected.
config 8723AU_BT_COEXIST
bool "Realtek RTL8723AU BlueTooth Coexistence"
default y
---help---
This option enables icoexistence with BlueTooth communications for the r8723au driver.
Unless you know that this driver will never by used with BT, or the target system has
limited memory, "Y" should be selected.
endif

58
drivers/staging/rtl8723au/Makefile Normal file
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@ -0,0 +1,58 @@
r8723au-y := \
core/rtw_ap.o \
core/rtw_cmd.o \
core/rtw_efuse.o \
core/rtw_io.o \
core/rtw_ioctl_set.o \
core/rtw_ieee80211.o \
core/rtw_led.o \
core/rtw_mlme.o \
core/rtw_mlme_ext.o \
core/rtw_p2p.o \
core/rtw_pwrctrl.o \
core/rtw_recv.o \
core/rtw_security.o \
core/rtw_sreset.o \
core/rtw_sta_mgt.o \
core/rtw_xmit.o \
core/rtw_wlan_util.o \
hal/hal_com.o \
hal/hal_intf.o \
hal/Hal8723PwrSeq.o \
hal/Hal8723UHWImg_CE.o \
hal/HalDMOutSrc8723A_CE.o \
hal/HalHWImg8723A_BB.o \
hal/HalHWImg8723A_MAC.o \
hal/HalHWImg8723A_RF.o \
hal/HalPwrSeqCmd.o \
hal/odm_RegConfig8723A.o \
hal/rtl8723a_bt-coexist.o \
hal/odm_debug.o \
hal/odm_interface.o \
hal/odm_HWConfig.o \
hal/odm.o \
hal/rtl8723a_cmd.o \
hal/rtl8723a_dm.o \
hal/rtl8723a_hal_init.o \
hal/rtl8723a_phycfg.o \
hal/rtl8723a_rf6052.o \
hal/rtl8723a_rxdesc.o \
hal/rtl8723a_sreset.o \
hal/rtl8723a_xmit.o \
hal/rtl8723au_led.o \
hal/rtl8723au_recv.o \
hal/rtl8723au_xmit.o \
hal/usb_halinit.o \
hal/usb_ops_linux.o \
os_dep/ioctl_cfg80211.o \
os_dep/mlme_linux.o \
os_dep/osdep_service.o \
os_dep/os_intfs.o \
os_dep/recv_linux.o \
os_dep/usb_intf.o \
os_dep/usb_ops_linux.o \
os_dep/xmit_linux.o
obj-$(CONFIG_R8723AU) := r8723au.o
ccflags-y += -D__CHECK_ENDIAN__ -I$(src)/include

13
drivers/staging/rtl8723au/TODO Normal file
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@ -0,0 +1,13 @@
TODO:
- find and remove code valid only for 5 HGz. Many of the obvious
ones have been removed, but things like channel > 14 still exist.
- find and remove any code for other chips that is left over
- convert any remaining unusual variable types
- find codes that can use %pM and %Nph formatting
- checkpatch.pl fixes - most of the remaining ones are lines too long. Many
of them will require refactoring
- merge Realtek's bugfixes and new features into the driver
- switch to use MAC80211
Please send any patches to Greg Kroah-Hartman <gregkh@linux.com>,
Jes Sorensen <Jes.Sorensen@redhat.com>, and Larry Finger <Larry.Finger@lwfinger.net>.

2087
drivers/staging/rtl8723au/core/rtw_ap.c Normal file
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File diff suppressed because it is too large Load Diff

1876
drivers/staging/rtl8723au/core/rtw_cmd.c Normal file
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File diff suppressed because it is too large Load Diff

716
drivers/staging/rtl8723au/core/rtw_efuse.c Normal file
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@ -0,0 +1,716 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _RTW_EFUSE_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_efuse.h>
/*------------------------Define local variable------------------------------*/
/* */
#define REG_EFUSE_CTRL 0x0030
#define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */
/* */
/*-----------------------------------------------------------------------------
* Function: Efuse_PowerSwitch23a
*
* Overview: When we want to enable write operation, we should change to
* pwr on state. When we stop write, we should switch to 500k mode
* and disable LDO 2.5V.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/17/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
void
Efuse_PowerSwitch23a(
struct rtw_adapter * pAdapter,
u8 bWrite,
u8 PwrState)
{
pAdapter->HalFunc.EfusePowerSwitch(pAdapter, bWrite, PwrState);
}
/*-----------------------------------------------------------------------------
* Function: efuse_GetCurrentSize23a
*
* Overview: Get current efuse size!!!
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/16/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
u16
Efuse_GetCurrentSize23a(struct rtw_adapter *pAdapter, u8 efuseType)
{
u16 ret = 0;
ret = pAdapter->HalFunc.EfuseGetCurrentSize(pAdapter, efuseType);
return ret;
}
/* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */
u8
Efuse_CalculateWordCnts23a(u8 word_en)
{
u8 word_cnts = 0;
if (!(word_en & BIT(0))) word_cnts++; /* 0 : write enable */
if (!(word_en & BIT(1))) word_cnts++;
if (!(word_en & BIT(2))) word_cnts++;
if (!(word_en & BIT(3))) word_cnts++;
return word_cnts;
}
/* */
/* Description: */
/* Execute E-Fuse read byte operation. */
/* Refered from SD1 Richard. */
/* */
/* Assumption: */
/* 1. Boot from E-Fuse and successfully auto-load. */
/* 2. PASSIVE_LEVEL (USB interface) */
/* */
/* Created by Roger, 2008.10.21. */
/* */
void
ReadEFuseByte23a(struct rtw_adapter *Adapter, u16 _offset, u8 *pbuf)
{
u32 value32;
u8 readbyte;
u16 retry;
/* Write Address */
rtw_write8(Adapter, EFUSE_CTRL+1, (_offset & 0xff));
readbyte = rtw_read8(Adapter, EFUSE_CTRL+2);
rtw_write8(Adapter, EFUSE_CTRL+2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
/* Write bit 32 0 */
readbyte = rtw_read8(Adapter, EFUSE_CTRL+3);
rtw_write8(Adapter, EFUSE_CTRL+3, (readbyte & 0x7f));
/* Check bit 32 read-ready */
retry = 0;
value32 = rtw_read32(Adapter, EFUSE_CTRL);
/* while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10)) */
while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10000))
{
value32 = rtw_read32(Adapter, EFUSE_CTRL);
retry++;
}
/* 20100205 Joseph: Add delay suggested by SD1 Victor. */
/* This fix the problem that Efuse read error in high temperature condition. */
/* Designer says that there shall be some delay after ready bit is set, or the */
/* result will always stay on last data we read. */
udelay(50);
value32 = rtw_read32(Adapter, EFUSE_CTRL);
*pbuf = (u8)(value32 & 0xff);
}
/* */
/* Description: */
/* 1. Execute E-Fuse read byte operation according as map offset and */
/* save to E-Fuse table. */
/* 2. Refered from SD1 Richard. */
/* */
/* Assumption: */
/* 1. Boot from E-Fuse and successfully auto-load. */
/* 2. PASSIVE_LEVEL (USB interface) */
/* */
/* Created by Roger, 2008.10.21. */
/* */
/* 2008/12/12 MH 1. Reorganize code flow and reserve bytes. and add description. */
/* 2. Add efuse utilization collect. */
/* 2008/12/22 MH Read Efuse must check if we write section 1 data again!!! Sec1 */
/* write addr must be after sec5. */
/* */
void
efuse_ReadEFuse(struct rtw_adapter *Adapter, u8 efuseType,
u16 _offset, u16 _size_byte, u8 *pbuf);
void
efuse_ReadEFuse(struct rtw_adapter *Adapter, u8 efuseType,
u16 _offset, u16 _size_byte, u8 *pbuf)
{
Adapter->HalFunc.ReadEFuse(Adapter, efuseType, _offset,
_size_byte, pbuf);
}
void
EFUSE_GetEfuseDefinition23a(struct rtw_adapter *pAdapter, u8 efuseType,
u8 type, void *pOut)
{
pAdapter->HalFunc.EFUSEGetEfuseDefinition(pAdapter, efuseType,
type, pOut);
}
/*-----------------------------------------------------------------------------
* Function: EFUSE_Read1Byte23a
*
* Overview: Copy from WMAC fot EFUSE read 1 byte.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 09/23/2008 MHC Copy from WMAC.
*
*---------------------------------------------------------------------------*/
u8
EFUSE_Read1Byte23a(struct rtw_adapter *Adapter, u16 Address)
{
u8 data;
u8 Bytetemp = {0x00};
u8 temp = {0x00};
u32 k = 0;
u16 contentLen = 0;
EFUSE_GetEfuseDefinition23a(Adapter, EFUSE_WIFI,
TYPE_EFUSE_REAL_CONTENT_LEN,
(void *)&contentLen);
if (Address < contentLen) /* E-fuse 512Byte */
{
/* Write E-fuse Register address bit0~7 */
temp = Address & 0xFF;
rtw_write8(Adapter, EFUSE_CTRL+1, temp);
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2);
/* Write E-fuse Register address bit8~9 */
temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
rtw_write8(Adapter, EFUSE_CTRL+2, temp);
/* Write 0x30[31]= 0 */
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
temp = Bytetemp & 0x7F;
rtw_write8(Adapter, EFUSE_CTRL+3, temp);
/* Wait Write-ready (0x30[31]= 1) */
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
while(!(Bytetemp & 0x80))
{
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
k++;
if (k == 1000)
{
k = 0;
break;
}
}
data = rtw_read8(Adapter, EFUSE_CTRL);
return data;
}
else
return 0xFF;
}/* EFUSE_Read1Byte23a */
/*-----------------------------------------------------------------------------
* Function: EFUSE_Write1Byte
*
* Overview: Copy from WMAC fot EFUSE write 1 byte.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 09/23/2008 MHC Copy from WMAC.
*
*---------------------------------------------------------------------------*/
void
EFUSE_Write1Byte(
struct rtw_adapter * Adapter,
u16 Address,
u8 Value);
void
EFUSE_Write1Byte(
struct rtw_adapter * Adapter,
u16 Address,
u8 Value)
{
u8 Bytetemp = {0x00};
u8 temp = {0x00};
u32 k = 0;
u16 contentLen = 0;
/* RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr =%x Data =%x\n", Address, Value)); */
EFUSE_GetEfuseDefinition23a(Adapter, EFUSE_WIFI,
TYPE_EFUSE_REAL_CONTENT_LEN,
(void *)&contentLen);
if (Address < contentLen) /* E-fuse 512Byte */
{
rtw_write8(Adapter, EFUSE_CTRL, Value);
/* Write E-fuse Register address bit0~7 */
temp = Address & 0xFF;
rtw_write8(Adapter, EFUSE_CTRL+1, temp);
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2);
/* Write E-fuse Register address bit8~9 */
temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
rtw_write8(Adapter, EFUSE_CTRL+2, temp);
/* Write 0x30[31]= 1 */
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
temp = Bytetemp | 0x80;
rtw_write8(Adapter, EFUSE_CTRL+3, temp);
/* Wait Write-ready (0x30[31]= 0) */
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
while(Bytetemp & 0x80)
{
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
k++;
if (k == 100)
{
k = 0;
break;
}
}
}
}/* EFUSE_Write1Byte */
/* 11/16/2008 MH Read one byte from real Efuse. */
u8
efuse_OneByteRead23a(struct rtw_adapter *pAdapter, u16 addr, u8 *data)
{
u8 tmpidx = 0;
u8 bResult;
/* -----------------e-fuse reg ctrl --------------------------------- */
/* address */
rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
rtw_write8(pAdapter, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03)) |
(rtw_read8(pAdapter, EFUSE_CTRL+2)&0xFC));
rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72);/* read cmd */
while(!(0x80 &rtw_read8(pAdapter, EFUSE_CTRL+3)) && (tmpidx<100))
tmpidx++;
if (tmpidx < 100) {
*data = rtw_read8(pAdapter, EFUSE_CTRL);
bResult = true;
} else {
*data = 0xff;
bResult = false;
}
return bResult;
}
/* 11/16/2008 MH Write one byte to reald Efuse. */
u8
efuse_OneByteWrite23a(struct rtw_adapter *pAdapter, u16 addr, u8 data)
{
u8 tmpidx = 0;
u8 bResult;
/* RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr = %x Data =%x\n", addr, data)); */
/* return 0; */
/* -----------------e-fuse reg ctrl --------------------------------- */
/* address */
rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
rtw_write8(pAdapter, EFUSE_CTRL+2,
(rtw_read8(pAdapter, EFUSE_CTRL+2)&0xFC)|(u8)((addr>>8)&0x03));
rtw_write8(pAdapter, EFUSE_CTRL, data);/* data */
rtw_write8(pAdapter, EFUSE_CTRL+3, 0xF2);/* write cmd */
while((0x80 & rtw_read8(pAdapter, EFUSE_CTRL+3)) && (tmpidx<100)) {
tmpidx++;
}
if (tmpidx<100)
{
bResult = true;
}
else
{
bResult = false;
}
return bResult;
}
int
Efuse_PgPacketRead23a(struct rtw_adapter *pAdapter, u8 offset, u8 *data)
{
int ret = 0;
ret = pAdapter->HalFunc.Efuse_PgPacketRead23a(pAdapter, offset, data);
return ret;
}
int
Efuse_PgPacketWrite23a(struct rtw_adapter *pAdapter, u8 offset,
u8 word_en, u8 *data)
{
int ret;
ret = pAdapter->HalFunc.Efuse_PgPacketWrite23a(pAdapter, offset,
word_en, data);
return ret;
}
/*-----------------------------------------------------------------------------
* Function: efuse_WordEnableDataRead23a
*
* Overview: Read allowed word in current efuse section data.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/16/2008 MHC Create Version 0.
* 11/21/2008 MHC Fix Write bug when we only enable late word.
*
*---------------------------------------------------------------------------*/
void
efuse_WordEnableDataRead23a(u8 word_en,
u8 *sourdata,
u8 *targetdata)
{
if (!(word_en&BIT(0)))
{
targetdata[0] = sourdata[0];
targetdata[1] = sourdata[1];
}
if (!(word_en&BIT(1)))
{
targetdata[2] = sourdata[2];
targetdata[3] = sourdata[3];
}
if (!(word_en&BIT(2)))
{
targetdata[4] = sourdata[4];
targetdata[5] = sourdata[5];
}
if (!(word_en&BIT(3)))
{
targetdata[6] = sourdata[6];
targetdata[7] = sourdata[7];
}
}
u8
Efuse_WordEnableDataWrite23a(struct rtw_adapter *pAdapter, u16 efuse_addr,
u8 word_en, u8 *data)
{
u8 ret = 0;
ret = pAdapter->HalFunc.Efuse_WordEnableDataWrite23a(pAdapter, efuse_addr,
word_en, data);
return ret;
}
static u8 efuse_read8(struct rtw_adapter *padapter, u16 address, u8 *value)
{
return efuse_OneByteRead23a(padapter, address, value);
}
static u8 efuse_write8(struct rtw_adapter *padapter, u16 address, u8 *value)
{
return efuse_OneByteWrite23a(padapter, address, *value);
}
/*
* read/wirte raw efuse data
*/
u8 rtw_efuse_access23a(struct rtw_adapter *padapter, u8 bWrite, u16 start_addr,
u16 cnts, u8 *data)
{
int i = 0;
u16 real_content_len = 0, max_available_size = 0;
u8 res = _FAIL ;
u8 (*rw8)(struct rtw_adapter *, u16, u8*);
EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI,
TYPE_EFUSE_REAL_CONTENT_LEN,
(void *)&real_content_len);
EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI,
TYPE_AVAILABLE_EFUSE_BYTES_TOTAL,
(void *)&max_available_size);
if (start_addr > real_content_len)
return _FAIL;
if (true == bWrite) {
if ((start_addr + cnts) > max_available_size)
return _FAIL;
rw8 = &efuse_write8;
} else
rw8 = &efuse_read8;
Efuse_PowerSwitch23a(padapter, bWrite, true);
/* e-fuse one byte read / write */
for (i = 0; i < cnts; i++) {
if (start_addr >= real_content_len) {
res = _FAIL;
break;
}
res = rw8(padapter, start_addr++, data++);
if (_FAIL == res) break;
}
Efuse_PowerSwitch23a(padapter, bWrite, false);
return res;
}
/* */
u16 efuse_GetMaxSize23a(struct rtw_adapter *padapter)
{
u16 max_size;
EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI,
TYPE_AVAILABLE_EFUSE_BYTES_TOTAL,
(void *)&max_size);
return max_size;
}
/* */
u8 efuse_GetCurrentSize23a(struct rtw_adapter *padapter, u16 *size)
{
Efuse_PowerSwitch23a(padapter, false, true);
*size = Efuse_GetCurrentSize23a(padapter, EFUSE_WIFI);
Efuse_PowerSwitch23a(padapter, false, false);
return _SUCCESS;
}
/* */
u8 rtw_efuse_map_read23a(struct rtw_adapter *padapter, u16 addr, u16 cnts, u8 *data)
{
u16 mapLen = 0;
EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI,
TYPE_EFUSE_MAP_LEN, (void *)&mapLen);
if ((addr + cnts) > mapLen)
return _FAIL;
Efuse_PowerSwitch23a(padapter, false, true);
efuse_ReadEFuse(padapter, EFUSE_WIFI, addr, cnts, data);
Efuse_PowerSwitch23a(padapter, false, false);
return _SUCCESS;
}
u8 rtw_BT_efuse_map_read23a(struct rtw_adapter *padapter, u16 addr, u16 cnts, u8 *data)
{
u16 mapLen = 0;
EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
TYPE_EFUSE_MAP_LEN, (void *)&mapLen);
if ((addr + cnts) > mapLen)
return _FAIL;
Efuse_PowerSwitch23a(padapter, false, true);
efuse_ReadEFuse(padapter, EFUSE_BT, addr, cnts, data);
Efuse_PowerSwitch23a(padapter, false, false);
return _SUCCESS;
}
/*-----------------------------------------------------------------------------
* Function: Efuse_ReadAllMap
*
* Overview: Read All Efuse content
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/11/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
void
Efuse_ReadAllMap(struct rtw_adapter *pAdapter, u8 efuseType, u8 *Efuse);
void
Efuse_ReadAllMap(struct rtw_adapter *pAdapter, u8 efuseType, u8 *Efuse)
{
u16 mapLen = 0;
Efuse_PowerSwitch23a(pAdapter, false, true);
EFUSE_GetEfuseDefinition23a(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN,
(void *)&mapLen);
efuse_ReadEFuse(pAdapter, efuseType, 0, mapLen, Efuse);
Efuse_PowerSwitch23a(pAdapter, false, false);
}
/*-----------------------------------------------------------------------------
* Function: efuse_ShadowRead1Byte
* efuse_ShadowRead2Byte
* efuse_ShadowRead4Byte
*
* Overview: Read from efuse init map by one/two/four bytes !!!!!
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/12/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
static void
efuse_ShadowRead1Byte(
struct rtw_adapter * pAdapter,
u16 Offset,
u8 *Value)
{
struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
*Value = pEEPROM->efuse_eeprom_data[Offset];
} /* EFUSE_ShadowRead23a1Byte */
/* Read Two Bytes */
static void
efuse_ShadowRead2Byte(
struct rtw_adapter * pAdapter,
u16 Offset,
u16 *Value)
{
struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
*Value = pEEPROM->efuse_eeprom_data[Offset];
*Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8;
} /* EFUSE_ShadowRead23a2Byte */
/* Read Four Bytes */
static void
efuse_ShadowRead4Byte(
struct rtw_adapter * pAdapter,
u16 Offset,
u32 *Value)
{
struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
*Value = pEEPROM->efuse_eeprom_data[Offset];
*Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8;
*Value |= pEEPROM->efuse_eeprom_data[Offset+2]<<16;
*Value |= pEEPROM->efuse_eeprom_data[Offset+3]<<24;
} /* efuse_ShadowRead4Byte */
/*-----------------------------------------------------------------------------
* Function: EFUSE_ShadowMapUpdate23a
*
* Overview: Transfer current EFUSE content to shadow init and modify map.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/13/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
void EFUSE_ShadowMapUpdate23a(struct rtw_adapter *pAdapter, u8 efuseType)
{
struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
u16 mapLen = 0;
EFUSE_GetEfuseDefinition23a(pAdapter, efuseType,
TYPE_EFUSE_MAP_LEN, (void *)&mapLen);
if (pEEPROM->bautoload_fail_flag == true)
memset(pEEPROM->efuse_eeprom_data, 0xFF, mapLen);
else
Efuse_ReadAllMap(pAdapter, efuseType,
pEEPROM->efuse_eeprom_data);
}/* EFUSE_ShadowMapUpdate23a */
/*-----------------------------------------------------------------------------
* Function: EFUSE_ShadowRead23a
*
* Overview: Read from efuse init map !!!!!
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/12/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
void
EFUSE_ShadowRead23a(
struct rtw_adapter * pAdapter,
u8 Type,
u16 Offset,
u32 *Value )
{
if (Type == 1)
efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value);
else if (Type == 2)
efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value);
else if (Type == 4)
efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value);
} /* EFUSE_ShadowRead23a */

1861
drivers/staging/rtl8723au/core/rtw_ieee80211.c Normal file
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File diff suppressed because it is too large Load Diff

266
drivers/staging/rtl8723au/core/rtw_io.c Normal file
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@ -0,0 +1,266 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/*
The purpose of rtw_io.c
a. provides the API
b. provides the protocol engine
c. provides the software interface between caller and the hardware interface
Compiler Flag Option:
1. For USB:
a. USE_ASYNC_IRP: Both sync/async operations are provided.
Only sync read/rtw_write_mem operations are provided.
jackson@realtek.com.tw
*/
#define _RTW_IO_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_io.h>
#include <osdep_intf.h>
#include <usb_ops.h>
u8 _rtw_read823a(struct rtw_adapter *adapter, u32 addr)
{
u8 r_val;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
r_val = pintfhdl->io_ops._read8(pintfhdl, addr);
return r_val;
}
u16 _rtw_read1623a(struct rtw_adapter *adapter, u32 addr)
{
u16 r_val;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
r_val = pintfhdl->io_ops._read16(pintfhdl, addr);
return le16_to_cpu(r_val);
}
u32 _rtw_read3223a(struct rtw_adapter *adapter, u32 addr)
{
u32 r_val;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
r_val = pintfhdl->io_ops._read32(pintfhdl, addr);
return le32_to_cpu(r_val);
}
int _rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
int ret;
ret = pintfhdl->io_ops._write8(pintfhdl, addr, val);
return RTW_STATUS_CODE23a(ret);
}
int _rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
int ret;
val = cpu_to_le16(val);
ret = pintfhdl->io_ops._write16(pintfhdl, addr, val);
return RTW_STATUS_CODE23a(ret);
}
int _rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
int ret;
val = cpu_to_le32(val);
ret = pintfhdl->io_ops._write32(pintfhdl, addr, val);
return RTW_STATUS_CODE23a(ret);
}
int _rtw_writeN23a(struct rtw_adapter *adapter, u32 addr , u32 length , u8 *pdata)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = (struct intf_hdl*)&pio_priv->intf;
int ret;
ret = pintfhdl->io_ops._writeN(pintfhdl, addr, length, pdata);
return RTW_STATUS_CODE23a(ret);
}
int _rtw_write823a_async23a(struct rtw_adapter *adapter, u32 addr, u8 val)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
int ret;
ret = pintfhdl->io_ops._write8_async(pintfhdl, addr, val);
return RTW_STATUS_CODE23a(ret);
}
int _rtw_write1623a_async(struct rtw_adapter *adapter, u32 addr, u16 val)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
int ret;
val = cpu_to_le16(val);
ret = pintfhdl->io_ops._write16_async(pintfhdl, addr, val);
return RTW_STATUS_CODE23a(ret);
}
int _rtw_write3223a_async23a(struct rtw_adapter *adapter, u32 addr, u32 val)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
int ret;
val = cpu_to_le32(val);
ret = pintfhdl->io_ops._write32_async(pintfhdl, addr, val);
return RTW_STATUS_CODE23a(ret);
}
void _rtw_read_mem23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
if ((adapter->bDriverStopped == true) ||
(adapter->bSurpriseRemoved == true)) {
RT_TRACE(_module_rtl871x_io_c_, _drv_info_,
("rtw_read_mem:bDriverStopped(%d) OR "
"bSurpriseRemoved(%d)", adapter->bDriverStopped,
adapter->bSurpriseRemoved));
return;
}
pintfhdl->io_ops._read_mem(pintfhdl, addr, cnt, pmem);
}
void _rtw_write_mem23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
pintfhdl->io_ops._write_mem(pintfhdl, addr, cnt, pmem);
}
void _rtw_read_port23a(struct rtw_adapter *adapter, u32 addr, u32 cnt,
struct recv_buf *rbuf)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
if ((adapter->bDriverStopped == true) ||
(adapter->bSurpriseRemoved == true)) {
RT_TRACE(_module_rtl871x_io_c_, _drv_info_,
("rtw_read_port:bDriverStopped(%d) OR "
"bSurpriseRemoved(%d)", adapter->bDriverStopped,
adapter->bSurpriseRemoved));
return;
}
pintfhdl->io_ops._read_port(pintfhdl, addr, cnt, rbuf);
}
void _rtw_read_port23a_cancel(struct rtw_adapter *adapter)
{
void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
_read_port_cancel = pintfhdl->io_ops._read_port_cancel;
if (_read_port_cancel)
_read_port_cancel(pintfhdl);
}
u32 _rtw_write_port23a(struct rtw_adapter *adapter, u32 addr, u32 cnt,
struct xmit_buf *xbuf)
{
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
u32 ret = _SUCCESS;
ret = pintfhdl->io_ops._write_port(pintfhdl, addr, cnt, xbuf);
return ret;
}
u32 _rtw_write_port23a_and_wait23a(struct rtw_adapter *adapter, u32 addr, u32 cnt,
struct xmit_buf *pxmitbuf, int timeout_ms)
{
int ret = _SUCCESS;
struct submit_ctx sctx;
rtw_sctx_init23a(&sctx, timeout_ms);
pxmitbuf->sctx = &sctx;
ret = _rtw_write_port23a(adapter, addr, cnt, pxmitbuf);
if (ret == _SUCCESS)
ret = rtw_sctx_wait23a(&sctx);
return ret;
}
void _rtw_write_port23a_cancel(struct rtw_adapter *adapter)
{
void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &pio_priv->intf;
_write_port_cancel = pintfhdl->io_ops._write_port_cancel;
if (_write_port_cancel)
_write_port_cancel(pintfhdl);
}
int rtw_init_io_priv23a(struct rtw_adapter *padapter,
void (*set_intf_ops)(struct _io_ops *pops))
{
struct io_priv *piopriv = &padapter->iopriv;
struct intf_hdl *pintf = &piopriv->intf;
if (set_intf_ops == NULL)
return _FAIL;
piopriv->padapter = padapter;
pintf->padapter = padapter;
pintf->pintf_dev = adapter_to_dvobj(padapter);
set_intf_ops(&pintf->io_ops);
return _SUCCESS;
}

601
drivers/staging/rtl8723au/core/rtw_ioctl_set.c Normal file
View File

@ -0,0 +1,601 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _RTW_IOCTL_SET_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_ioctl_set.h>
#include <hal_intf.h>
#include <usb_osintf.h>
#include <usb_ops.h>
#include <linux/ieee80211.h>
u8 rtw_do_join23a(struct rtw_adapter *padapter)
{
struct list_head *plist, *phead;
u8* pibss = NULL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct rtw_queue *queue = &pmlmepriv->scanned_queue;
u8 ret = _SUCCESS;
spin_lock_bh(&pmlmepriv->scanned_queue.lock);
phead = get_list_head(queue);
plist = phead->next;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("\n rtw_do_join23a: phead = %p; plist = %p\n\n\n",
phead, plist));
pmlmepriv->cur_network.join_res = -2;
set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
pmlmepriv->to_join = true;
if (_rtw_queue_empty23a(queue) == true) {
spin_unlock_bh(&pmlmepriv->scanned_queue.lock);
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
/* when set_ssid/set_bssid for rtw_do_join23a(), but
scanning queue is empty */
/* we try to issue sitesurvey firstly */
if (pmlmepriv->LinkDetectInfo.bBusyTraffic == false ||
rtw_to_roaming(padapter) > 0) {
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("rtw_do_join23a(): site survey if scanned_queue "
"is empty\n."));
/* submit site_survey23a_cmd */
ret = rtw_sitesurvey_cmd23a(padapter,
&pmlmepriv->assoc_ssid, 1,
NULL, 0);
if (ret != _SUCCESS) {
pmlmepriv->to_join = false;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("rtw_do_join23a(): site survey return "
"error\n."));
}
} else {
pmlmepriv->to_join = false;
ret = _FAIL;
}
goto exit;
} else {
int select_ret;
spin_unlock_bh(&pmlmepriv->scanned_queue.lock);
select_ret = rtw_select_and_join_from_scanned_queue23a(pmlmepriv);
if (select_ret == _SUCCESS) {
pmlmepriv->to_join = false;
mod_timer(&pmlmepriv->assoc_timer,
jiffies + msecs_to_jiffies(MAX_JOIN_TIMEOUT));
} else {
if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == true) {
struct wlan_bssid_ex *pdev_network;
/* submit createbss_cmd to change to a
ADHOC_MASTER */
/* pmlmepriv->lock has been acquired by
caller... */
pdev_network =
&padapter->registrypriv.dev_network;
pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
pibss = padapter->registrypriv.dev_network.MacAddress;
memcpy(&pdev_network->Ssid,
&pmlmepriv->assoc_ssid,
sizeof(struct cfg80211_ssid));
rtw_update_registrypriv_dev_network23a(padapter);
rtw_generate_random_ibss23a(pibss);
if (rtw_createbss_cmd23a(padapter) != _SUCCESS) {
RT_TRACE(_module_rtl871x_ioctl_set_c_,
_drv_err_,
("***Error =>do_goin: rtw_creat"
"ebss_cmd status FAIL***\n"));
ret = false;
goto exit;
}
pmlmepriv->to_join = false;
RT_TRACE(_module_rtl871x_ioctl_set_c_,
_drv_info_,
("***Error => rtw_select_and_join_from"
"_scanned_queue FAIL under STA_Mode"
"***\n "));
} else {
/* can't associate ; reset under-linking */
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
/* when set_ssid/set_bssid for rtw_do_join23a(),
but there are no desired bss in scanning
queue */
/* we try to issue sitesurvey firstly */
if (pmlmepriv->LinkDetectInfo.bBusyTraffic ==
false || rtw_to_roaming(padapter) > 0) {
/* DBG_8723A("rtw_do_join23a() when no "
"desired bss in scanning queue\n");
*/
ret = rtw_sitesurvey_cmd23a(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0);
if (ret != _SUCCESS) {
pmlmepriv->to_join = false;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("do_join(): site survey return error\n."));
}
} else {
ret = _FAIL;
pmlmepriv->to_join = false;
}
}
}
}
exit:
return ret;
}
u8 rtw_set_802_11_ssid23a(struct rtw_adapter* padapter, struct cfg80211_ssid *ssid)
{
u8 status = _SUCCESS;
u32 cur_time = 0;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct wlan_network *pnetwork = &pmlmepriv->cur_network;
DBG_8723A_LEVEL(_drv_always_, "set ssid [%s] fw_state = 0x%08x\n",
ssid->ssid, get_fwstate(pmlmepriv));
if (padapter->hw_init_completed == false) {
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("set_ssid: hw_init_completed == false =>exit!!!\n"));
status = _FAIL;
goto exit;
}
spin_lock_bh(&pmlmepriv->lock);
DBG_8723A("Set SSID under fw_state = 0x%08x\n", get_fwstate(pmlmepriv));
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true) {
goto handle_tkip_countermeasure;
} else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == true) {
goto release_mlme_lock;
}
if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == true)
{
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("set_ssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n"));
if ((pmlmepriv->assoc_ssid.ssid_len == ssid->ssid_len) &&
!memcmp(&pmlmepriv->assoc_ssid.ssid, ssid->ssid,
ssid->ssid_len)) {
if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == false))
{
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("Set SSID is the same ssid, fw_state = 0x%08x\n",
get_fwstate(pmlmepriv)));
if (rtw_is_same_ibss23a(padapter, pnetwork) == false)
{
/* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */
rtw_disassoc_cmd23a(padapter, 0, true);
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
rtw_indicate_disconnect23a(padapter);
rtw_free_assoc_resources23a(padapter, 1);
if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true) {
_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
}
} else {
goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
}
} else {
rtw_lps_ctrl_wk_cmd23a(padapter, LPS_CTRL_JOINBSS, 1);
}
} else {
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("Set SSID not the same ssid\n"));
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("set_ssid =[%s] len = 0x%x\n", ssid->ssid,
(unsigned int)ssid->ssid_len));
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("assoc_ssid =[%s] len = 0x%x\n",
pmlmepriv->assoc_ssid.ssid,
(unsigned int)pmlmepriv->assoc_ssid.ssid_len));
rtw_disassoc_cmd23a(padapter, 0, true);
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
rtw_indicate_disconnect23a(padapter);
rtw_free_assoc_resources23a(padapter, 1);
if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true) {
_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
}
}
}
handle_tkip_countermeasure:
if (padapter->securitypriv.btkip_countermeasure == true) {
cur_time = jiffies;
if ((cur_time - padapter->securitypriv.btkip_countermeasure_time) > 60 * HZ)
{
padapter->securitypriv.btkip_countermeasure = false;
padapter->securitypriv.btkip_countermeasure_time = 0;
}
else
{
status = _FAIL;
goto release_mlme_lock;
}
}
memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(struct cfg80211_ssid));
pmlmepriv->assoc_by_bssid = false;
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true) {
pmlmepriv->to_join = true;
}
else {
status = rtw_do_join23a(padapter);
}
release_mlme_lock:
spin_unlock_bh(&pmlmepriv->lock);
exit:
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("-rtw_set_802_11_ssid23a: status =%d\n", status));
return status;
}
u8 rtw_set_802_11_infrastructure_mode23a(struct rtw_adapter* padapter,
enum ndis_802_11_net_infra networktype)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct wlan_network *cur_network = &pmlmepriv->cur_network;
enum ndis_802_11_net_infra* pold_state = &cur_network->network.InfrastructureMode;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_notice_,
("+rtw_set_802_11_infrastructure_mode23a: old =%d new =%d fw_state = 0x%08x\n",
*pold_state, networktype, get_fwstate(pmlmepriv)));
if (*pold_state != networktype)
{
spin_lock_bh(&pmlmepriv->lock);
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, (" change mode!"));
/* DBG_8723A("change mode, old_mode =%d, new_mode =%d, fw_state = 0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); */
if (*pold_state == Ndis802_11APMode)
{
/* change to other mode from Ndis802_11APMode */
cur_network->join_res = -1;
#ifdef CONFIG_8723AU_AP_MODE
stop_ap_mode23a(padapter);
#endif
}
if ((check_fwstate(pmlmepriv, _FW_LINKED) == true) ||(*pold_state == Ndis802_11IBSS))
rtw_disassoc_cmd23a(padapter, 0, true);
if ((check_fwstate(pmlmepriv, _FW_LINKED) == true) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true))
rtw_free_assoc_resources23a(padapter, 1);
if ((*pold_state == Ndis802_11Infrastructure) ||(*pold_state == Ndis802_11IBSS))
{
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
{
rtw_indicate_disconnect23a(padapter); /* will clr Linked_state; before this function, we must have chked whether issue dis-assoc_cmd or not */
}
}
*pold_state = networktype;
_clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE);
switch (networktype)
{
case Ndis802_11IBSS:
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
break;
case Ndis802_11Infrastructure:
set_fwstate(pmlmepriv, WIFI_STATION_STATE);
break;
case Ndis802_11APMode:
set_fwstate(pmlmepriv, WIFI_AP_STATE);
#ifdef CONFIG_8723AU_AP_MODE
start_ap_mode23a(padapter);
/* rtw_indicate_connect23a(padapter); */
#endif
break;
case Ndis802_11AutoUnknown:
case Ndis802_11InfrastructureMax:
break;
}
/* SecClearAllKeys(adapter); */
/* RT_TRACE(COMP_OID_SET, DBG_LOUD, ("set_infrastructure: fw_state:%x after changing mode\n", */
/* get_fwstate(pmlmepriv))); */
spin_unlock_bh(&pmlmepriv->lock);
}
return true;
}
u8 rtw_set_802_11_bssid23a_list_scan(struct rtw_adapter *padapter,
struct cfg80211_ssid *pssid, int ssid_max_num)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
u8 res = true;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("+rtw_set_802_11_bssid23a_list_scan(), fw_state =%x\n",
get_fwstate(pmlmepriv)));
if (!padapter) {
res = false;
goto exit;
}
if (padapter->hw_init_completed == false) {
res = false;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("\n === rtw_set_802_11_bssid23a_list_scan:"
"hw_init_completed == false ===\n"));
goto exit;
}
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) ||
(pmlmepriv->LinkDetectInfo.bBusyTraffic == true)) {
/* Scan or linking is in progress, do nothing. */
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("rtw_set_802_11_bssid23a_list_scan fail since fw_state "
"= %x\n", get_fwstate(pmlmepriv)));
res = true;
if (check_fwstate(pmlmepriv,
(_FW_UNDER_SURVEY|_FW_UNDER_LINKING))) {
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("\n###_FW_UNDER_SURVEY|_FW_UNDER_LINKING\n"));
} else {
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("\n###pmlmepriv->sitesurveyctrl.traffic_"
"busy == true\n"));
}
} else {
if (rtw_is_scan_deny(padapter)) {
DBG_8723A(FUNC_ADPT_FMT": scan deny\n",
FUNC_ADPT_ARG(padapter));
return _SUCCESS;
}
spin_lock_bh(&pmlmepriv->lock);
res = rtw_sitesurvey_cmd23a(padapter, pssid, ssid_max_num,
NULL, 0);
spin_unlock_bh(&pmlmepriv->lock);
}
exit:
return res;
}
u8 rtw_set_802_11_authentication_mode23a(struct rtw_adapter* padapter,
enum ndis_802_11_auth_mode authmode)
{
struct security_priv *psecuritypriv = &padapter->securitypriv;
int res;
u8 ret;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("set_802_11_auth.mode(): mode =%x\n", authmode));
psecuritypriv->ndisauthtype = authmode;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("rtw_set_802_11_authentication_mode23a:"
"psecuritypriv->ndisauthtype =%d",
psecuritypriv->ndisauthtype));
if (psecuritypriv->ndisauthtype > 3)
psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
res = rtw_set_auth23a(padapter, psecuritypriv);
if (res == _SUCCESS)
ret = true;
else
ret = false;
return ret;
}
u8 rtw_set_802_11_add_wep23a(struct rtw_adapter* padapter,
struct ndis_802_11_wep *wep)
{
u8 bdefaultkey;
u8 btransmitkey;
int keyid, res;
struct security_priv *psecuritypriv = &padapter->securitypriv;
u8 ret = _SUCCESS;
bdefaultkey = (wep->KeyIndex & 0x40000000) > 0 ? false : true;
btransmitkey = (wep->KeyIndex & 0x80000000) > 0 ? true : false;
keyid = wep->KeyIndex & 0x3fffffff;
if (keyid >= 4) {
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
("MgntActrtw_set_802_11_add_wep23a:keyid>4 =>fail\n"));
ret = false;
goto exit;
}
switch (wep->KeyLength)
{
case 5:
psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("MgntActrtw_set_802_11_add_wep23a:wep->KeyLength = 5\n"));
break;
case 13:
psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("MgntActrtw_set_802_11_add_wep23a:wep->KeyLength = 13\n"));
break;
default:
psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("MgntActrtw_set_802_11_add_wep23a:wep->KeyLength!= 5 "
"or 13\n"));
break;
}
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("rtw_set_802_11_add_wep23a:befor memcpy, wep->KeyLength = 0x%x "
"wep->KeyIndex = 0x%x keyid =%x\n",
wep->KeyLength, wep->KeyIndex, keyid));
memcpy(&psecuritypriv->dot11DefKey[keyid].skey[0],
&wep->KeyMaterial, wep->KeyLength);
psecuritypriv->dot11DefKeylen[keyid] = wep->KeyLength;
psecuritypriv->dot11PrivacyKeyIndex = keyid;
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
("rtw_set_802_11_add_wep23a:security key material : %x %x %x %x "
"%x %x %x %x %x %x %x %x %x\n",
psecuritypriv->dot11DefKey[keyid].skey[0],
psecuritypriv->dot11DefKey[keyid].skey[1],
psecuritypriv->dot11DefKey[keyid].skey[2],
psecuritypriv->dot11DefKey[keyid].skey[3],
psecuritypriv->dot11DefKey[keyid].skey[4],
psecuritypriv->dot11DefKey[keyid].skey[5],
psecuritypriv->dot11DefKey[keyid].skey[6],
psecuritypriv->dot11DefKey[keyid].skey[7],
psecuritypriv->dot11DefKey[keyid].skey[8],
psecuritypriv->dot11DefKey[keyid].skey[9],
psecuritypriv->dot11DefKey[keyid].skey[10],
psecuritypriv->dot11DefKey[keyid].skey[11],
psecuritypriv->dot11DefKey[keyid].skey[12]));
res = rtw_set_key23a(padapter, psecuritypriv, keyid, 1);
if (res == _FAIL)
ret = false;
exit:
return ret;
}
/*
* rtw_get_cur_max_rate23a -
* @adapter: pointer to _adapter structure
*
* Return 0 or 100Kbps
*/
u16 rtw_get_cur_max_rate23a(struct rtw_adapter *adapter)
{
int i = 0;
u8 *p;
u16 rate = 0, max_rate = 0;
struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
struct registry_priv *pregistrypriv = &adapter->registrypriv;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct wlan_bssid_ex *pcur_bss = &pmlmepriv->cur_network.network;
struct ieee80211_ht_cap *pht_capie;
u8 rf_type = 0;
u8 bw_40MHz = 0, short_GI_20 = 0, short_GI_40 = 0;
u16 mcs_rate = 0;
u32 ht_ielen = 0;
if (!check_fwstate(pmlmepriv, _FW_LINKED) &&
!check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))
return 0;
if (pmlmeext->cur_wireless_mode & (WIRELESS_11_24N|WIRELESS_11_5N)) {
p = rtw_get_ie23a(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_,
&ht_ielen, pcur_bss->IELength - 12);
if (p && ht_ielen > 0) {
pht_capie = (struct ieee80211_ht_cap *)(p + 2);
memcpy(&mcs_rate, &pht_capie->mcs, 2);
/* bw_40MHz = (pht_capie->cap_info&
IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1:0; */
/* cur_bwmod is updated by beacon, pmlmeinfo is
updated by association response */
bw_40MHz = (pmlmeext->cur_bwmode &&
(HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH &
pmlmeinfo->HT_info.infos[0])) ? 1:0;
/* short_GI = (pht_capie->cap_info & (IEEE80211_HT_CAP
_SGI_20|IEEE80211_HT_CAP_SGI_40)) ? 1 : 0; */
short_GI_20 = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info&IEEE80211_HT_CAP_SGI_20) ? 1:0;
short_GI_40 = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info&IEEE80211_HT_CAP_SGI_40) ? 1:0;
rtw23a_hal_get_hwreg(adapter, HW_VAR_RF_TYPE,
(u8 *)(&rf_type));
max_rate = rtw_mcs_rate23a(rf_type, bw_40MHz &
pregistrypriv->cbw40_enable,
short_GI_20, short_GI_40,
pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate
);
}
} else {
while ((pcur_bss->SupportedRates[i] != 0) &&
(pcur_bss->SupportedRates[i] != 0xFF)) {
rate = pcur_bss->SupportedRates[i] & 0x7F;
if (rate>max_rate)
max_rate = rate;
i++;
}
max_rate = max_rate * 10 / 2;
}
return max_rate;
}

1899
drivers/staging/rtl8723au/core/rtw_led.c Normal file
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File diff suppressed because it is too large Load Diff

2500
drivers/staging/rtl8723au/core/rtw_mlme.c Normal file
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File diff suppressed because it is too large Load Diff

9990
drivers/staging/rtl8723au/core/rtw_mlme_ext.c Normal file
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File diff suppressed because it is too large Load Diff

4001
drivers/staging/rtl8723au/core/rtw_p2p.c Normal file
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689
drivers/staging/rtl8723au/core/rtw_pwrctrl.c Normal file
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@ -0,0 +1,689 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _RTW_PWRCTRL_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <osdep_intf.h>
#ifdef CONFIG_8723AU_BT_COEXIST
#include <rtl8723a_hal.h>
#endif
void ips_enter23a(struct rtw_adapter * padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
down(&pwrpriv->lock);
pwrpriv->bips_processing = true;
/* syn ips_mode with request */
pwrpriv->ips_mode = pwrpriv->ips_mode_req;
pwrpriv->ips_enter23a_cnts++;
DBG_8723A("==>ips_enter23a cnts:%d\n", pwrpriv->ips_enter23a_cnts);
#ifdef CONFIG_8723AU_BT_COEXIST
BTDM_TurnOffBtCoexistBeforeEnterIPS(padapter);
#endif
if (rf_off == pwrpriv->change_rfpwrstate)
{
pwrpriv->bpower_saving = true;
DBG_8723A_LEVEL(_drv_always_, "nolinked power save enter\n");
if (pwrpriv->ips_mode == IPS_LEVEL_2)
pwrpriv->bkeepfwalive = true;
rtw_ips_pwr_down23a(padapter);
pwrpriv->rf_pwrstate = rf_off;
}
pwrpriv->bips_processing = false;
up(&pwrpriv->lock);
}
int ips_leave23a(struct rtw_adapter * padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
int result = _SUCCESS;
int keyid;
down(&pwrpriv->lock);
if ((pwrpriv->rf_pwrstate == rf_off) &&!pwrpriv->bips_processing)
{
pwrpriv->bips_processing = true;
pwrpriv->change_rfpwrstate = rf_on;
pwrpriv->ips_leave23a_cnts++;
DBG_8723A("==>ips_leave23a cnts:%d\n", pwrpriv->ips_leave23a_cnts);
if ((result = rtw_ips_pwr_up23a(padapter)) == _SUCCESS) {
pwrpriv->rf_pwrstate = rf_on;
}
DBG_8723A_LEVEL(_drv_always_, "nolinked power save leave\n");
if ((_WEP40_ == psecuritypriv->dot11PrivacyAlgrthm) ||(_WEP104_ == psecuritypriv->dot11PrivacyAlgrthm))
{
DBG_8723A("==>%s, channel(%d), processing(%x)\n", __func__, padapter->mlmeextpriv.cur_channel, pwrpriv->bips_processing);
set_channel_bwmode23a(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20);
for (keyid = 0;keyid<4;keyid++) {
if (pmlmepriv->key_mask & CHKBIT(keyid)) {
if (keyid == psecuritypriv->dot11PrivacyKeyIndex)
result = rtw_set_key23a(padapter, psecuritypriv, keyid, 1);
else
result = rtw_set_key23a(padapter, psecuritypriv, keyid, 0);
}
}
}
DBG_8723A("==> ips_leave23a.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c));
pwrpriv->bips_processing = false;
pwrpriv->bkeepfwalive = false;
pwrpriv->bpower_saving = false;
}
up(&pwrpriv->lock);
return result;
}
static bool rtw_pwr_unassociated_idle(struct rtw_adapter *adapter)
{
struct rtw_adapter *buddy = adapter->pbuddy_adapter;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct xmit_priv *pxmit_priv = &adapter->xmitpriv;
struct wifidirect_info *pwdinfo = &adapter->wdinfo;
bool ret = false;
if (time_after_eq(adapter->pwrctrlpriv.ips_deny_time, jiffies))
goto exit;
if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR)
|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS)
|| check_fwstate(pmlmepriv, WIFI_AP_STATE)
|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE)
|| !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
) {
goto exit;
}
/* consider buddy, if exist */
if (buddy) {
struct mlme_priv *b_pmlmepriv = &buddy->mlmepriv;
struct wifidirect_info *b_pwdinfo = &buddy->wdinfo;
if (check_fwstate(b_pmlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR)
|| check_fwstate(b_pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS)
|| check_fwstate(b_pmlmepriv, WIFI_AP_STATE)
|| check_fwstate(b_pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE)
|| !rtw_p2p_chk_state(b_pwdinfo, P2P_STATE_NONE)
) {
goto exit;
}
}
if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF ||
pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) {
DBG_8723A_LEVEL(_drv_always_, "There are some pkts to transmit\n");
DBG_8723A_LEVEL(_drv_info_, "free_xmitbuf_cnt: %d, free_xmit_extbuf_cnt: %d\n",
pxmit_priv->free_xmitbuf_cnt, pxmit_priv->free_xmit_extbuf_cnt);
goto exit;
}
ret = true;
exit:
return ret;
}
void rtw_ps_processor23a(struct rtw_adapter*padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
enum rt_rf_power_state rfpwrstate;
pwrpriv->ps_processing = true;
if (pwrpriv->bips_processing == true)
goto exit;
if (padapter->pwrctrlpriv.bHWPwrPindetect) {
rfpwrstate = RfOnOffDetect23a(padapter);
DBG_8723A("@@@@- #2 %s ==> rfstate:%s\n", __func__, (rfpwrstate == rf_on)?"rf_on":"rf_off");
if (rfpwrstate!= pwrpriv->rf_pwrstate) {
if (rfpwrstate == rf_off) {
pwrpriv->change_rfpwrstate = rf_off;
pwrpriv->brfoffbyhw = true;
padapter->bCardDisableWOHSM = true;
rtw_hw_suspend23a(padapter);
} else {
pwrpriv->change_rfpwrstate = rf_on;
rtw_hw_resume23a(padapter);
}
DBG_8723A("current rf_pwrstate(%s)\n", (pwrpriv->rf_pwrstate == rf_off)?"rf_off":"rf_on");
}
pwrpriv->pwr_state_check_cnts ++;
}
if (pwrpriv->ips_mode_req == IPS_NONE)
goto exit;
if (rtw_pwr_unassociated_idle(padapter) == false)
goto exit;
if ((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts%4) == 0))
{
DBG_8723A("==>%s .fw_state(%x)\n", __func__, get_fwstate(pmlmepriv));
pwrpriv->change_rfpwrstate = rf_off;
ips_enter23a(padapter);
}
exit:
rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv);
pwrpriv->ps_processing = false;
return;
}
static void pwr_state_check_handler(unsigned long data)
{
struct rtw_adapter *padapter = (struct rtw_adapter *)data;
rtw_ps_cmd23a(padapter);
}
/*
*
* Parameters
* padapter
* pslv power state level, only could be PS_STATE_S0 ~ PS_STATE_S4
*
*/
void rtw_set_rpwm23a(struct rtw_adapter *padapter, u8 pslv)
{
u8 rpwm;
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
pslv = PS_STATE(pslv);
if (true == pwrpriv->btcoex_rfon)
{
if (pslv < PS_STATE_S4)
pslv = PS_STATE_S3;
}
if (pwrpriv->rpwm == pslv) {
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
("%s: Already set rpwm[0x%02X], new = 0x%02X!\n", __func__, pwrpriv->rpwm, pslv));
return;
}
if ((padapter->bSurpriseRemoved == true) ||
(padapter->hw_init_completed == false)) {
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
("%s: SurpriseRemoved(%d) hw_init_completed(%d)\n",
__func__, padapter->bSurpriseRemoved, padapter->hw_init_completed));
pwrpriv->cpwm = PS_STATE_S4;
return;
}
if (padapter->bDriverStopped == true) {
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
("%s: change power state(0x%02X) when DriverStopped\n", __func__, pslv));
if (pslv < PS_STATE_S2) {
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
("%s: Reject to enter PS_STATE(0x%02X) lower than S2 when DriverStopped!!\n", __func__, pslv));
return;
}
}
rpwm = pslv | pwrpriv->tog;
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
("rtw_set_rpwm23a: rpwm = 0x%02x cpwm = 0x%02x\n", rpwm, pwrpriv->cpwm));
pwrpriv->rpwm = pslv;
rtw_hal_set_hwreg23a(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
pwrpriv->tog += 0x80;
pwrpriv->cpwm = pslv;
}
u8 PS_RDY_CHECK(struct rtw_adapter * padapter)
{
unsigned long delta_time;
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
delta_time = jiffies - pwrpriv->DelayLPSLastTimeStamp;
if (delta_time < LPS_DELAY_TIME)
{
return false;
}
if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) ||
(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true) ||
(check_fwstate(pmlmepriv, WIFI_AP_STATE) == true) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == true))
return false;
if (true == pwrpriv->bInSuspend)
return false;
if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == false))
{
DBG_8723A("Group handshake still in progress !!!\n");
return false;
}
if (!rtw_cfg80211_pwr_mgmt(padapter))
return false;
return true;
}
void rtw_set_ps_mode23a(struct rtw_adapter *padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
#ifdef CONFIG_8723AU_P2P
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
#endif /* CONFIG_8723AU_P2P */
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
("%s: PowerMode =%d Smart_PS =%d\n",
__func__, ps_mode, smart_ps));
if (ps_mode > PM_Card_Disable) {
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, ("ps_mode:%d error\n", ps_mode));
return;
}
if (pwrpriv->pwr_mode == ps_mode)
{
if (PS_MODE_ACTIVE == ps_mode) return;
if ((pwrpriv->smart_ps == smart_ps) &&
(pwrpriv->bcn_ant_mode == bcn_ant_mode))
{
return;
}
}
if (ps_mode == PS_MODE_ACTIVE) {
#ifdef CONFIG_8723AU_P2P
if (pwdinfo->opp_ps == 0)
#endif /* CONFIG_8723AU_P2P */
{
DBG_8723A("rtw_set_ps_mode23a: Leave 802.11 power save\n");
pwrpriv->pwr_mode = ps_mode;
rtw_set_rpwm23a(padapter, PS_STATE_S4);
rtw_hal_set_hwreg23a(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
pwrpriv->bFwCurrentInPSMode = false;
}
}
else
{
if (PS_RDY_CHECK(padapter)
#ifdef CONFIG_8723AU_BT_COEXIST
|| (BT_1Ant(padapter) == true)
#endif
)
{
DBG_8723A("%s: Enter 802.11 power save\n", __func__);
pwrpriv->bFwCurrentInPSMode = true;
pwrpriv->pwr_mode = ps_mode;
pwrpriv->smart_ps = smart_ps;
pwrpriv->bcn_ant_mode = bcn_ant_mode;
rtw_hal_set_hwreg23a(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
#ifdef CONFIG_8723AU_P2P
/* Set CTWindow after LPS */
if (pwdinfo->opp_ps == 1)
p2p_ps_wk_cmd23a(padapter, P2P_PS_ENABLE, 0);
#endif /* CONFIG_8723AU_P2P */
rtw_set_rpwm23a(padapter, PS_STATE_S2);
}
}
}
/*
* Return:
* 0: Leave OK
* -1: Timeout
* -2: Other error
*/
s32 LPS_RF_ON_check23a(struct rtw_adapter *padapter, u32 delay_ms)
{
unsigned long start_time, end_time;
u8 bAwake = false;
s32 err = 0;
start_time = jiffies;
end_time = start_time + msecs_to_jiffies(delay_ms);
while (1)
{
rtw23a_hal_get_hwreg(padapter, HW_VAR_FWLPS_RF_ON, &bAwake);
if (true == bAwake)
break;
if (true == padapter->bSurpriseRemoved)
{
err = -2;
DBG_8723A("%s: device surprise removed!!\n", __func__);
break;
}
if (time_after(jiffies, end_time)) {
err = -1;
DBG_8723A("%s: Wait for FW LPS leave more than %u ms!!!\n", __func__, delay_ms);
break;
}
udelay(100);
}
return err;
}
/* Description: */
/* Enter the leisure power save mode. */
void LPS_Enter23a(struct rtw_adapter *padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
if (!PS_RDY_CHECK(padapter))
return;
if (pwrpriv->bLeisurePs) {
/* Idle for a while if we connect to AP a while ago. */
if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */
if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {
pwrpriv->bpower_saving = true;
DBG_8723A("%s smart_ps:%d\n", __func__, pwrpriv->smart_ps);
/* For Tenda W311R IOT issue */
rtw_set_ps_mode23a(padapter, pwrpriv->power_mgnt, pwrpriv->smart_ps, 0);
}
} else {
pwrpriv->LpsIdleCount++;
}
}
}
/* Description: */
/* Leave the leisure power save mode. */
void LPS_Leave23a(struct rtw_adapter *padapter)
{
#define LPS_LEAVE_TIMEOUT_MS 100
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
if (pwrpriv->bLeisurePs) {
if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
rtw_set_ps_mode23a(padapter, PS_MODE_ACTIVE, 0, 0);
if (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
LPS_RF_ON_check23a(padapter, LPS_LEAVE_TIMEOUT_MS);
}
}
pwrpriv->bpower_saving = false;
}
/* Description: Leave all power save mode: LPS, FwLPS, IPS if needed. */
/* Move code to function by tynli. 2010.03.26. */
void LeaveAllPowerSaveMode23a(struct rtw_adapter *Adapter)
{
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
u8 enqueue = 0;
/* DBG_8723A("%s.....\n", __func__); */
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
{ /* connect */
#ifdef CONFIG_8723AU_P2P
p2p_ps_wk_cmd23a(Adapter, P2P_PS_DISABLE, enqueue);
#endif /* CONFIG_8723AU_P2P */
rtw_lps_ctrl_wk_cmd23a(Adapter, LPS_CTRL_LEAVE, enqueue);
}
}
void rtw_init_pwrctrl_priv23a(struct rtw_adapter *padapter)
{
struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
sema_init(&pwrctrlpriv->lock, 1);
pwrctrlpriv->rf_pwrstate = rf_on;
pwrctrlpriv->ips_enter23a_cnts = 0;
pwrctrlpriv->ips_leave23a_cnts = 0;
pwrctrlpriv->bips_processing = false;
pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode;
pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode;
pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL;
pwrctrlpriv->pwr_state_check_cnts = 0;
pwrctrlpriv->bInternalAutoSuspend = false;
pwrctrlpriv->bInSuspend = false;
pwrctrlpriv->bkeepfwalive = false;
pwrctrlpriv->LpsIdleCount = 0;
pwrctrlpriv->power_mgnt = padapter->registrypriv.power_mgnt;/* PS_MODE_MIN; */
pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt)?true:false;
pwrctrlpriv->bFwCurrentInPSMode = false;
pwrctrlpriv->rpwm = 0;
pwrctrlpriv->cpwm = PS_STATE_S4;
pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE;
pwrctrlpriv->smart_ps = padapter->registrypriv.smart_ps;
pwrctrlpriv->bcn_ant_mode = 0;
pwrctrlpriv->tog = 0x80;
pwrctrlpriv->btcoex_rfon = false;
setup_timer(&pwrctrlpriv->pwr_state_check_timer,
pwr_state_check_handler, (unsigned long)padapter);
}
void rtw_free_pwrctrl_priv(struct rtw_adapter *adapter)
{
}
u8 rtw_interface_ps_func23a(struct rtw_adapter *padapter, enum hal_intf_ps_func efunc_id, u8* val)
{
u8 bResult = true;
rtw_hal_intf_ps_func23a(padapter, efunc_id, val);
return bResult;
}
inline void rtw_set_ips_deny23a(struct rtw_adapter *padapter, u32 ms)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
pwrpriv->ips_deny_time = jiffies + msecs_to_jiffies(ms);
}
/*
* rtw_pwr_wakeup - Wake the NIC up from: 1)IPS. 2)USB autosuspend
* @adapter: pointer to _adapter structure
* @ips_deffer_ms: the ms wiil prevent from falling into IPS after wakeup
* Return _SUCCESS or _FAIL
*/
int _rtw_pwr_wakeup23a(struct rtw_adapter *padapter, u32 ips_deffer_ms, const char *caller)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
int ret = _SUCCESS;
unsigned long start = jiffies;
unsigned long new_deny_time;
new_deny_time = jiffies + msecs_to_jiffies(ips_deffer_ms);
if (time_before(pwrpriv->ips_deny_time, new_deny_time))
pwrpriv->ips_deny_time = new_deny_time;
if (pwrpriv->ps_processing) {
DBG_8723A("%s wait ps_processing...\n", __func__);
while (pwrpriv->ps_processing &&
jiffies_to_msecs(jiffies - start) <= 3000)
msleep(10);
if (pwrpriv->ps_processing)
DBG_8723A("%s wait ps_processing timeout\n", __func__);
else
DBG_8723A("%s wait ps_processing done\n", __func__);
}
if (rtw_hal_sreset_inprogress(padapter)) {
DBG_8723A("%s wait sreset_inprogress...\n", __func__);
while (rtw_hal_sreset_inprogress(padapter) &&
jiffies_to_msecs(jiffies - start) <= 4000)
msleep(10);
if (rtw_hal_sreset_inprogress(padapter))
DBG_8723A("%s wait sreset_inprogress timeout\n", __func__);
else
DBG_8723A("%s wait sreset_inprogress done\n", __func__);
}
if (pwrpriv->bInternalAutoSuspend == false && pwrpriv->bInSuspend) {
DBG_8723A("%s wait bInSuspend...\n", __func__);
while (pwrpriv->bInSuspend &&
(jiffies_to_msecs(jiffies - start) <= 3000)) {
msleep(10);
}
if (pwrpriv->bInSuspend)
DBG_8723A("%s wait bInSuspend timeout\n", __func__);
else
DBG_8723A("%s wait bInSuspend done\n", __func__);
}
/* System suspend is not allowed to wakeup */
if ((pwrpriv->bInternalAutoSuspend == false) && (true == pwrpriv->bInSuspend)) {
ret = _FAIL;
goto exit;
}
/* block??? */
if ((pwrpriv->bInternalAutoSuspend == true) && (padapter->net_closed == true)) {
ret = _FAIL;
goto exit;
}
/* I think this should be check in IPS, LPS, autosuspend functions... */
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
{
ret = _SUCCESS;
goto exit;
}
if (rf_off == pwrpriv->rf_pwrstate) {
DBG_8723A("%s call ips_leave23a....\n", __func__);
if (_FAIL == ips_leave23a(padapter)) {
DBG_8723A("======> ips_leave23a fail.............\n");
ret = _FAIL;
goto exit;
}
}
/* TODO: the following checking need to be merged... */
if (padapter->bDriverStopped || !padapter->bup ||
!padapter->hw_init_completed) {
DBG_8723A("%s: bDriverStopped =%d, bup =%d, hw_init_completed "
"=%u\n", caller, padapter->bDriverStopped,
padapter->bup, padapter->hw_init_completed);
ret = false;
goto exit;
}
exit:
new_deny_time = jiffies + msecs_to_jiffies(ips_deffer_ms);
if (time_before(pwrpriv->ips_deny_time, new_deny_time))
pwrpriv->ips_deny_time = new_deny_time;
return ret;
}
int rtw_pm_set_lps23a(struct rtw_adapter *padapter, u8 mode)
{
int ret = 0;
struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
if (mode < PS_MODE_NUM)
{
if (pwrctrlpriv->power_mgnt != mode)
{
if (PS_MODE_ACTIVE == mode)
{
LeaveAllPowerSaveMode23a(padapter);
}
else
{
pwrctrlpriv->LpsIdleCount = 2;
}
pwrctrlpriv->power_mgnt = mode;
pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt)?true:false;
}
}
else
{
ret = -EINVAL;
}
return ret;
}
int rtw_pm_set_ips23a(struct rtw_adapter *padapter, u8 mode)
{
struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
if (mode == IPS_NORMAL || mode == IPS_LEVEL_2) {
rtw_ips_mode_req(pwrctrlpriv, mode);
DBG_8723A("%s %s\n", __func__, mode == IPS_NORMAL?"IPS_NORMAL":"IPS_LEVEL_2");
return 0;
}
else if (mode == IPS_NONE) {
rtw_ips_mode_req(pwrctrlpriv, mode);
DBG_8723A("%s %s\n", __func__, "IPS_NONE");
if ((padapter->bSurpriseRemoved == 0)&&_FAIL == rtw_pwr_wakeup(padapter))
return -EFAULT;
}
else {
return -EINVAL;
}
return 0;
}

2471
drivers/staging/rtl8723au/core/rtw_recv.c Normal file
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File diff suppressed because it is too large Load Diff

1652
drivers/staging/rtl8723au/core/rtw_security.c Normal file
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File diff suppressed because it is too large Load Diff

255
drivers/staging/rtl8723au/core/rtw_sreset.c Normal file
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@ -0,0 +1,255 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include<rtw_sreset.h>
void sreset_init_value23a(struct rtw_adapter *padapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
mutex_init(&psrtpriv->silentreset_mutex);
psrtpriv->silent_reset_inprogress = false;
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
psrtpriv->last_tx_time = 0;
psrtpriv->last_tx_complete_time = 0;
}
void sreset_reset_value23a(struct rtw_adapter *padapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
psrtpriv->silent_reset_inprogress = false;
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
psrtpriv->last_tx_time = 0;
psrtpriv->last_tx_complete_time = 0;
}
u8 sreset_get_wifi_status23a(struct rtw_adapter *padapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u8 status = WIFI_STATUS_SUCCESS;
u32 val32 = 0;
if (psrtpriv->silent_reset_inprogress)
return status;
val32 = rtw_read32(padapter, REG_TXDMA_STATUS);
if (val32 == 0xeaeaeaea) {
psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
} else if (val32 != 0) {
DBG_8723A("txdmastatu(%x)\n", val32);
psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
}
if (WIFI_STATUS_SUCCESS != psrtpriv->Wifi_Error_Status) {
DBG_8723A("==>%s error_status(0x%x)\n", __func__, psrtpriv->Wifi_Error_Status);
status = (psrtpriv->Wifi_Error_Status &~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL));
}
DBG_8723A("==> %s wifi_status(0x%x)\n", __func__, status);
/* status restore */
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
return status;
}
void sreset_set_wifi_error_status23a(struct rtw_adapter *padapter, u32 status)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.Wifi_Error_Status = status;
}
void sreset_set_trigger_point(struct rtw_adapter *padapter, s32 tgp)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.dbg_trigger_point = tgp;
}
bool sreset_inprogress(struct rtw_adapter *padapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
return pHalData->srestpriv.silent_reset_inprogress;
}
static void sreset_restore_security_station(struct rtw_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *psta;
struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
u8 val8;
if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X)
val8 = 0xcc;
else
val8 = 0xcf;
rtw_hal_set_hwreg23a(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
psta = rtw_get_stainfo23a(pstapriv, get_bssid(mlmepriv));
if (psta == NULL) {
/* DEBUG_ERR(("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
} else {
/* pairwise key */
rtw_setstakey_cmd23a(padapter, (unsigned char *)psta, true);
/* group key */
rtw_set_key23a(padapter,&padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0);
}
}
}
static void sreset_restore_network_station(struct rtw_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
u8 threshold;
rtw_setopmode_cmd23a(padapter, Ndis802_11Infrastructure);
/* TH = 1 => means that invalidate usb rx aggregation */
/* TH = 0 => means that validate usb rx aggregation, use init value. */
if (mlmepriv->htpriv.ht_option) {
if (padapter->registrypriv.wifi_spec == 1)
threshold = 1;
else
threshold = 0;
rtw_hal_set_hwreg23a(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
} else {
threshold = 1;
rtw_hal_set_hwreg23a(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
}
set_channel_bwmode23a(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
/* disable dynamic functions, such as high power, DIG */
/* Switch_DM_Func23a(padapter, DYNAMIC_FUNC_DISABLE, false); */
rtw_hal_set_hwreg23a(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
{
u8 join_type = 0;
rtw_hal_set_hwreg23a(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
}
Set_MSR23a(padapter, (pmlmeinfo->state & 0x3));
mlmeext_joinbss_event_callback23a(padapter, 1);
/* restore Sequence No. */
rtw_write8(padapter, 0x4dc, padapter->xmitpriv.nqos_ssn);
sreset_restore_security_station(padapter);
}
static void sreset_restore_network_status(struct rtw_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
DBG_8723A(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
sreset_restore_network_station(padapter);
#ifdef CONFIG_8723AU_AP_MODE
} else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) {
DBG_8723A(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
rtw_ap_restore_network(padapter);
#endif
} else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) {
DBG_8723A(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
} else {
DBG_8723A(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
}
}
static void sreset_stop_adapter(struct rtw_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter == NULL)
return;
DBG_8723A(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
if (!rtw_netif_queue_stopped(padapter->pnetdev))
netif_tx_stop_all_queues(padapter->pnetdev);
rtw_cancel_all_timer23a(padapter);
/* TODO: OS and HCI independent */
tasklet_kill(&pxmitpriv->xmit_tasklet);
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
rtw_scan_abort23a(padapter);
if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING))
rtw23a_join_to_handler((unsigned long)padapter);
}
static void sreset_start_adapter(struct rtw_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter == NULL)
return;
DBG_8723A(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
if (check_fwstate(pmlmepriv, _FW_LINKED)) {
sreset_restore_network_status(padapter);
}
/* TODO: OS and HCI independent */
tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
mod_timer(&padapter->mlmepriv.dynamic_chk_timer,
jiffies + msecs_to_jiffies(2000));
if (rtw_netif_queue_stopped(padapter->pnetdev))
netif_tx_wake_all_queues(padapter->pnetdev);
}
void sreset_reset(struct rtw_adapter *padapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
unsigned long start = jiffies;
DBG_8723A("%s\n", __func__);
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
mutex_lock(&psrtpriv->silentreset_mutex);
psrtpriv->silent_reset_inprogress = true;
pwrpriv->change_rfpwrstate = rf_off;
sreset_stop_adapter(padapter);
ips_enter23a(padapter);
ips_leave23a(padapter);
sreset_start_adapter(padapter);
psrtpriv->silent_reset_inprogress = false;
mutex_unlock(&psrtpriv->silentreset_mutex);
DBG_8723A("%s done in %d ms\n", __func__,
jiffies_to_msecs(jiffies - start));
}

509
drivers/staging/rtl8723au/core/rtw_sta_mgt.c Normal file
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@ -0,0 +1,509 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _RTW_STA_MGT_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <recv_osdep.h>
#include <xmit_osdep.h>
#include <mlme_osdep.h>
#include <sta_info.h>
void _rtw_init_stainfo(struct sta_info *psta)
{
memset((u8 *)psta, 0, sizeof (struct sta_info));
spin_lock_init(&psta->lock);
INIT_LIST_HEAD(&psta->list);
INIT_LIST_HEAD(&psta->hash_list);
_rtw_init_queue23a(&psta->sleep_q);
psta->sleepq_len = 0;
_rtw_init_sta_xmit_priv23a(&psta->sta_xmitpriv);
_rtw_init_sta_recv_priv23a(&psta->sta_recvpriv);
#ifdef CONFIG_8723AU_AP_MODE
INIT_LIST_HEAD(&psta->asoc_list);
INIT_LIST_HEAD(&psta->auth_list);
psta->expire_to = 0;
psta->flags = 0;
psta->capability = 0;
psta->bpairwise_key_installed = false;
psta->nonerp_set = 0;
psta->no_short_slot_time_set = 0;
psta->no_short_preamble_set = 0;
psta->no_ht_gf_set = 0;
psta->no_ht_set = 0;
psta->ht_20mhz_set = 0;
psta->keep_alive_trycnt = 0;
#endif /* CONFIG_8723AU_AP_MODE */
}
u32 _rtw_init_sta_priv23a(struct sta_priv *pstapriv)
{
struct sta_info *psta;
s32 i;
pstapriv->pallocated_stainfo_buf = rtw_zvmalloc(sizeof(struct sta_info) * NUM_STA+ 4);
if (!pstapriv->pallocated_stainfo_buf)
return _FAIL;
pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 -
((unsigned long)(pstapriv->pallocated_stainfo_buf) & 3);
_rtw_init_queue23a(&pstapriv->free_sta_queue);
spin_lock_init(&pstapriv->sta_hash_lock);
pstapriv->asoc_sta_count = 0;
_rtw_init_queue23a(&pstapriv->sleep_q);
_rtw_init_queue23a(&pstapriv->wakeup_q);
psta = (struct sta_info *)(pstapriv->pstainfo_buf);
for (i = 0; i < NUM_STA; i++) {
_rtw_init_stainfo(psta);
INIT_LIST_HEAD(&pstapriv->sta_hash[i]);
list_add_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue));
psta++;
}
#ifdef CONFIG_8723AU_AP_MODE
pstapriv->sta_dz_bitmap = 0;
pstapriv->tim_bitmap = 0;
INIT_LIST_HEAD(&pstapriv->asoc_list);
INIT_LIST_HEAD(&pstapriv->auth_list);
spin_lock_init(&pstapriv->asoc_list_lock);
spin_lock_init(&pstapriv->auth_list_lock);
pstapriv->asoc_list_cnt = 0;
pstapriv->auth_list_cnt = 0;
pstapriv->auth_to = 3; /* 3*2 = 6 sec */
pstapriv->assoc_to = 3;
/* pstapriv->expire_to = 900; 900*2 = 1800 sec = 30 min, expire after no any traffic. */
/* pstapriv->expire_to = 30; 30*2 = 60 sec = 1 min, expire after no any traffic. */
pstapriv->expire_to = 3; /* 3*2 = 6 sec */
pstapriv->max_num_sta = NUM_STA;
#endif
return _SUCCESS;
}
inline int rtw_stainfo_offset23a(struct sta_priv *stapriv, struct sta_info *sta)
{
int offset = (((u8 *)sta) - stapriv->pstainfo_buf)/sizeof(struct sta_info);
if (!stainfo_offset_valid(offset))
DBG_8723A("%s invalid offset(%d), out of range!!!", __func__, offset);
return offset;
}
inline struct sta_info *rtw_get_stainfo23a_by_offset23a(struct sta_priv *stapriv, int offset)
{
if (!stainfo_offset_valid(offset))
DBG_8723A("%s invalid offset(%d), out of range!!!", __func__, offset);
return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info));
}
/* this function is used to free the memory of lock || sema for all stainfos */
void rtw_mfree_all_stainfo(struct sta_priv *pstapriv)
{
struct list_head *plist, *phead;
struct sta_info *psta;
spin_lock_bh(&pstapriv->sta_hash_lock);
phead = get_list_head(&pstapriv->free_sta_queue);
/* we really achieve a lot in this loop .... */
list_for_each(plist, phead)
psta = container_of(plist, struct sta_info, list);
spin_unlock_bh(&pstapriv->sta_hash_lock);
}
void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv)
{
rtw_mfree_all_stainfo(pstapriv); /* be done before free sta_hash_lock */
}
u32 _rtw_free_sta_priv23a(struct sta_priv *pstapriv)
{
struct list_head *phead, *plist, *ptmp;
struct sta_info *psta;
struct recv_reorder_ctrl *preorder_ctrl;
int index;
if (pstapriv) {
/* delete all reordering_ctrl_timer */
spin_lock_bh(&pstapriv->sta_hash_lock);
for (index = 0; index < NUM_STA; index++) {
phead = &pstapriv->sta_hash[index];
list_for_each_safe(plist, ptmp, phead) {
int i;
psta = container_of(plist, struct sta_info,
hash_list);
for (i = 0; i < 16 ; i++) {
preorder_ctrl = &psta->recvreorder_ctrl[i];
del_timer_sync(&preorder_ctrl->reordering_ctrl_timer);
}
}
}
spin_unlock_bh(&pstapriv->sta_hash_lock);
/*===============================*/
rtw_mfree_sta_priv_lock(pstapriv);
if (pstapriv->pallocated_stainfo_buf)
rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info)*NUM_STA+4);
}
return _SUCCESS;
}
struct sta_info *rtw_alloc_stainfo23a(struct sta_priv *pstapriv, u8 *hwaddr)
{
struct list_head *phash_list;
struct sta_info *psta;
struct rtw_queue *pfree_sta_queue;
struct recv_reorder_ctrl *preorder_ctrl;
uint tmp_aid;
s32 index;
int i = 0;
u16 wRxSeqInitialValue = 0xffff;
pfree_sta_queue = &pstapriv->free_sta_queue;
spin_lock_bh(&pstapriv->sta_hash_lock);
if (_rtw_queue_empty23a(pfree_sta_queue)) {
spin_unlock_bh(&pstapriv->sta_hash_lock);
return NULL;
}
psta = container_of((&pfree_sta_queue->queue)->next, struct sta_info, list);
list_del_init(&psta->list);
tmp_aid = psta->aid;
_rtw_init_stainfo(psta);
psta->padapter = pstapriv->padapter;
memcpy(psta->hwaddr, hwaddr, ETH_ALEN);
index = wifi_mac_hash(hwaddr);
RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_info_,
("rtw_alloc_stainfo23a: index = %x", index));
if (index >= NUM_STA) {
RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_,
("ERROR => rtw_alloc_stainfo23a: index >= NUM_STA"));
psta = NULL;
goto exit;
}
phash_list = &pstapriv->sta_hash[index];
list_add_tail(&psta->hash_list, phash_list);
pstapriv->asoc_sta_count ++ ;
/* For the SMC router, the sequence number of first packet of WPS handshake will be 0. */
/* In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable. */
/* So, we initialize the tid_rxseq variable as the 0xffff. */
for (i = 0; i < 16; i++)
memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2);
RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_info_,
("alloc number_%d stainfo with hwaddr = %pM\n",
pstapriv->asoc_sta_count, hwaddr));
init_addba_retry_timer23a(psta);
/* for A-MPDU Rx reordering buffer control */
for (i = 0; i < 16; i++) {
preorder_ctrl = &psta->recvreorder_ctrl[i];
preorder_ctrl->padapter = pstapriv->padapter;
preorder_ctrl->enable = false;
preorder_ctrl->indicate_seq = 0xffff;
preorder_ctrl->wend_b = 0xffff;
/* preorder_ctrl->wsize_b = (NR_RECVBUFF-2); */
preorder_ctrl->wsize_b = 64;/* 64; */
_rtw_init_queue23a(&preorder_ctrl->pending_recvframe_queue);
rtw_init_recv_timer23a(preorder_ctrl);
}
/* init for DM */
psta->rssi_stat.UndecoratedSmoothedPWDB = (-1);
psta->rssi_stat.UndecoratedSmoothedCCK = (-1);
/* init for the sequence number of received management frame */
psta->RxMgmtFrameSeqNum = 0xffff;
exit:
spin_unlock_bh(&pstapriv->sta_hash_lock);
return psta;
}
/* using pstapriv->sta_hash_lock to protect */
u32 rtw_free_stainfo23a(struct rtw_adapter *padapter, struct sta_info *psta)
{
struct rtw_queue *pfree_sta_queue;
struct recv_reorder_ctrl *preorder_ctrl;
struct sta_xmit_priv *pstaxmitpriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct hw_xmit *phwxmit;
int i;
if (psta == NULL)
goto exit;
spin_lock_bh(&psta->lock);
psta->state &= ~_FW_LINKED;
spin_unlock_bh(&psta->lock);
pfree_sta_queue = &pstapriv->free_sta_queue;
pstaxmitpriv = &psta->sta_xmitpriv;
spin_lock_bh(&pxmitpriv->lock);
rtw_free_xmitframe_queue23a(pxmitpriv, &psta->sleep_q);
psta->sleepq_len = 0;
/* vo */
rtw_free_xmitframe_queue23a(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);
list_del_init(&pstaxmitpriv->vo_q.tx_pending);
phwxmit = pxmitpriv->hwxmits;
phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt;
pstaxmitpriv->vo_q.qcnt = 0;
/* vi */
rtw_free_xmitframe_queue23a(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending);
list_del_init(&pstaxmitpriv->vi_q.tx_pending);
phwxmit = pxmitpriv->hwxmits+1;
phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt;
pstaxmitpriv->vi_q.qcnt = 0;
/* be */
rtw_free_xmitframe_queue23a(pxmitpriv, &pstaxmitpriv->be_q.sta_pending);
list_del_init(&pstaxmitpriv->be_q.tx_pending);
phwxmit = pxmitpriv->hwxmits+2;
phwxmit->accnt -= pstaxmitpriv->be_q.qcnt;
pstaxmitpriv->be_q.qcnt = 0;
/* bk */
rtw_free_xmitframe_queue23a(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);
list_del_init(&pstaxmitpriv->bk_q.tx_pending);
phwxmit = pxmitpriv->hwxmits+3;
phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt;
pstaxmitpriv->bk_q.qcnt = 0;
spin_unlock_bh(&pxmitpriv->lock);
list_del_init(&psta->hash_list);
RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_, ("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n", pstapriv->asoc_sta_count, psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2], psta->hwaddr[3], psta->hwaddr[4], psta->hwaddr[5]));
pstapriv->asoc_sta_count --;
/* re-init sta_info; 20061114 will be init in alloc_stainfo */
/* _rtw_init_sta_xmit_priv23a(&psta->sta_xmitpriv); */
/* _rtw_init_sta_recv_priv23a(&psta->sta_recvpriv); */
del_timer_sync(&psta->addba_retry_timer);
/* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */
for (i = 0; i < 16; i++) {
struct list_head *phead, *plist;
struct recv_frame *prframe;
struct rtw_queue *ppending_recvframe_queue;
struct rtw_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
preorder_ctrl = &psta->recvreorder_ctrl[i];
del_timer_sync(&preorder_ctrl->reordering_ctrl_timer);
ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
spin_lock_bh(&ppending_recvframe_queue->lock);
phead = get_list_head(ppending_recvframe_queue);
plist = phead->next;
while (!list_empty(phead)) {
prframe = container_of(plist, struct recv_frame, list);
plist = plist->next;
list_del_init(&prframe->list);
rtw_free_recvframe23a(prframe, pfree_recv_queue);
}
spin_unlock_bh(&ppending_recvframe_queue->lock);
}
if (!(psta->state & WIFI_AP_STATE))
rtw_hal_set_odm_var23a(padapter, HAL_ODM_STA_INFO, psta, false);
#ifdef CONFIG_8723AU_AP_MODE
spin_lock_bh(&pstapriv->auth_list_lock);
if (!list_empty(&psta->auth_list)) {
list_del_init(&psta->auth_list);
pstapriv->auth_list_cnt--;
}
spin_unlock_bh(&pstapriv->auth_list_lock);
psta->expire_to = 0;
psta->sleepq_ac_len = 0;
psta->qos_info = 0;
psta->max_sp_len = 0;
psta->uapsd_bk = 0;
psta->uapsd_be = 0;
psta->uapsd_vi = 0;
psta->uapsd_vo = 0;
psta->has_legacy_ac = 0;
pstapriv->sta_dz_bitmap &= ~CHKBIT(psta->aid);
pstapriv->tim_bitmap &= ~CHKBIT(psta->aid);
if ((psta->aid >0) && (pstapriv->sta_aid[psta->aid - 1] == psta)) {
pstapriv->sta_aid[psta->aid - 1] = NULL;
psta->aid = 0;
}
#endif /* CONFIG_8723AU_AP_MODE */
list_add_tail(&psta->list, get_list_head(pfree_sta_queue));
exit:
return _SUCCESS;
}
/* free all stainfo which in sta_hash[all] */
void rtw_free_all_stainfo23a(struct rtw_adapter *padapter)
{
struct list_head *plist, *phead, *ptmp;
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info* pbcmc_stainfo = rtw_get_bcmc_stainfo23a(padapter);
s32 index; if (pstapriv->asoc_sta_count == 1)
return;
spin_lock_bh(&pstapriv->sta_hash_lock);
for (index = 0; index < NUM_STA; index++) {
phead = &pstapriv->sta_hash[index];
list_for_each_safe(plist, ptmp, phead) {
psta = container_of(plist, struct sta_info, hash_list);
if (pbcmc_stainfo!= psta)
rtw_free_stainfo23a(padapter, psta);
}
}
spin_unlock_bh(&pstapriv->sta_hash_lock);
}
/* any station allocated can be searched by hash list */
struct sta_info *rtw_get_stainfo23a(struct sta_priv *pstapriv, u8 *hwaddr)
{
struct list_head *plist, *phead;
struct sta_info *psta = NULL;
u32 index;
u8 *addr;
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
if (hwaddr == NULL)
return NULL;
if (is_multicast_ether_addr(hwaddr))
addr = bc_addr;
else
addr = hwaddr;
index = wifi_mac_hash(addr);
spin_lock_bh(&pstapriv->sta_hash_lock);
phead = &pstapriv->sta_hash[index];
list_for_each(plist, phead) {
psta = container_of(plist, struct sta_info, hash_list);
if (!memcmp(psta->hwaddr, addr, ETH_ALEN)) {
/* if found the matched address */
break;
}
psta = NULL;
}
spin_unlock_bh(&pstapriv->sta_hash_lock);
return psta;
}
u32 rtw_init_bcmc_stainfo23a(struct rtw_adapter* padapter)
{
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *psta;
struct tx_servq *ptxservq;
u32 res = _SUCCESS;
unsigned char bcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
psta = rtw_alloc_stainfo23a(pstapriv, bcast_addr);
if (psta == NULL) {
res = _FAIL;
RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_,
("rtw_alloc_stainfo23a fail"));
return res;
}
/* default broadcast & multicast use macid 1 */
psta->mac_id = 1;
ptxservq = &psta->sta_xmitpriv.be_q;
return _SUCCESS;
}
struct sta_info *rtw_get_bcmc_stainfo23a(struct rtw_adapter *padapter)
{
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
psta = rtw_get_stainfo23a(pstapriv, bc_addr);
return psta;
}
u8 rtw_access_ctrl23a(struct rtw_adapter *padapter, u8 *mac_addr)
{
u8 res = true;
#ifdef CONFIG_8723AU_AP_MODE
struct list_head *plist, *phead;
struct rtw_wlan_acl_node *paclnode;
u8 match = false;
struct sta_priv *pstapriv = &padapter->stapriv;
struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
struct rtw_queue *pacl_node_q = &pacl_list->acl_node_q;
spin_lock_bh(&pacl_node_q->lock);
phead = get_list_head(pacl_node_q);
list_for_each(plist, phead) {
paclnode = container_of(plist, struct rtw_wlan_acl_node, list);
if (!memcmp(paclnode->addr, mac_addr, ETH_ALEN)) {
if (paclnode->valid) {
match = true;
break;
}
}
}
spin_unlock_bh(&pacl_node_q->lock);
if (pacl_list->mode == 1)/* accept unless in deny list */
res = (match) ? false : true;
else if (pacl_list->mode == 2)/* deny unless in accept list */
res = (match) ? true : false;
else
res = true;
#endif
return res;
}

1760
drivers/staging/rtl8723au/core/rtw_wlan_util.c Normal file
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File diff suppressed because it is too large Load Diff

2460
drivers/staging/rtl8723au/core/rtw_xmit.c Normal file
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File diff suppressed because it is too large Load Diff

80
drivers/staging/rtl8723au/hal/Hal8723PwrSeq.c Normal file
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@ -0,0 +1,80 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "Hal8723PwrSeq.h"
/*
drivers should parse below arrays and do the corresponding actions
*/
/* 3 Power on Array */
struct wlan_pwr_cfg rtl8723AU_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_CARDEMU_TO_ACT
RTL8723A_TRANS_END
};
/* 3 Radio off GPIO Array */
struct wlan_pwr_cfg rtl8723AU_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU
RTL8723A_TRANS_END
};
/* 3 Card Disable Array */
struct wlan_pwr_cfg rtl8723AU_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU
RTL8723A_TRANS_CARDEMU_TO_CARDDIS
RTL8723A_TRANS_END
};
/* 3 Card Enable Array */
struct wlan_pwr_cfg rtl8723AU_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_CARDDIS_TO_CARDEMU
RTL8723A_TRANS_CARDEMU_TO_ACT
RTL8723A_TRANS_END
};
/* 3 Suspend Array */
struct wlan_pwr_cfg rtl8723AU_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU
RTL8723A_TRANS_CARDEMU_TO_SUS
RTL8723A_TRANS_END
};
/* 3 Resume Array */
struct wlan_pwr_cfg rtl8723AU_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_SUS_TO_CARDEMU
RTL8723A_TRANS_CARDEMU_TO_ACT
RTL8723A_TRANS_END
};
/* 3 HWPDN Array */
struct wlan_pwr_cfg rtl8723AU_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU
RTL8723A_TRANS_CARDEMU_TO_PDN
RTL8723A_TRANS_END
};
/* 3 Enter LPS */
struct wlan_pwr_cfg rtl8723AU_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS] = {
/* FW behavior */
RTL8723A_TRANS_ACT_TO_LPS
RTL8723A_TRANS_END
};
/* 3 Leave LPS */
struct wlan_pwr_cfg rtl8723AU_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS] = {
/* FW behavior */
RTL8723A_TRANS_LPS_TO_ACT
RTL8723A_TRANS_END
};

136
drivers/staging/rtl8723au/hal/Hal8723UHWImg_CE.c Normal file
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@ -0,0 +1,136 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/*Created on 2013/01/14, 15:51*/
#include "odm_precomp.h"
u32 Rtl8723UPHY_REG_Array_PG[Rtl8723UPHY_REG_Array_PGLength] = {
0xe00, 0xffffffff, 0x0a0c0c0c,
0xe04, 0xffffffff, 0x02040608,
0xe08, 0x0000ff00, 0x00000000,
0x86c, 0xffffff00, 0x00000000,
0xe10, 0xffffffff, 0x0a0c0d0e,
0xe14, 0xffffffff, 0x02040608,
0xe18, 0xffffffff, 0x0a0c0d0e,
0xe1c, 0xffffffff, 0x02040608,
0x830, 0xffffffff, 0x0a0c0c0c,
0x834, 0xffffffff, 0x02040608,
0x838, 0xffffff00, 0x00000000,
0x86c, 0x000000ff, 0x00000000,
0x83c, 0xffffffff, 0x0a0c0d0e,
0x848, 0xffffffff, 0x02040608,
0x84c, 0xffffffff, 0x0a0c0d0e,
0x868, 0xffffffff, 0x02040608,
0xe00, 0xffffffff, 0x00000000,
0xe04, 0xffffffff, 0x00000000,
0xe08, 0x0000ff00, 0x00000000,
0x86c, 0xffffff00, 0x00000000,
0xe10, 0xffffffff, 0x00000000,
0xe14, 0xffffffff, 0x00000000,
0xe18, 0xffffffff, 0x00000000,
0xe1c, 0xffffffff, 0x00000000,
0x830, 0xffffffff, 0x00000000,
0x834, 0xffffffff, 0x00000000,
0x838, 0xffffff00, 0x00000000,
0x86c, 0x000000ff, 0x00000000,
0x83c, 0xffffffff, 0x00000000,
0x848, 0xffffffff, 0x00000000,
0x84c, 0xffffffff, 0x00000000,
0x868, 0xffffffff, 0x00000000,
0xe00, 0xffffffff, 0x04040404,
0xe04, 0xffffffff, 0x00020204,
0xe08, 0x0000ff00, 0x00000000,
0x86c, 0xffffff00, 0x00000000,
0xe10, 0xffffffff, 0x06060606,
0xe14, 0xffffffff, 0x00020406,
0xe18, 0xffffffff, 0x00000000,
0xe1c, 0xffffffff, 0x00000000,
0x830, 0xffffffff, 0x04040404,
0x834, 0xffffffff, 0x00020204,
0x838, 0xffffff00, 0x00000000,
0x86c, 0x000000ff, 0x00000000,
0x83c, 0xffffffff, 0x06060606,
0x848, 0xffffffff, 0x00020406,
0x84c, 0xffffffff, 0x00000000,
0x868, 0xffffffff, 0x00000000,
0xe00, 0xffffffff, 0x00000000,
0xe04, 0xffffffff, 0x00000000,
0xe08, 0x0000ff00, 0x00000000,
0x86c, 0xffffff00, 0x00000000,
0xe10, 0xffffffff, 0x00000000,
0xe14, 0xffffffff, 0x00000000,
0xe18, 0xffffffff, 0x00000000,
0xe1c, 0xffffffff, 0x00000000,
0x830, 0xffffffff, 0x00000000,
0x834, 0xffffffff, 0x00000000,
0x838, 0xffffff00, 0x00000000,
0x86c, 0x000000ff, 0x00000000,
0x83c, 0xffffffff, 0x00000000,
0x848, 0xffffffff, 0x00000000,
0x84c, 0xffffffff, 0x00000000,
0x868, 0xffffffff, 0x00000000,
0xe00, 0xffffffff, 0x00000000,
0xe04, 0xffffffff, 0x00000000,
0xe08, 0x0000ff00, 0x00000000,
0x86c, 0xffffff00, 0x00000000,
0xe10, 0xffffffff, 0x00000000,
0xe14, 0xffffffff, 0x00000000,
0xe18, 0xffffffff, 0x00000000,
0xe1c, 0xffffffff, 0x00000000,
0x830, 0xffffffff, 0x00000000,
0x834, 0xffffffff, 0x00000000,
0x838, 0xffffff00, 0x00000000,
0x86c, 0x000000ff, 0x00000000,
0x83c, 0xffffffff, 0x00000000,
0x848, 0xffffffff, 0x00000000,
0x84c, 0xffffffff, 0x00000000,
0x868, 0xffffffff, 0x00000000,
0xe00, 0xffffffff, 0x04040404,
0xe04, 0xffffffff, 0x00020204,
0xe08, 0x0000ff00, 0x00000000,
0x86c, 0xffffff00, 0x00000000,
0xe10, 0xffffffff, 0x00000000,
0xe14, 0xffffffff, 0x00000000,
0xe18, 0xffffffff, 0x00000000,
0xe1c, 0xffffffff, 0x00000000,
0x830, 0xffffffff, 0x04040404,
0x834, 0xffffffff, 0x00020204,
0x838, 0xffffff00, 0x00000000,
0x86c, 0x000000ff, 0x00000000,
0x83c, 0xffffffff, 0x00000000,
0x848, 0xffffffff, 0x00000000,
0x84c, 0xffffffff, 0x00000000,
0x868, 0xffffffff, 0x00000000,
0xe00, 0xffffffff, 0x00000000,
0xe04, 0xffffffff, 0x00000000,
0xe08, 0x0000ff00, 0x00000000,
0x86c, 0xffffff00, 0x00000000,
0xe10, 0xffffffff, 0x00000000,
0xe14, 0xffffffff, 0x00000000,
0xe18, 0xffffffff, 0x00000000,
0xe1c, 0xffffffff, 0x00000000,
0x830, 0xffffffff, 0x00000000,
0x834, 0xffffffff, 0x00000000,
0x838, 0xffffff00, 0x00000000,
0x86c, 0x000000ff, 0x00000000,
0x83c, 0xffffffff, 0x00000000,
0x848, 0xffffffff, 0x00000000,
0x84c, 0xffffffff, 0x00000000,
0x868, 0xffffffff, 0x00000000,
};
u32 Rtl8723UMACPHY_Array_PG[Rtl8723UMACPHY_Array_PGLength] = {
0x0,
};

1063
drivers/staging/rtl8723au/hal/HalDMOutSrc8723A_CE.c Normal file
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726
drivers/staging/rtl8723au/hal/HalHWImg8723A_BB.c Normal file
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@ -0,0 +1,726 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "odm_precomp.h"
static bool CheckCondition(const u32 Condition, const u32 Hex)
{
u32 _board = (Hex & 0x000000FF);
u32 _interface = (Hex & 0x0000FF00) >> 8;
u32 _platform = (Hex & 0x00FF0000) >> 16;
u32 cond = Condition;
if (Condition == 0xCDCDCDCD)
return true;
cond = Condition & 0x000000FF;
if ((_board == cond) && cond != 0x00)
return false;
cond = Condition & 0x0000FF00;
cond = cond >> 8;
if ((_interface & cond) == 0 && cond != 0x07)
return false;
cond = Condition & 0x00FF0000;
cond = cond >> 16;
if ((_platform & cond) == 0 && cond != 0x0F)
return false;
return true;
}
/******************************************************************************
* AGC_TAB_1T.TXT
******************************************************************************/
static u32 Array_AGC_TAB_1T_8723A[] = {
0xC78, 0x7B000001,
0xC78, 0x7B010001,
0xC78, 0x7B020001,
0xC78, 0x7B030001,
0xC78, 0x7B040001,
0xC78, 0x7B050001,
0xC78, 0x7A060001,
0xC78, 0x79070001,
0xC78, 0x78080001,
0xC78, 0x77090001,
0xC78, 0x760A0001,
0xC78, 0x750B0001,
0xC78, 0x740C0001,
0xC78, 0x730D0001,
0xC78, 0x720E0001,
0xC78, 0x710F0001,
0xC78, 0x70100001,
0xC78, 0x6F110001,
0xC78, 0x6E120001,
0xC78, 0x6D130001,
0xC78, 0x6C140001,
0xC78, 0x6B150001,
0xC78, 0x6A160001,
0xC78, 0x69170001,
0xC78, 0x68180001,
0xC78, 0x67190001,
0xC78, 0x661A0001,
0xC78, 0x651B0001,
0xC78, 0x641C0001,
0xC78, 0x631D0001,
0xC78, 0x621E0001,
0xC78, 0x611F0001,
0xC78, 0x60200001,
0xC78, 0x49210001,
0xC78, 0x48220001,
0xC78, 0x47230001,
0xC78, 0x46240001,
0xC78, 0x45250001,
0xC78, 0x44260001,
0xC78, 0x43270001,
0xC78, 0x42280001,
0xC78, 0x41290001,
0xC78, 0x402A0001,
0xC78, 0x262B0001,
0xC78, 0x252C0001,
0xC78, 0x242D0001,
0xC78, 0x232E0001,
0xC78, 0x222F0001,
0xC78, 0x21300001,
0xC78, 0x20310001,
0xC78, 0x06320001,
0xC78, 0x05330001,
0xC78, 0x04340001,
0xC78, 0x03350001,
0xC78, 0x02360001,
0xC78, 0x01370001,
0xC78, 0x00380001,
0xC78, 0x00390001,
0xC78, 0x003A0001,
0xC78, 0x003B0001,
0xC78, 0x003C0001,
0xC78, 0x003D0001,
0xC78, 0x003E0001,
0xC78, 0x003F0001,
0xC78, 0x7B400001,
0xC78, 0x7B410001,
0xC78, 0x7B420001,
0xC78, 0x7B430001,
0xC78, 0x7B440001,
0xC78, 0x7B450001,
0xC78, 0x7A460001,
0xC78, 0x79470001,
0xC78, 0x78480001,
0xC78, 0x77490001,
0xC78, 0x764A0001,
0xC78, 0x754B0001,
0xC78, 0x744C0001,
0xC78, 0x734D0001,
0xC78, 0x724E0001,
0xC78, 0x714F0001,
0xC78, 0x70500001,
0xC78, 0x6F510001,
0xC78, 0x6E520001,
0xC78, 0x6D530001,
0xC78, 0x6C540001,
0xC78, 0x6B550001,
0xC78, 0x6A560001,
0xC78, 0x69570001,
0xC78, 0x68580001,
0xC78, 0x67590001,
0xC78, 0x665A0001,
0xC78, 0x655B0001,
0xC78, 0x645C0001,
0xC78, 0x635D0001,
0xC78, 0x625E0001,
0xC78, 0x615F0001,
0xC78, 0x60600001,
0xC78, 0x49610001,
0xC78, 0x48620001,
0xC78, 0x47630001,
0xC78, 0x46640001,
0xC78, 0x45650001,
0xC78, 0x44660001,
0xC78, 0x43670001,
0xC78, 0x42680001,
0xC78, 0x41690001,
0xC78, 0x406A0001,
0xC78, 0x266B0001,
0xC78, 0x256C0001,
0xC78, 0x246D0001,
0xC78, 0x236E0001,
0xC78, 0x226F0001,
0xC78, 0x21700001,
0xC78, 0x20710001,
0xC78, 0x06720001,
0xC78, 0x05730001,
0xC78, 0x04740001,
0xC78, 0x03750001,
0xC78, 0x02760001,
0xC78, 0x01770001,
0xC78, 0x00780001,
0xC78, 0x00790001,
0xC78, 0x007A0001,
0xC78, 0x007B0001,
0xC78, 0x007C0001,
0xC78, 0x007D0001,
0xC78, 0x007E0001,
0xC78, 0x007F0001,
0xC78, 0x3800001E,
0xC78, 0x3801001E,
0xC78, 0x3802001E,
0xC78, 0x3803001E,
0xC78, 0x3804001E,
0xC78, 0x3805001E,
0xC78, 0x3806001E,
0xC78, 0x3807001E,
0xC78, 0x3808001E,
0xC78, 0x3C09001E,
0xC78, 0x3E0A001E,
0xC78, 0x400B001E,
0xC78, 0x440C001E,
0xC78, 0x480D001E,
0xC78, 0x4C0E001E,
0xC78, 0x500F001E,
0xC78, 0x5210001E,
0xC78, 0x5611001E,
0xC78, 0x5A12001E,
0xC78, 0x5E13001E,
0xC78, 0x6014001E,
0xC78, 0x6015001E,
0xC78, 0x6016001E,
0xC78, 0x6217001E,
0xC78, 0x6218001E,
0xC78, 0x6219001E,
0xC78, 0x621A001E,
0xC78, 0x621B001E,
0xC78, 0x621C001E,
0xC78, 0x621D001E,
0xC78, 0x621E001E,
0xC78, 0x621F001E,
};
#define READ_NEXT_PAIR(v1, v2, i) \
do { \
i += 2; v1 = Array[i]; v2 = Array[i+1]; \
} while (0)
void ODM_ReadAndConfig_AGC_TAB_1T_8723A(struct dm_odm_t *pDM_Odm)
{
u32 hex;
u32 i;
u8 platform = 0x04;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_AGC_TAB_1T_8723A)/sizeof(u32);
u32 *Array = Array_AGC_TAB_1T_8723A;
hex = board;
hex += interfaceValue << 8;
hex += platform << 16;
hex += 0xFF000000;
for (i = 0; i < ArrayLen; i += 2) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
/* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) {
odm_ConfigBB_AGC_8723A(pDM_Odm, v1, bMaskDWord, v2);
continue;
} else {
if (!CheckCondition(Array[i], hex)) {
/* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else {
/* Configure matched pairs and skip to end of if-else. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2) {
odm_ConfigBB_AGC_8723A(pDM_Odm, v1, bMaskDWord, v2);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}
/******************************************************************************
* PHY_REG_1T.TXT
******************************************************************************/
static u32 Array_PHY_REG_1T_8723A[] = {
0x800, 0x80040000,
0x804, 0x00000003,
0x808, 0x0000FC00,
0x80C, 0x0000000A,
0x810, 0x10001331,
0x814, 0x020C3D10,
0x818, 0x02200385,
0x81C, 0x00000000,
0x820, 0x01000100,
0x824, 0x00390004,
0x828, 0x00000000,
0x82C, 0x00000000,
0x830, 0x00000000,
0x834, 0x00000000,
0x838, 0x00000000,
0x83C, 0x00000000,
0x840, 0x00010000,
0x844, 0x00000000,
0x848, 0x00000000,
0x84C, 0x00000000,
0x850, 0x00000000,
0x854, 0x00000000,
0x858, 0x569A569A,
0x85C, 0x001B25A4,
0x860, 0x66F60110,
0x864, 0x061F0130,
0x868, 0x00000000,
0x86C, 0x32323200,
0x870, 0x07000760,
0x874, 0x22004000,
0x878, 0x00000808,
0x87C, 0x00000000,
0x880, 0xC0083070,
0x884, 0x000004D5,
0x888, 0x00000000,
0x88C, 0xCCC000C0,
0x890, 0x00000800,
0x894, 0xFFFFFFFE,
0x898, 0x40302010,
0x89C, 0x00706050,
0x900, 0x00000000,
0x904, 0x00000023,
0x908, 0x00000000,
0x90C, 0x81121111,
0xA00, 0x00D047C8,
0xA04, 0x80FF000C,
0xA08, 0x8C838300,
0xA0C, 0x2E68120F,
0xA10, 0x9500BB78,
0xA14, 0x11144028,
0xA18, 0x00881117,
0xA1C, 0x89140F00,
0xA20, 0x1A1B0000,
0xA24, 0x090E1317,
0xA28, 0x00000204,
0xA2C, 0x00D30000,
0xA70, 0x101FBF00,
0xA74, 0x00000007,
0xA78, 0x00000900,
0xC00, 0x48071D40,
0xC04, 0x03A05611,
0xC08, 0x000000E4,
0xC0C, 0x6C6C6C6C,
0xC10, 0x08800000,
0xC14, 0x40000100,
0xC18, 0x08800000,
0xC1C, 0x40000100,
0xC20, 0x00000000,
0xC24, 0x00000000,
0xC28, 0x00000000,
0xC2C, 0x00000000,
0xC30, 0x69E9AC44,
0xFF0F011F, 0xABCD,
0xC34, 0x469652CF,
0xCDCDCDCD, 0xCDCD,
0xC34, 0x469652AF,
0xFF0F011F, 0xDEAD,
0xC38, 0x49795994,
0xC3C, 0x0A97971C,
0xC40, 0x1F7C403F,
0xC44, 0x000100B7,
0xC48, 0xEC020107,
0xC4C, 0x007F037F,
0xC50, 0x69543420,
0xC54, 0x43BC0094,
0xC58, 0x69543420,
0xC5C, 0x433C0094,
0xC60, 0x00000000,
0xFF0F011F, 0xABCD,
0xC64, 0x7116848B,
0xCDCDCDCD, 0xCDCD,
0xC64, 0x7112848B,
0xFF0F011F, 0xDEAD,
0xC68, 0x47C00BFF,
0xC6C, 0x00000036,
0xC70, 0x2C7F000D,
0xC74, 0x018610DB,
0xC78, 0x0000001F,
0xC7C, 0x00B91612,
0xC80, 0x40000100,
0xC84, 0x20F60000,
0xC88, 0x40000100,
0xC8C, 0x20200000,
0xC90, 0x00121820,
0xC94, 0x00000000,
0xC98, 0x00121820,
0xC9C, 0x00007F7F,
0xCA0, 0x00000000,
0xCA4, 0x00000080,
0xCA8, 0x00000000,
0xCAC, 0x00000000,
0xCB0, 0x00000000,
0xCB4, 0x00000000,
0xCB8, 0x00000000,
0xCBC, 0x28000000,
0xCC0, 0x00000000,
0xCC4, 0x00000000,
0xCC8, 0x00000000,
0xCCC, 0x00000000,
0xCD0, 0x00000000,
0xCD4, 0x00000000,
0xCD8, 0x64B22427,
0xCDC, 0x00766932,
0xCE0, 0x00222222,
0xCE4, 0x00000000,
0xCE8, 0x37644302,
0xCEC, 0x2F97D40C,
0xD00, 0x00080740,
0xD04, 0x00020401,
0xD08, 0x0000907F,
0xD0C, 0x20010201,
0xD10, 0xA0633333,
0xD14, 0x3333BC43,
0xD18, 0x7A8F5B6B,
0xD2C, 0xCC979975,
0xD30, 0x00000000,
0xD34, 0x80608000,
0xD38, 0x00000000,
0xD3C, 0x00027293,
0xD40, 0x00000000,
0xD44, 0x00000000,
0xD48, 0x00000000,
0xD4C, 0x00000000,
0xD50, 0x6437140A,
0xD54, 0x00000000,
0xD58, 0x00000000,
0xD5C, 0x30032064,
0xD60, 0x4653DE68,
0xD64, 0x04518A3C,
0xD68, 0x00002101,
0xD6C, 0x2A201C16,
0xD70, 0x1812362E,
0xD74, 0x322C2220,
0xD78, 0x000E3C24,
0xE00, 0x2A2A2A2A,
0xE04, 0x2A2A2A2A,
0xE08, 0x03902A2A,
0xE10, 0x2A2A2A2A,
0xE14, 0x2A2A2A2A,
0xE18, 0x2A2A2A2A,
0xE1C, 0x2A2A2A2A,
0xE28, 0x00000000,
0xE30, 0x1000DC1F,
0xE34, 0x10008C1F,
0xE38, 0x02140102,
0xE3C, 0x681604C2,
0xE40, 0x01007C00,
0xE44, 0x01004800,
0xE48, 0xFB000000,
0xE4C, 0x000028D1,
0xE50, 0x1000DC1F,
0xE54, 0x10008C1F,
0xE58, 0x02140102,
0xE5C, 0x28160D05,
0xE60, 0x00000008,
0xE68, 0x001B25A4,
0xE6C, 0x631B25A0,
0xE70, 0x631B25A0,
0xE74, 0x081B25A0,
0xE78, 0x081B25A0,
0xE7C, 0x081B25A0,
0xE80, 0x081B25A0,
0xE84, 0x631B25A0,
0xE88, 0x081B25A0,
0xE8C, 0x631B25A0,
0xED0, 0x631B25A0,
0xED4, 0x631B25A0,
0xED8, 0x631B25A0,
0xEDC, 0x001B25A0,
0xEE0, 0x001B25A0,
0xEEC, 0x6B1B25A0,
0xF14, 0x00000003,
0xF4C, 0x00000000,
0xF00, 0x00000300,
};
void ODM_ReadAndConfig_PHY_REG_1T_8723A(struct dm_odm_t *pDM_Odm)
{
u32 hex = 0;
u32 i = 0;
u8 platform = 0x04;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_PHY_REG_1T_8723A)/sizeof(u32);
u32 *Array = Array_PHY_REG_1T_8723A;
hex += board;
hex += interfaceValue << 8;
hex += platform << 16;
hex += 0xFF000000;
for (i = 0; i < ArrayLen; i += 2) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
/* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) {
odm_ConfigBB_PHY_8723A(pDM_Odm, v1, bMaskDWord, v2);
continue;
} else {
if (!CheckCondition(Array[i], hex)) {
/* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else {
/* Configure matched pairs and skip to end of if-else. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2) {
odm_ConfigBB_PHY_8723A(pDM_Odm, v1, bMaskDWord, v2);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}
/******************************************************************************
* PHY_REG_MP.TXT
******************************************************************************/
static u32 Array_PHY_REG_MP_8723A[] = {
0xC30, 0x69E9AC4A,
0xC3C, 0x0A979718,
};
void ODM_ReadAndConfig_PHY_REG_MP_8723A(struct dm_odm_t *pDM_Odm)
{
u32 hex = 0;
u32 i = 0;
u8 platform = 0x04;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_PHY_REG_MP_8723A)/sizeof(u32);
u32 *Array = Array_PHY_REG_MP_8723A;
hex += board;
hex += interfaceValue << 8;
hex += platform << 16;
hex += 0xFF000000;
for (i = 0; i < ArrayLen; i += 2) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
/* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) {
odm_ConfigBB_PHY_8723A(pDM_Odm, v1, bMaskDWord, v2);
continue;
} else {
if (!CheckCondition(Array[i], hex)) {
/* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else {
/* Configure matched pairs and skip to end of if-else. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2) {
odm_ConfigBB_PHY_8723A(pDM_Odm, v1, bMaskDWord, v2);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
static u32 Array_PHY_REG_PG_8723A[] = {
0xE00, 0xFFFFFFFF, 0x0A0C0C0C,
0xE04, 0xFFFFFFFF, 0x02040608,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x0A0C0D0E,
0xE14, 0xFFFFFFFF, 0x02040608,
0xE18, 0xFFFFFFFF, 0x0A0C0D0E,
0xE1C, 0xFFFFFFFF, 0x02040608,
0x830, 0xFFFFFFFF, 0x0A0C0C0C,
0x834, 0xFFFFFFFF, 0x02040608,
0x838, 0xFFFFFF00, 0x00000000,
0x86C, 0x000000FF, 0x00000000,
0x83C, 0xFFFFFFFF, 0x0A0C0D0E,
0x848, 0xFFFFFFFF, 0x02040608,
0x84C, 0xFFFFFFFF, 0x0A0C0D0E,
0x868, 0xFFFFFFFF, 0x02040608,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0x830, 0xFFFFFFFF, 0x00000000,
0x834, 0xFFFFFFFF, 0x00000000,
0x838, 0xFFFFFF00, 0x00000000,
0x86C, 0x000000FF, 0x00000000,
0x83C, 0xFFFFFFFF, 0x00000000,
0x848, 0xFFFFFFFF, 0x00000000,
0x84C, 0xFFFFFFFF, 0x00000000,
0x868, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x04040404,
0xE04, 0xFFFFFFFF, 0x00020204,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x06060606,
0xE14, 0xFFFFFFFF, 0x00020406,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0x830, 0xFFFFFFFF, 0x04040404,
0x834, 0xFFFFFFFF, 0x00020204,
0x838, 0xFFFFFF00, 0x00000000,
0x86C, 0x000000FF, 0x00000000,
0x83C, 0xFFFFFFFF, 0x06060606,
0x848, 0xFFFFFFFF, 0x00020406,
0x84C, 0xFFFFFFFF, 0x00000000,
0x868, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0x830, 0xFFFFFFFF, 0x00000000,
0x834, 0xFFFFFFFF, 0x00000000,
0x838, 0xFFFFFF00, 0x00000000,
0x86C, 0x000000FF, 0x00000000,
0x83C, 0xFFFFFFFF, 0x00000000,
0x848, 0xFFFFFFFF, 0x00000000,
0x84C, 0xFFFFFFFF, 0x00000000,
0x868, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0x830, 0xFFFFFFFF, 0x00000000,
0x834, 0xFFFFFFFF, 0x00000000,
0x838, 0xFFFFFF00, 0x00000000,
0x86C, 0x000000FF, 0x00000000,
0x83C, 0xFFFFFFFF, 0x00000000,
0x848, 0xFFFFFFFF, 0x00000000,
0x84C, 0xFFFFFFFF, 0x00000000,
0x868, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x04040404,
0xE04, 0xFFFFFFFF, 0x00020204,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0x830, 0xFFFFFFFF, 0x04040404,
0x834, 0xFFFFFFFF, 0x00020204,
0x838, 0xFFFFFF00, 0x00000000,
0x86C, 0x000000FF, 0x00000000,
0x83C, 0xFFFFFFFF, 0x00000000,
0x848, 0xFFFFFFFF, 0x00000000,
0x84C, 0xFFFFFFFF, 0x00000000,
0x868, 0xFFFFFFFF, 0x00000000,
0xE00, 0xFFFFFFFF, 0x00000000,
0xE04, 0xFFFFFFFF, 0x00000000,
0xE08, 0x0000FF00, 0x00000000,
0x86C, 0xFFFFFF00, 0x00000000,
0xE10, 0xFFFFFFFF, 0x00000000,
0xE14, 0xFFFFFFFF, 0x00000000,
0xE18, 0xFFFFFFFF, 0x00000000,
0xE1C, 0xFFFFFFFF, 0x00000000,
0x830, 0xFFFFFFFF, 0x00000000,
0x834, 0xFFFFFFFF, 0x00000000,
0x838, 0xFFFFFF00, 0x00000000,
0x86C, 0x000000FF, 0x00000000,
0x83C, 0xFFFFFFFF, 0x00000000,
0x848, 0xFFFFFFFF, 0x00000000,
0x84C, 0xFFFFFFFF, 0x00000000,
0x868, 0xFFFFFFFF, 0x00000000,
};
void ODM_ReadAndConfig_PHY_REG_PG_8723A(struct dm_odm_t *pDM_Odm)
{
u32 hex = 0;
u32 i = 0;
u8 platform = 0x04;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_PHY_REG_PG_8723A)/sizeof(u32);
u32 *Array = Array_PHY_REG_PG_8723A;
hex += board;
hex += interfaceValue << 8;
hex += platform << 16;
hex += 0xFF000000;
for (i = 0; i < ArrayLen; i += 3) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
u32 v3 = Array[i+2];
/* this line is a line of pure_body */
if (v1 < 0xCDCDCDCD) {
odm_ConfigBB_PHY_REG_PG_8723A(pDM_Odm, v1, v2, v3);
continue;
} else { /* this line is the start of branch */
if (!CheckCondition(Array[i], hex)) {
/* don't need the hw_body */
i += 2; /* skip the pair of expression */
v1 = Array[i];
v2 = Array[i+1];
v3 = Array[i+2];
while (v2 != 0xDEAD) {
i += 3;
v1 = Array[i];
v2 = Array[i+1];
v3 = Array[i+1];
}
}
}
}
}

188
drivers/staging/rtl8723au/hal/HalHWImg8723A_MAC.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "odm_precomp.h"
static bool CheckCondition(const u32 Condition, const u32 Hex)
{
u32 _board = (Hex & 0x000000FF);
u32 _interface = (Hex & 0x0000FF00) >> 8;
u32 _platform = (Hex & 0x00FF0000) >> 16;
u32 cond = Condition;
if (Condition == 0xCDCDCDCD)
return true;
cond = Condition & 0x000000FF;
if ((_board == cond) && cond != 0x00)
return false;
cond = Condition & 0x0000FF00;
cond = cond >> 8;
if ((_interface & cond) == 0 && cond != 0x07)
return false;
cond = Condition & 0x00FF0000;
cond = cond >> 16;
if ((_platform & cond) == 0 && cond != 0x0F)
return false;
return true;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
static u32 Array_MAC_REG_8723A[] = {
0x420, 0x00000080,
0x423, 0x00000000,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000006,
0x437, 0x00000007,
0x438, 0x00000000,
0x439, 0x00000000,
0x43A, 0x00000000,
0x43B, 0x00000001,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000006,
0x43F, 0x00000007,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000015,
0x445, 0x000000F0,
0x446, 0x0000000F,
0x447, 0x00000000,
0x458, 0x00000041,
0x459, 0x000000A8,
0x45A, 0x00000072,
0x45B, 0x000000B9,
0x460, 0x00000066,
0x461, 0x00000066,
0x462, 0x00000008,
0x463, 0x00000003,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x515, 0x00000010,
0x516, 0x0000000A,
0x517, 0x00000010,
0x51A, 0x00000016,
0x524, 0x0000000F,
0x525, 0x0000004F,
0x546, 0x00000040,
0x547, 0x00000000,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55A, 0x00000002,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x652, 0x00000020,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
};
void ODM_ReadAndConfig_MAC_REG_8723A(struct dm_odm_t *pDM_Odm)
{
#define READ_NEXT_PAIR(v1, v2, i) \
do { \
i += 2; v1 = Array[i]; v2 = Array[i+1]; \
} while (0)
u32 hex = 0;
u32 i = 0;
u8 platform = 0x04;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_MAC_REG_8723A)/sizeof(u32);
u32 *Array = Array_MAC_REG_8723A;
hex += board;
hex += interfaceValue << 8;
hex += platform << 16;
hex += 0xFF000000;
for (i = 0; i < ArrayLen; i += 2) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
/* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) {
odm_ConfigMAC_8723A(pDM_Odm, v1, (u8)v2);
continue;
} else {
if (!CheckCondition(Array[i], hex)) {
/* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else {
/* Configure matched pairs and skip to end of if-else. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2) {
odm_ConfigMAC_8723A(pDM_Odm, v1, (u8)v2);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}

259
drivers/staging/rtl8723au/hal/HalHWImg8723A_RF.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "odm_precomp.h"
static bool CheckCondition(const u32 Condition, const u32 Hex)
{
u32 _board = (Hex & 0x000000FF);
u32 _interface = (Hex & 0x0000FF00) >> 8;
u32 _platform = (Hex & 0x00FF0000) >> 16;
u32 cond = Condition;
if (Condition == 0xCDCDCDCD)
return true;
cond = Condition & 0x000000FF;
if ((_board == cond) && cond != 0x00)
return false;
cond = Condition & 0x0000FF00;
cond = cond >> 8;
if ((_interface & cond) == 0 && cond != 0x07)
return false;
cond = Condition & 0x00FF0000;
cond = cond >> 16;
if ((_platform & cond) == 0 && cond != 0x0F)
return false;
return true;
}
/******************************************************************************
* RadioA_1T.TXT
******************************************************************************/
static u32 Array_RadioA_1T_8723A[] = {
0x000, 0x00030159,
0x001, 0x00031284,
0x002, 0x00098000,
0xFF0F011F, 0xABCD,
0x003, 0x00018C63,
0xCDCDCDCD, 0xCDCD,
0x003, 0x00039C63,
0xFF0F011F, 0xDEAD,
0x004, 0x000210E7,
0x009, 0x0002044F,
0x00A, 0x0001A3F1,
0x00B, 0x00014787,
0x00C, 0x000896FE,
0x00D, 0x0000E02C,
0x00E, 0x00039CE7,
0x00F, 0x00000451,
0x019, 0x00000000,
0x01A, 0x00030355,
0x01B, 0x00060A00,
0x01C, 0x000FC378,
0x01D, 0x000A1250,
0x01E, 0x0000024F,
0x01F, 0x00000000,
0x020, 0x0000B614,
0x021, 0x0006C000,
0x022, 0x00000000,
0x023, 0x00001558,
0x024, 0x00000060,
0x025, 0x00000483,
0x026, 0x0004F000,
0x027, 0x000EC7D9,
0x028, 0x00057730,
0x029, 0x00004783,
0x02A, 0x00000001,
0x02B, 0x00021334,
0x02A, 0x00000000,
0x02B, 0x00000054,
0x02A, 0x00000001,
0x02B, 0x00000808,
0x02B, 0x00053333,
0x02C, 0x0000000C,
0x02A, 0x00000002,
0x02B, 0x00000808,
0x02B, 0x0005B333,
0x02C, 0x0000000D,
0x02A, 0x00000003,
0x02B, 0x00000808,
0x02B, 0x00063333,
0x02C, 0x0000000D,
0x02A, 0x00000004,
0x02B, 0x00000808,
0x02B, 0x0006B333,
0x02C, 0x0000000D,
0x02A, 0x00000005,
0x02B, 0x00000808,
0x02B, 0x00073333,
0x02C, 0x0000000D,
0x02A, 0x00000006,
0x02B, 0x00000709,
0x02B, 0x0005B333,
0x02C, 0x0000000D,
0x02A, 0x00000007,
0x02B, 0x00000709,
0x02B, 0x00063333,
0x02C, 0x0000000D,
0x02A, 0x00000008,
0x02B, 0x0000060A,
0x02B, 0x0004B333,
0x02C, 0x0000000D,
0x02A, 0x00000009,
0x02B, 0x0000060A,
0x02B, 0x00053333,
0x02C, 0x0000000D,
0x02A, 0x0000000A,
0x02B, 0x0000060A,
0x02B, 0x0005B333,
0x02C, 0x0000000D,
0x02A, 0x0000000B,
0x02B, 0x0000060A,
0x02B, 0x00063333,
0x02C, 0x0000000D,
0x02A, 0x0000000C,
0x02B, 0x0000060A,
0x02B, 0x0006B333,
0x02C, 0x0000000D,
0x02A, 0x0000000D,
0x02B, 0x0000060A,
0x02B, 0x00073333,
0x02C, 0x0000000D,
0x02A, 0x0000000E,
0x02B, 0x0000050B,
0x02B, 0x00066666,
0x02C, 0x0000001A,
0x02A, 0x000E0000,
0x010, 0x0004000F,
0x011, 0x000E31FC,
0x010, 0x0006000F,
0x011, 0x000FF9F8,
0x010, 0x0002000F,
0x011, 0x000203F9,
0x010, 0x0003000F,
0x011, 0x000FF500,
0x010, 0x00000000,
0x011, 0x00000000,
0x010, 0x0008000F,
0x011, 0x0003F100,
0x010, 0x0009000F,
0x011, 0x00023100,
0x012, 0x00032000,
0x012, 0x00071000,
0x012, 0x000B0000,
0x012, 0x000FC000,
0x013, 0x000287B3,
0x013, 0x000244B7,
0x013, 0x000204AB,
0x013, 0x0001C49F,
0x013, 0x00018493,
0x013, 0x0001429B,
0x013, 0x00010299,
0x013, 0x0000C29C,
0x013, 0x000081A0,
0x013, 0x000040AC,
0x013, 0x00000020,
0x014, 0x0001944C,
0x014, 0x00059444,
0x014, 0x0009944C,
0x014, 0x000D9444,
0xFF0F011F, 0xABCD,
0x015, 0x0000F424,
0x015, 0x0004F424,
0x015, 0x0008F424,
0x015, 0x000CF424,
0xCDCDCDCD, 0xCDCD,
0x015, 0x0000F474,
0x015, 0x0004F477,
0x015, 0x0008F455,
0x015, 0x000CF455,
0xFF0F011F, 0xDEAD,
0x016, 0x00000339,
0x016, 0x00040339,
0x016, 0x00080339,
0xFF0F011F, 0xABCD,
0x016, 0x000C0356,
0xCDCDCDCD, 0xCDCD,
0x016, 0x000C0366,
0xFF0F011F, 0xDEAD,
0x000, 0x00010159,
0x018, 0x0000F401,
0x0FE, 0x00000000,
0x0FE, 0x00000000,
0x01F, 0x00000003,
0x0FE, 0x00000000,
0x0FE, 0x00000000,
0x01E, 0x00000247,
0x01F, 0x00000000,
0x000, 0x00030159,
};
void ODM_ReadAndConfig_RadioA_1T_8723A(struct dm_odm_t *pDM_Odm)
{
#define READ_NEXT_PAIR(v1, v2, i) \
do { \
i += 2; v1 = Array[i]; v2 = Array[i+1];\
} while (0)
u32 hex = 0;
u32 i = 0;
u8 platform = 0x04;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_RadioA_1T_8723A)/sizeof(u32);
u32 *Array = Array_RadioA_1T_8723A;
hex += board;
hex += interfaceValue << 8;
hex += platform << 16;
hex += 0xFF000000;
for (i = 0; i < ArrayLen; i += 2) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
/* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) {
odm_ConfigRF_RadioA_8723A(pDM_Odm, v1, v2);
continue;
} else {
if (!CheckCondition(Array[i], hex)) {
/* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else {
/* Configure matched pairs and skip to end of if-else. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2) {
odm_ConfigRF_RadioA_8723A(pDM_Odm, v1, v2);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}

163
drivers/staging/rtl8723au/hal/HalPwrSeqCmd.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
HalPwrSeqCmd.c
Abstract:
Implement HW Power sequence configuration CMD handling routine for
Realtek devices.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
2011-07-07 Roger Create.
--*/
#include <HalPwrSeqCmd.h>
/* */
/* Description: */
/* This routine deal with the Power Configuration CMDs parsing
for RTL8723/RTL8188E Series IC. */
/* */
/* Assumption: */
/* We should follow specific format which was released from
HW SD. */
/* */
/* 2011.07.07, added by Roger. */
/* */
u8 HalPwrSeqCmdParsing23a(struct rtw_adapter *padapter, u8 CutVersion,
u8 FabVersion, u8 InterfaceType,
struct wlan_pwr_cfg PwrSeqCmd[])
{
struct wlan_pwr_cfg PwrCfgCmd = { 0 };
u8 bPollingBit = false;
u32 AryIdx = 0;
u8 value = 0;
u32 offset = 0;
u32 pollingCount = 0; /* polling autoload done. */
u32 maxPollingCnt = 5000;
do {
PwrCfgCmd = PwrSeqCmd[AryIdx];
RT_TRACE(_module_hal_init_c_, _drv_info_,
("HalPwrSeqCmdParsing23a: offset(%#x) cut_msk(%#x) "
"fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) "
"msk(%#x) value(%#x)\n",
GET_PWR_CFG_OFFSET(PwrCfgCmd),
GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
GET_PWR_CFG_BASE(PwrCfgCmd),
GET_PWR_CFG_CMD(PwrCfgCmd),
GET_PWR_CFG_MASK(PwrCfgCmd),
GET_PWR_CFG_VALUE(PwrCfgCmd)));
/* 2 Only Handle the command whose FAB, CUT, and Interface are
matched */
if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
case PWR_CMD_READ:
RT_TRACE(_module_hal_init_c_, _drv_info_,
("HalPwrSeqCmdParsing23a: "
"PWR_CMD_READ\n"));
break;
case PWR_CMD_WRITE:
RT_TRACE(_module_hal_init_c_, _drv_info_,
("HalPwrSeqCmdParsing23a: "
"PWR_CMD_WRITE\n"));
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
/* Read the value from system register */
value = rtw_read8(padapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) &
GET_PWR_CFG_MASK(PwrCfgCmd));
/* Write the value back to sytem register */
rtw_write8(padapter, offset, value);
break;
case PWR_CMD_POLLING:
RT_TRACE(_module_hal_init_c_, _drv_info_,
("HalPwrSeqCmdParsing23a: "
"PWR_CMD_POLLING\n"));
bPollingBit = false;
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
do {
value = rtw_read8(padapter, offset);
value &= GET_PWR_CFG_MASK(PwrCfgCmd);
if (value ==
(GET_PWR_CFG_VALUE(PwrCfgCmd) &
GET_PWR_CFG_MASK(PwrCfgCmd)))
bPollingBit = true;
else
udelay(10);
if (pollingCount++ > maxPollingCnt) {
DBG_8723A("Fail to polling "
"Offset[%#x]\n",
offset);
return false;
}
} while (!bPollingBit);
break;
case PWR_CMD_DELAY:
RT_TRACE(_module_hal_init_c_, _drv_info_,
("HalPwrSeqCmdParsing23a: "
"PWR_CMD_DELAY\n"));
if (GET_PWR_CFG_VALUE(PwrCfgCmd) ==
PWRSEQ_DELAY_US)
udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
else
udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd) *
1000);
break;
case PWR_CMD_END:
/* When this command is parsed, end
the process */
RT_TRACE(_module_hal_init_c_, _drv_info_,
("HalPwrSeqCmdParsing23a: "
"PWR_CMD_END\n"));
return true;
break;
default:
RT_TRACE(_module_hal_init_c_, _drv_err_,
("HalPwrSeqCmdParsing23a: "
"Unknown CMD!!\n"));
break;
}
}
AryIdx++; /* Add Array Index */
} while (1);
return true;
}

881
drivers/staging/rtl8723au/hal/hal_com.c Normal file
View File

@ -0,0 +1,881 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include <osdep_service.h>
#include <drv_types.h>
#include <hal_intf.h>
#include <hal_com.h>
#include <rtl8723a_hal.h>
#define _HAL_INIT_C_
void dump_chip_info23a(struct hal_version ChipVersion)
{
int cnt = 0;
u8 buf[128];
cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723A_");
cnt += sprintf((buf + cnt), "%s_", IS_NORMAL_CHIP(ChipVersion) ?
"Normal_Chip" : "Test_Chip");
cnt += sprintf((buf + cnt), "%s_",
IS_CHIP_VENDOR_TSMC(ChipVersion) ? "TSMC" : "UMC");
if (IS_A_CUT(ChipVersion))
cnt += sprintf((buf + cnt), "A_CUT_");
else if (IS_B_CUT(ChipVersion))
cnt += sprintf((buf + cnt), "B_CUT_");
else if (IS_C_CUT(ChipVersion))
cnt += sprintf((buf + cnt), "C_CUT_");
else if (IS_D_CUT(ChipVersion))
cnt += sprintf((buf + cnt), "D_CUT_");
else if (IS_E_CUT(ChipVersion))
cnt += sprintf((buf + cnt), "E_CUT_");
else
cnt += sprintf((buf + cnt), "UNKNOWN_CUT(%d)_",
ChipVersion.CUTVersion);
if (IS_1T1R(ChipVersion))
cnt += sprintf((buf + cnt), "1T1R_");
else if (IS_1T2R(ChipVersion))
cnt += sprintf((buf + cnt), "1T2R_");
else if (IS_2T2R(ChipVersion))
cnt += sprintf((buf + cnt), "2T2R_");
else
cnt += sprintf((buf + cnt), "UNKNOWN_RFTYPE(%d)_",
ChipVersion.RFType);
cnt += sprintf((buf + cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
DBG_8723A("%s", buf);
}
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
/* return the final channel plan decision */
/* hw_channel_plan: channel plan from HW (efuse/eeprom) */
/* sw_channel_plan: channel plan from SW (registry/module param) */
/* def_channel_plan: channel plan used when the former two is invalid */
u8 hal_com_get_channel_plan23a(struct rtw_adapter *padapter, u8 hw_channel_plan,
u8 sw_channel_plan, u8 def_channel_plan,
bool AutoLoadFail)
{
u8 swConfig;
u8 chnlPlan;
swConfig = true;
if (!AutoLoadFail) {
if (!rtw_is_channel_plan_valid(sw_channel_plan))
swConfig = false;
if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
swConfig = false;
}
if (swConfig == true)
chnlPlan = sw_channel_plan;
else
chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
if (!rtw_is_channel_plan_valid(chnlPlan))
chnlPlan = def_channel_plan;
return chnlPlan;
}
u8 MRateToHwRate23a(u8 rate)
{
u8 ret = DESC_RATE1M;
switch (rate) {
/* CCK and OFDM non-HT rates */
case IEEE80211_CCK_RATE_1MB:
ret = DESC_RATE1M;
break;
case IEEE80211_CCK_RATE_2MB:
ret = DESC_RATE2M;
break;
case IEEE80211_CCK_RATE_5MB:
ret = DESC_RATE5_5M;
break;
case IEEE80211_CCK_RATE_11MB:
ret = DESC_RATE11M;
break;
case IEEE80211_OFDM_RATE_6MB:
ret = DESC_RATE6M;
break;
case IEEE80211_OFDM_RATE_9MB:
ret = DESC_RATE9M;
break;
case IEEE80211_OFDM_RATE_12MB:
ret = DESC_RATE12M;
break;
case IEEE80211_OFDM_RATE_18MB:
ret = DESC_RATE18M;
break;
case IEEE80211_OFDM_RATE_24MB:
ret = DESC_RATE24M;
break;
case IEEE80211_OFDM_RATE_36MB:
ret = DESC_RATE36M;
break;
case IEEE80211_OFDM_RATE_48MB:
ret = DESC_RATE48M;
break;
case IEEE80211_OFDM_RATE_54MB:
ret = DESC_RATE54M;
break;
/* HT rates since here */
/* case MGN_MCS0: ret = DESC_RATEMCS0; break; */
/* case MGN_MCS1: ret = DESC_RATEMCS1; break; */
/* case MGN_MCS2: ret = DESC_RATEMCS2; break; */
/* case MGN_MCS3: ret = DESC_RATEMCS3; break; */
/* case MGN_MCS4: ret = DESC_RATEMCS4; break; */
/* case MGN_MCS5: ret = DESC_RATEMCS5; break; */
/* case MGN_MCS6: ret = DESC_RATEMCS6; break; */
/* case MGN_MCS7: ret = DESC_RATEMCS7; break; */
default:
break;
}
return ret;
}
void HalSetBrateCfg23a(struct rtw_adapter *padapter, u8 *mBratesOS)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
u8 i, is_brate, brate;
u16 brate_cfg = 0;
u8 rate_index;
for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
brate = mBratesOS[i] & 0x7f;
if (is_brate) {
switch (brate) {
case IEEE80211_CCK_RATE_1MB:
brate_cfg |= RATE_1M;
break;
case IEEE80211_CCK_RATE_2MB:
brate_cfg |= RATE_2M;
break;
case IEEE80211_CCK_RATE_5MB:
brate_cfg |= RATE_5_5M;
break;
case IEEE80211_CCK_RATE_11MB:
brate_cfg |= RATE_11M;
break;
case IEEE80211_OFDM_RATE_6MB:
brate_cfg |= RATE_6M;
break;
case IEEE80211_OFDM_RATE_9MB:
brate_cfg |= RATE_9M;
break;
case IEEE80211_OFDM_RATE_12MB:
brate_cfg |= RATE_12M;
break;
case IEEE80211_OFDM_RATE_18MB:
brate_cfg |= RATE_18M;
break;
case IEEE80211_OFDM_RATE_24MB:
brate_cfg |= RATE_24M;
break;
case IEEE80211_OFDM_RATE_36MB:
brate_cfg |= RATE_36M;
break;
case IEEE80211_OFDM_RATE_48MB:
brate_cfg |= RATE_48M;
break;
case IEEE80211_OFDM_RATE_54MB:
brate_cfg |= RATE_54M;
break;
}
}
}
/* 2007.01.16, by Emily */
/* Select RRSR (in Legacy-OFDM and CCK) */
/* For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M,
and 1M from the Basic rate. */
/* We do not use other rates. */
/* 2011.03.30 add by Luke Lee */
/* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */
/* because CCK 2M has poor TXEVM */
/* CCK 5.5M & 11M ACK should be enabled for better
performance */
brate_cfg = (brate_cfg | 0xd) & 0x15d;
pHalData->BasicRateSet = brate_cfg;
brate_cfg |= 0x01; /* default enable 1M ACK rate */
DBG_8723A("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", brate_cfg);
/* Set RRSR rate table. */
rtw_write8(padapter, REG_RRSR, brate_cfg & 0xff);
rtw_write8(padapter, REG_RRSR + 1, (brate_cfg >> 8) & 0xff);
rtw_write8(padapter, REG_RRSR + 2,
rtw_read8(padapter, REG_RRSR + 2) & 0xf0);
rate_index = 0;
/* Set RTS initial rate */
while (brate_cfg > 0x1) {
brate_cfg = (brate_cfg >> 1);
rate_index++;
}
/* Ziv - Check */
rtw_write8(padapter, REG_INIRTS_RATE_SEL, rate_index);
return;
}
static void _OneOutPipeMapping(struct rtw_adapter *pAdapter)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0]; /* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0]; /* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0]; /* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0]; /* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0]; /* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0]; /* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0]; /* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0]; /* TXCMD */
}
static void _TwoOutPipeMapping(struct rtw_adapter *pAdapter, bool bWIFICfg)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if (bWIFICfg) { /* WMM */
/* BK, BE, VI, VO, BCN, CMD, MGT, HIGH, HCCA */
/* 0, 1, 0, 1, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1]; /* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0]; /* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1]; /* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0]; /* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0]; /* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0]; /* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0]; /* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0]; /* TXCMD*/
} else { /* typical setting */
/* BK, BE, VI, VO, BCN, CMD, MGT, HIGH, HCCA */
/* 1, 1, 0, 0, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0]; /* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0]; /* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1]; /* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1]; /* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0]; /* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0]; /* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0]; /* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0]; /* TXCMD*/
}
}
static void _ThreeOutPipeMapping(struct rtw_adapter *pAdapter, bool bWIFICfg)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if (bWIFICfg) { /* for WMM */
/* BK, BE, VI, VO, BCN, CMD, MGT, HIGH, HCCA */
/* 1, 2, 1, 0, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:N, 2:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0]; /* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1]; /* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2]; /* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1]; /* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0]; /* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0]; /* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0]; /* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0]; /* TXCMD*/
} else { /* typical setting */
/* BK, BE, VI, VO, BCN, CMD, MGT, HIGH, HCCA */
/* 2, 2, 1, 0, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:N, 2:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0]; /* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1]; /* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2]; /* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2]; /* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0]; /* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0]; /* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0]; /* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0]; /* TXCMD*/
}
}
bool Hal_MappingOutPipe23a(struct rtw_adapter *pAdapter, u8 NumOutPipe)
{
struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
bool bWIFICfg = (pregistrypriv->wifi_spec) ? true : false;
bool result = true;
switch (NumOutPipe) {
case 2:
_TwoOutPipeMapping(pAdapter, bWIFICfg);
break;
case 3:
_ThreeOutPipeMapping(pAdapter, bWIFICfg);
break;
case 1:
_OneOutPipeMapping(pAdapter);
break;
default:
result = false;
break;
}
return result;
}
void hal_init_macaddr23a(struct rtw_adapter *adapter)
{
rtw_hal_set_hwreg23a(adapter, HW_VAR_MAC_ADDR,
adapter->eeprompriv.mac_addr);
}
/*
* C2H event format:
* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID
* BITS [127:120] [119:16] [15:8] [7:4] [3:0]
*/
void c2h_evt_clear23a(struct rtw_adapter *adapter)
{
rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
}
s32 c2h_evt_read23a(struct rtw_adapter *adapter, u8 *buf)
{
s32 ret = _FAIL;
struct c2h_evt_hdr *c2h_evt;
int i;
u8 trigger;
if (buf == NULL)
goto exit;
trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
if (trigger == C2H_EVT_HOST_CLOSE)
goto exit; /* Not ready */
else if (trigger != C2H_EVT_FW_CLOSE)
goto clear_evt; /* Not a valid value */
c2h_evt = (struct c2h_evt_hdr *)buf;
memset(c2h_evt, 0, 16);
*buf = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
*(buf + 1) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1);
RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read23a(): ",
&c2h_evt, sizeof(c2h_evt));
if (0) {
DBG_8723A("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n",
__func__, c2h_evt->id, c2h_evt->plen, c2h_evt->seq,
trigger);
}
/* Read the content */
for (i = 0; i < c2h_evt->plen; i++)
c2h_evt->payload[i] = rtw_read8(adapter,
REG_C2HEVT_MSG_NORMAL +
sizeof(*c2h_evt) + i);
RT_PRINT_DATA(_module_hal_init_c_, _drv_info_,
"c2h_evt_read23a(): Command Content:\n", c2h_evt->payload,
c2h_evt->plen);
ret = _SUCCESS;
clear_evt:
/*
* Clear event to notify FW we have read the command.
* If this field isn't clear, the FW won't update the
* next command message.
*/
c2h_evt_clear23a(adapter);
exit:
return ret;
}
void
rtl8723a_set_ampdu_min_space(struct rtw_adapter *padapter, u8 MinSpacingToSet)
{
u8 SecMinSpace;
if (MinSpacingToSet <= 7) {
switch (padapter->securitypriv.dot11PrivacyAlgrthm) {
case _NO_PRIVACY_:
case _AES_:
SecMinSpace = 0;
break;
case _WEP40_:
case _WEP104_:
case _TKIP_:
case _TKIP_WTMIC_:
SecMinSpace = 6;
break;
default:
SecMinSpace = 7;
break;
}
if (MinSpacingToSet < SecMinSpace)
MinSpacingToSet = SecMinSpace;
/* RT_TRACE(COMP_MLME, DBG_LOUD,
("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
padapter->MgntInfo.MinSpaceCfg)); */
MinSpacingToSet |=
rtw_read8(padapter, REG_AMPDU_MIN_SPACE) & 0xf8;
rtw_write8(padapter, REG_AMPDU_MIN_SPACE,
MinSpacingToSet);
}
}
void rtl8723a_set_ampdu_factor(struct rtw_adapter *padapter, u8 FactorToSet)
{
u8 RegToSet_Normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
u8 MaxAggNum;
u8 *pRegToSet;
u8 index = 0;
pRegToSet = RegToSet_Normal; /* 0xb972a841; */
#ifdef CONFIG_8723AU_BT_COEXIST
if ((BT_IsBtDisabled(padapter) == false) &&
(BT_1Ant(padapter) == true)) {
MaxAggNum = 0x8;
} else
#endif /* CONFIG_8723AU_BT_COEXIST */
{
MaxAggNum = 0xF;
}
if (FactorToSet <= 3) {
FactorToSet = (1 << (FactorToSet + 2));
if (FactorToSet > MaxAggNum)
FactorToSet = MaxAggNum;
for (index = 0; index < 4; index++) {
if ((pRegToSet[index] & 0xf0) > (FactorToSet << 4))
pRegToSet[index] = (pRegToSet[index] & 0x0f) |
(FactorToSet << 4);
if ((pRegToSet[index] & 0x0f) > FactorToSet)
pRegToSet[index] = (pRegToSet[index] & 0xf0) |
FactorToSet;
rtw_write8(padapter, REG_AGGLEN_LMT + index,
pRegToSet[index]);
}
/* RT_TRACE(COMP_MLME, DBG_LOUD,
("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet)); */
}
}
void rtl8723a_set_acm_ctrl(struct rtw_adapter *padapter, u8 ctrl)
{
u8 hwctrl = 0;
if (ctrl != 0) {
hwctrl |= AcmHw_HwEn;
if (ctrl & BIT(1)) /* BE */
hwctrl |= AcmHw_BeqEn;
if (ctrl & BIT(2)) /* VI */
hwctrl |= AcmHw_ViqEn;
if (ctrl & BIT(3)) /* VO */
hwctrl |= AcmHw_VoqEn;
}
DBG_8723A("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
rtw_write8(padapter, REG_ACMHWCTRL, hwctrl);
}
void rtl8723a_set_media_status(struct rtw_adapter *padapter, u8 status)
{
u8 val8;
val8 = rtw_read8(padapter, MSR) & 0x0c;
val8 |= status;
rtw_write8(padapter, MSR, val8);
}
void rtl8723a_set_media_status1(struct rtw_adapter *padapter, u8 status)
{
u8 val8;
val8 = rtw_read8(padapter, MSR) & 0x03;
val8 |= status << 2;
rtw_write8(padapter, MSR, val8);
}
void rtl8723a_set_bcn_func(struct rtw_adapter *padapter, u8 val)
{
if (val)
SetBcnCtrlReg23a(padapter, EN_BCN_FUNCTION | EN_TXBCN_RPT, 0);
else
SetBcnCtrlReg23a(padapter, 0, EN_BCN_FUNCTION | EN_TXBCN_RPT);
}
void rtl8723a_check_bssid(struct rtw_adapter *padapter, u8 val)
{
u32 val32;
val32 = rtw_read32(padapter, REG_RCR);
if (val)
val32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN;
else
val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
rtw_write32(padapter, REG_RCR, val32);
}
void rtl8723a_mlme_sitesurvey(struct rtw_adapter *padapter, u8 flag)
{
if (flag) { /* under sitesurvey */
u32 v32;
/* config RCR to receive different BSSID & not
to receive data frame */
v32 = rtw_read32(padapter, REG_RCR);
v32 &= ~(RCR_CBSSID_BCN);
rtw_write32(padapter, REG_RCR, v32);
/* reject all data frame */
rtw_write16(padapter, REG_RXFLTMAP2, 0);
/* disable update TSF */
SetBcnCtrlReg23a(padapter, DIS_TSF_UDT, 0);
} else { /* sitesurvey done */
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo;
u32 v32;
pmlmeinfo = &pmlmeext->mlmext_info;
if ((is_client_associated_to_ap23a(padapter) == true) ||
((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) ||
((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
/* enable to rx data frame */
rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
/* enable update TSF */
SetBcnCtrlReg23a(padapter, 0, DIS_TSF_UDT);
}
v32 = rtw_read32(padapter, REG_RCR);
v32 |= RCR_CBSSID_BCN;
rtw_write32(padapter, REG_RCR, v32);
}
#ifdef CONFIG_8723AU_BT_COEXIST
BT_WifiScanNotify(padapter, flag ? true : false);
#endif
}
void rtl8723a_on_rcr_am(struct rtw_adapter *padapter)
{
rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR) | RCR_AM);
DBG_8723A("%s, %d, RCR = %x \n", __FUNCTION__, __LINE__,
rtw_read32(padapter, REG_RCR));
}
void rtl8723a_off_rcr_am(struct rtw_adapter *padapter)
{
rtw_write32(padapter, REG_RCR,
rtw_read32(padapter, REG_RCR) & (~RCR_AM));
DBG_8723A("%s, %d, RCR = %x \n", __FUNCTION__, __LINE__,
rtw_read32(padapter, REG_RCR));
}
void rtl8723a_set_slot_time(struct rtw_adapter *padapter, u8 slottime)
{
u8 u1bAIFS, aSifsTime;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
rtw_write8(padapter, REG_SLOT, slottime);
if (pmlmeinfo->WMM_enable == 0) {
if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
aSifsTime = 10;
else
aSifsTime = 16;
u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
/* <Roger_EXP> Temporary removed, 2008.06.20. */
rtw_write8(padapter, REG_EDCA_VO_PARAM, u1bAIFS);
rtw_write8(padapter, REG_EDCA_VI_PARAM, u1bAIFS);
rtw_write8(padapter, REG_EDCA_BE_PARAM, u1bAIFS);
rtw_write8(padapter, REG_EDCA_BK_PARAM, u1bAIFS);
}
}
void rtl8723a_ack_preamble(struct rtw_adapter *padapter, u8 bShortPreamble)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
u8 regTmp;
/* Joseph marked out for Netgear 3500 TKIP
channel 7 issue.(Temporarily) */
regTmp = (pHalData->nCur40MhzPrimeSC) << 5;
/* regTmp = 0; */
if (bShortPreamble)
regTmp |= 0x80;
rtw_write8(padapter, REG_RRSR + 2, regTmp);
}
void rtl8723a_set_sec_cfg(struct rtw_adapter *padapter, u8 sec)
{
rtw_write8(padapter, REG_SECCFG, sec);
}
void rtl8723a_cam_empty_entry(struct rtw_adapter *padapter, u8 ucIndex)
{
u8 i;
u32 ulCommand = 0;
u32 ulContent = 0;
u32 ulEncAlgo = CAM_AES;
for (i = 0; i < CAM_CONTENT_COUNT; i++) {
/* filled id in CAM config 2 byte */
if (i == 0) {
ulContent |= (ucIndex & 0x03) |
((u16) (ulEncAlgo) << 2);
/* ulContent |= CAM_VALID; */
} else {
ulContent = 0;
}
/* polling bit, and No Write enable, and address */
ulCommand = CAM_CONTENT_COUNT * ucIndex + i;
ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
/* write content 0 is equall to mark invalid */
/* delay_ms(40); */
rtw_write32(padapter, WCAMI, ulContent);
/* RT_TRACE(COMP_SEC, DBG_LOUD,
("CAM_empty_entry23a(): WRITE A4: %lx \n", ulContent));*/
/* delay_ms(40); */
rtw_write32(padapter, RWCAM, ulCommand);
/* RT_TRACE(COMP_SEC, DBG_LOUD,
("CAM_empty_entry23a(): WRITE A0: %lx \n", ulCommand));*/
}
}
void rtl8723a_cam_invalid_all(struct rtw_adapter *padapter)
{
rtw_write32(padapter, RWCAM, BIT(31) | BIT(30));
}
void rtl8723a_cam_write(struct rtw_adapter *padapter, u32 val1, u32 val2)
{
u32 cmd;
rtw_write32(padapter, WCAMI, val1);
cmd = CAM_POLLINIG | CAM_WRITE | val2;
rtw_write32(padapter, RWCAM, cmd);
}
void rtl8723a_fifo_cleanup(struct rtw_adapter *padapter)
{
#define RW_RELEASE_EN BIT(18)
#define RXDMA_IDLE BIT(17)
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
u8 trycnt = 100;
/* pause tx */
rtw_write8(padapter, REG_TXPAUSE, 0xff);
/* keep sn */
padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ);
if (pwrpriv->bkeepfwalive != true) {
u32 v32;
/* RX DMA stop */
v32 = rtw_read32(padapter, REG_RXPKT_NUM);
v32 |= RW_RELEASE_EN;
rtw_write32(padapter, REG_RXPKT_NUM, v32);
do {
v32 = rtw_read32(padapter, REG_RXPKT_NUM) & RXDMA_IDLE;
if (!v32)
break;
} while (trycnt--);
if (trycnt == 0) {
DBG_8723A("Stop RX DMA failed......\n");
}
/* RQPN Load 0 */
rtw_write16(padapter, REG_RQPN_NPQ, 0);
rtw_write32(padapter, REG_RQPN, 0x80000000);
mdelay(10);
}
}
void rtl8723a_set_apfm_on_mac(struct rtw_adapter *padapter, u8 val)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
pHalData->bMacPwrCtrlOn = val;
DBG_8723A("%s: bMacPwrCtrlOn =%d\n", __func__, pHalData->bMacPwrCtrlOn);
}
void rtl8723a_bcn_valid(struct rtw_adapter *padapter)
{
/* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2,
write 1 to clear, Clear by sw */
rtw_write8(padapter, REG_TDECTRL + 2,
rtw_read8(padapter, REG_TDECTRL + 2) | BIT0);
}
void rtl8723a_set_tx_pause(struct rtw_adapter *padapter, u8 pause)
{
rtw_write8(padapter, REG_TXPAUSE, pause);
}
void rtl8723a_set_beacon_interval(struct rtw_adapter *padapter, u16 interval)
{
rtw_write16(padapter, REG_BCN_INTERVAL, interval);
}
void rtl8723a_set_resp_sifs(struct rtw_adapter *padapter,
u8 r2t1, u8 r2t2, u8 t2t1, u8 t2t2)
{
/* SIFS_Timer = 0x0a0a0808; */
/* RESP_SIFS for CCK */
/* SIFS_T2T_CCK (0x08) */
rtw_write8(padapter, REG_R2T_SIFS, r2t1);
/* SIFS_R2T_CCK(0x08) */
rtw_write8(padapter, REG_R2T_SIFS + 1, r2t2);
/* RESP_SIFS for OFDM */
/* SIFS_T2T_OFDM (0x0a) */
rtw_write8(padapter, REG_T2T_SIFS, t2t1);
/* SIFS_R2T_OFDM(0x0a) */
rtw_write8(padapter, REG_T2T_SIFS + 1, t2t2);
}
void rtl8723a_set_ac_param_vo(struct rtw_adapter *padapter, u32 vo)
{
rtw_write32(padapter, REG_EDCA_VO_PARAM, vo);
}
void rtl8723a_set_ac_param_vi(struct rtw_adapter *padapter, u32 vi)
{
rtw_write32(padapter, REG_EDCA_VI_PARAM, vi);
}
void rtl8723a_set_ac_param_be(struct rtw_adapter *padapter, u32 be)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
pHalData->AcParam_BE = be;
rtw_write32(padapter, REG_EDCA_BE_PARAM, be);
}
void rtl8723a_set_ac_param_bk(struct rtw_adapter *padapter, u32 bk)
{
rtw_write32(padapter, REG_EDCA_BK_PARAM, bk);
}
void rtl8723a_set_rxdma_agg_pg_th(struct rtw_adapter *padapter, u8 val)
{
rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, val);
}
void rtl8723a_set_nav_upper(struct rtw_adapter *padapter, u32 usNavUpper)
{
if (usNavUpper > HAL_8723A_NAV_UPPER_UNIT * 0xFF) {
RT_TRACE(_module_hal_init_c_, _drv_notice_,
("The setting value (0x%08X us) of NAV_UPPER "
"is larger than (%d * 0xFF)!!!\n",
usNavUpper, HAL_8723A_NAV_UPPER_UNIT));
return;
}
/* The value of ((usNavUpper + HAL_8723A_NAV_UPPER_UNIT - 1) /
HAL_8723A_NAV_UPPER_UNIT) */
/* is getting the upper integer. */
usNavUpper = (usNavUpper + HAL_8723A_NAV_UPPER_UNIT - 1) /
HAL_8723A_NAV_UPPER_UNIT;
rtw_write8(padapter, REG_NAV_UPPER, (u8) usNavUpper);
}
void rtl8723a_set_initial_gain(struct rtw_adapter *padapter, u32 rx_gain)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct dig_t *pDigTable = &pHalData->odmpriv.DM_DigTable;
if (rx_gain == 0xff) /* restore rx gain */
ODM_Write_DIG23a(&pHalData->odmpriv, pDigTable->BackupIGValue);
else {
pDigTable->BackupIGValue = pDigTable->CurIGValue;
ODM_Write_DIG23a(&pHalData->odmpriv, rx_gain);
}
}
void rtl8723a_odm_support_ability_write(struct rtw_adapter *padapter, u32 val)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
pHalData->odmpriv.SupportAbility = val;
}
void rtl8723a_odm_support_ability_backup(struct rtw_adapter *padapter, u8 val)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
if (val) /* save dm flag */
pHalData->odmpriv.BK_SupportAbility =
pHalData->odmpriv.SupportAbility;
else /* restore dm flag */
pHalData->odmpriv.SupportAbility =
pHalData->odmpriv.BK_SupportAbility;
}
void rtl8723a_odm_support_ability_set(struct rtw_adapter *padapter, u32 val)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
if (val == DYNAMIC_ALL_FUNC_ENABLE) {
pHalData->dmpriv.DMFlag = pHalData->dmpriv.InitDMFlag;
pHalData->odmpriv.SupportAbility = pHalData->dmpriv.InitODMFlag;
} else {
pHalData->odmpriv.SupportAbility |= val;
}
}
void rtl8723a_odm_support_ability_clr(struct rtw_adapter *padapter, u32 val)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
pHalData->odmpriv.SupportAbility &= val;
}
void rtl8723a_set_rpwm(struct rtw_adapter *padapter, u8 val)
{
rtw_write8(padapter, REG_USB_HRPWM, val);
}

420
drivers/staging/rtl8723au/hal/hal_intf.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _HAL_INTF_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <hal_intf.h>
#include <usb_hal.h>
void rtw_hal_chip_configure23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.intf_chip_configure)
padapter->HalFunc.intf_chip_configure(padapter);
}
void rtw_hal_read_chip_info23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.read_adapter_info)
padapter->HalFunc.read_adapter_info(padapter);
}
void rtw_hal_read_chip_version23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.read_chip_version)
padapter->HalFunc.read_chip_version(padapter);
}
void rtw_hal_def_value_init23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.init_default_value)
padapter->HalFunc.init_default_value(padapter);
}
void rtw_hal_free_data23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.free_hal_data)
padapter->HalFunc.free_hal_data(padapter);
}
void rtw_hal_dm_init23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.dm_init)
padapter->HalFunc.dm_init(padapter);
}
void rtw_hal_dm_deinit23a(struct rtw_adapter *padapter)
{
/* cancel dm timer */
if (padapter->HalFunc.dm_deinit)
padapter->HalFunc.dm_deinit(padapter);
}
void rtw_hal_sw_led_init23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.InitSwLeds)
padapter->HalFunc.InitSwLeds(padapter);
}
void rtw_hal_sw_led_deinit23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.DeInitSwLeds)
padapter->HalFunc.DeInitSwLeds(padapter);
}
u32 rtw_hal_power_on23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.hal_power_on)
return padapter->HalFunc.hal_power_on(padapter);
return _FAIL;
}
uint rtw_hal_init23a(struct rtw_adapter *padapter)
{
uint status = _SUCCESS;
padapter->hw_init_completed = false;
status = padapter->HalFunc.hal_init(padapter);
if (status == _SUCCESS) {
padapter->hw_init_completed = true;
if (padapter->registrypriv.notch_filter == 1)
rtw_hal_notch_filter23a(padapter, 1);
rtw_hal_reset_security_engine23a(padapter);
} else {
padapter->hw_init_completed = false;
DBG_8723A("rtw_hal_init23a: hal__init fail\n");
}
RT_TRACE(_module_hal_init_c_, _drv_err_, ("-rtl871x_hal_init:status = 0x%x\n", status));
return status;
}
uint rtw_hal_deinit23a(struct rtw_adapter *padapter)
{
uint status = _SUCCESS;
status = padapter->HalFunc.hal_deinit(padapter);
if (status == _SUCCESS)
padapter->hw_init_completed = false;
else
DBG_8723A("\n rtw_hal_deinit23a: hal_init fail\n");
return status;
}
void rtw_hal_set_hwreg23a(struct rtw_adapter *padapter, u8 variable, u8 *val)
{
if (padapter->HalFunc.SetHwRegHandler)
padapter->HalFunc.SetHwRegHandler(padapter, variable, val);
}
void rtw23a_hal_get_hwreg(struct rtw_adapter *padapter, u8 variable, u8 *val)
{
if (padapter->HalFunc.GetHwRegHandler)
padapter->HalFunc.GetHwRegHandler(padapter, variable, val);
}
u8 rtw_hal_set_def_var23a(struct rtw_adapter *padapter, enum hal_def_variable eVariable, void *pValue)
{
if (padapter->HalFunc.SetHalDefVarHandler)
return padapter->HalFunc.SetHalDefVarHandler(padapter, eVariable, pValue);
return _FAIL;
}
u8 rtw_hal_get_def_var23a(struct rtw_adapter *padapter, enum hal_def_variable eVariable, void *pValue)
{
if (padapter->HalFunc.GetHalDefVarHandler)
return padapter->HalFunc.GetHalDefVarHandler(padapter, eVariable, pValue);
return _FAIL;
}
void rtw_hal_set_odm_var23a(struct rtw_adapter *padapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet)
{
if (padapter->HalFunc.SetHalODMVarHandler)
padapter->HalFunc.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
}
void rtw_hal_get_odm_var23a(struct rtw_adapter *padapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet)
{
if (padapter->HalFunc.GetHalODMVarHandler)
padapter->HalFunc.GetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
}
void rtw_hal_enable_interrupt23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.enable_interrupt)
padapter->HalFunc.enable_interrupt(padapter);
else
DBG_8723A("%s: HalFunc.enable_interrupt is NULL!\n", __FUNCTION__);
}
void rtw_hal_disable_interrupt23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.disable_interrupt)
padapter->HalFunc.disable_interrupt(padapter);
else
DBG_8723A("%s: HalFunc.disable_interrupt is NULL!\n", __FUNCTION__);
}
u32 rtw_hal_inirp_init23a(struct rtw_adapter *padapter)
{
u32 rst = _FAIL;
if (padapter->HalFunc.inirp_init)
rst = padapter->HalFunc.inirp_init(padapter);
else
DBG_8723A(" %s HalFunc.inirp_init is NULL!!!\n", __FUNCTION__);
return rst;
}
u32 rtw_hal_inirp_deinit23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.inirp_deinit)
return padapter->HalFunc.inirp_deinit(padapter);
return _FAIL;
}
u8 rtw_hal_intf_ps_func23a(struct rtw_adapter *padapter, enum hal_intf_ps_func efunc_id, u8 *val)
{
if (padapter->HalFunc.interface_ps_func)
return padapter->HalFunc.interface_ps_func(padapter, efunc_id, val);
return _FAIL;
}
s32 rtw_hal_xmit23aframe_enqueue(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe)
{
if (padapter->HalFunc.hal_xmitframe_enqueue)
return padapter->HalFunc.hal_xmitframe_enqueue(padapter, pxmitframe);
return false;
}
s32 rtw_hal_xmit23a(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe)
{
if (padapter->HalFunc.hal_xmit)
return padapter->HalFunc.hal_xmit(padapter, pxmitframe);
return false;
}
s32 rtw_hal_mgnt_xmit23a(struct rtw_adapter *padapter, struct xmit_frame *pmgntframe)
{
s32 ret = _FAIL;
if (padapter->HalFunc.mgnt_xmit)
ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe);
return ret;
}
s32 rtw_hal_init23a_xmit_priv(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.init_xmit_priv != NULL)
return padapter->HalFunc.init_xmit_priv(padapter);
return _FAIL;
}
void rtw_hal_free_xmit_priv23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.free_xmit_priv != NULL)
padapter->HalFunc.free_xmit_priv(padapter);
}
s32 rtw_hal_init23a_recv_priv(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.init_recv_priv)
return padapter->HalFunc.init_recv_priv(padapter);
return _FAIL;
}
void rtw_hal_free_recv_priv23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.free_recv_priv)
padapter->HalFunc.free_recv_priv(padapter);
}
void rtw_hal_update_ra_mask23a(struct sta_info *psta, u8 rssi_level)
{
struct rtw_adapter *padapter;
struct mlme_priv *pmlmepriv;
if (!psta)
return;
padapter = psta->padapter;
pmlmepriv = &padapter->mlmepriv;
if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
#ifdef CONFIG_8723AU_AP_MODE
add_RATid23a(padapter, psta, rssi_level);
#endif
} else {
if (padapter->HalFunc.UpdateRAMaskHandler)
padapter->HalFunc.UpdateRAMaskHandler(padapter, psta->mac_id, rssi_level);
}
}
void rtw_hal_add_ra_tid23a(struct rtw_adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level)
{
if (padapter->HalFunc.Add_RateATid)
padapter->HalFunc.Add_RateATid(padapter, bitmap, arg, rssi_level);
}
/* Start specifical interface thread */
void rtw_hal_start_thread23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.run_thread)
padapter->HalFunc.run_thread(padapter);
}
/* Start specifical interface thread */
void rtw_hal_stop_thread23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.cancel_thread)
padapter->HalFunc.cancel_thread(padapter);
}
u32 rtw_hal_read_bbreg23a(struct rtw_adapter *padapter, u32 RegAddr, u32 BitMask)
{
u32 data = 0;
if (padapter->HalFunc.read_bbreg)
data = padapter->HalFunc.read_bbreg(padapter, RegAddr, BitMask);
return data;
}
void rtw_hal_write_bbreg23a(struct rtw_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
{
if (padapter->HalFunc.write_bbreg)
padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data);
}
u32 rtw_hal_read_rfreg23a(struct rtw_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask)
{
u32 data = 0;
if (padapter->HalFunc.read_rfreg)
data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
return data;
}
void rtw_hal_write_rfreg23a(struct rtw_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
{
if (padapter->HalFunc.write_rfreg)
padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
}
s32 rtw_hal_interrupt_handler23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.interrupt_handler)
return padapter->HalFunc.interrupt_handler(padapter);
return _FAIL;
}
void rtw_hal_set_bwmode23a(struct rtw_adapter *padapter,
enum ht_channel_width Bandwidth, u8 offset)
{
if (padapter->HalFunc.set_bwmode_handler)
padapter->HalFunc.set_bwmode_handler(padapter, Bandwidth,
offset);
}
void rtw_hal_set_chan23a(struct rtw_adapter *padapter, u8 channel)
{
if (padapter->HalFunc.set_channel_handler)
padapter->HalFunc.set_channel_handler(padapter, channel);
}
void rtw_hal_dm_watchdog23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.hal_dm_watchdog)
padapter->HalFunc.hal_dm_watchdog(padapter);
}
void rtw_hal_bcn_related_reg_setting23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.SetBeaconRelatedRegistersHandler)
padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter);
}
void rtw_hal_sreset_init23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.sreset_init_value23a)
padapter->HalFunc.sreset_init_value23a(padapter);
}
void rtw_hal_sreset_reset23a(struct rtw_adapter *padapter)
{
padapter = GET_PRIMARY_ADAPTER(padapter);
if (padapter->HalFunc.silentreset)
padapter->HalFunc.silentreset(padapter);
}
void rtw_hal_sreset_reset23a_value23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.sreset_reset_value23a)
padapter->HalFunc.sreset_reset_value23a(padapter);
}
void rtw_hal_sreset_xmit_status_check23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.sreset_xmit_status_check)
padapter->HalFunc.sreset_xmit_status_check(padapter);
}
void rtw_hal_sreset_linked_status_check23a(struct rtw_adapter *padapter)
{
if (padapter->HalFunc.sreset_linked_status_check)
padapter->HalFunc.sreset_linked_status_check(padapter);
}
u8 rtw_hal_sreset_get_wifi_status23a(struct rtw_adapter *padapter)
{
u8 status = 0;
if (padapter->HalFunc.sreset_get_wifi_status23a)
status = padapter->HalFunc.sreset_get_wifi_status23a(padapter);
return status;
}
bool rtw_hal_sreset_inprogress(struct rtw_adapter *padapter)
{
bool inprogress = false;
padapter = GET_PRIMARY_ADAPTER(padapter);
if (padapter->HalFunc.sreset_inprogress)
inprogress = padapter->HalFunc.sreset_inprogress(padapter);
return inprogress;
}
void rtw_hal_notch_filter23a(struct rtw_adapter *adapter, bool enable)
{
if (adapter->HalFunc.hal_notch_filter)
adapter->HalFunc.hal_notch_filter(adapter, enable);
}
void rtw_hal_reset_security_engine23a(struct rtw_adapter *adapter)
{
if (adapter->HalFunc.hal_reset_security_engine)
adapter->HalFunc.hal_reset_security_engine(adapter);
}
s32 rtw_hal_c2h_handler23a(struct rtw_adapter *adapter, struct c2h_evt_hdr *c2h_evt)
{
s32 ret = _FAIL;
if (adapter->HalFunc.c2h_handler)
ret = adapter->HalFunc.c2h_handler(adapter, c2h_evt);
return ret;
}
c2h_id_filter rtw_hal_c2h_id_filter_ccx23a(struct rtw_adapter *adapter)
{
return adapter->HalFunc.c2h_id_filter_ccx;
}

2090
drivers/staging/rtl8723au/hal/odm.c Normal file
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File diff suppressed because it is too large Load Diff

481
drivers/staging/rtl8723au/hal/odm_HWConfig.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/* */
/* include files */
/* */
#include "odm_precomp.h"
#define READ_AND_CONFIG READ_AND_CONFIG_MP
#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig##txt##ic(pDM_Odm))
#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC##txt##ic(pDM_Odm))
static u8 odm_QueryRxPwrPercentage(s8 AntPower)
{
if ((AntPower <= -100) || (AntPower >= 20))
return 0;
else if (AntPower >= 0)
return 100;
else
return 100 + AntPower;
}
static s32 odm_SignalScaleMapping_92CSeries(struct dm_odm_t *pDM_Odm, s32 CurrSig)
{
s32 RetSig = 0;
if ((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) {
if (CurrSig >= 51 && CurrSig <= 100)
RetSig = 100;
else if (CurrSig >= 41 && CurrSig <= 50)
RetSig = 80 + ((CurrSig - 40)*2);
else if (CurrSig >= 31 && CurrSig <= 40)
RetSig = 66 + (CurrSig - 30);
else if (CurrSig >= 21 && CurrSig <= 30)
RetSig = 54 + (CurrSig - 20);
else if (CurrSig >= 10 && CurrSig <= 20)
RetSig = 42 + (((CurrSig - 10) * 2) / 3);
else if (CurrSig >= 5 && CurrSig <= 9)
RetSig = 22 + (((CurrSig - 5) * 3) / 2);
else if (CurrSig >= 1 && CurrSig <= 4)
RetSig = 6 + (((CurrSig - 1) * 3) / 2);
else
RetSig = CurrSig;
}
return RetSig;
}
static s32 odm_SignalScaleMapping(struct dm_odm_t *pDM_Odm, s32 CurrSig)
{
return odm_SignalScaleMapping_92CSeries(pDM_Odm, CurrSig);
}
static u8
odm_EVMdbToPercentage(
s8 Value
)
{
/* */
/* -33dB~0dB to 0%~99% */
/* */
s8 ret_val;
ret_val = Value;
if (ret_val >= 0)
ret_val = 0;
if (ret_val <= -33)
ret_val = -33;
ret_val = 0 - ret_val;
ret_val *= 3;
if (ret_val == 99)
ret_val = 100;
return ret_val;
}
static void odm_RxPhyStatus92CSeries_Parsing(struct dm_odm_t *pDM_Odm,
struct odm_phy_info *pPhyInfo,
u8 *pPhyStatus,
struct odm_packet_info *pPktinfo)
{
struct phy_status_rpt *pPhyStaRpt = (struct phy_status_rpt *)pPhyStatus;
u8 i, Max_spatial_stream;
s8 rx_pwr[4], rx_pwr_all = 0;
u8 EVM, PWDB_ALL = 0, PWDB_ALL_BT;
u8 RSSI, total_rssi = 0;
u8 isCCKrate = 0;
u8 rf_rx_num = 0;
u8 cck_highpwr = 0;
isCCKrate = (pPktinfo->Rate <= DESC92C_RATE11M) ? true : false;
pPhyInfo->RxMIMOSignalQuality[RF_PATH_A] = -1;
pPhyInfo->RxMIMOSignalQuality[RF_PATH_B] = -1;
if (isCCKrate) {
u8 report;
u8 cck_agc_rpt;
pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++;
/* (1)Hardware does not provide RSSI for CCK */
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
cck_highpwr = pDM_Odm->bCckHighPower;
cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ;
/* The RSSI formula should be modified according to the gain table */
if (!cck_highpwr) {
report = (cck_agc_rpt & 0xc0)>>6;
switch (report) {
/* Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion */
/* Note: different RF with the different RNA gain. */
case 0x3:
rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
break;
case 0x2:
rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
break;
case 0x1:
rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
break;
case 0x0:
rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
break;
}
} else {
report = (cck_agc_rpt & 0x60)>>5;
switch (report) {
case 0x3:
rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f)<<1) ;
break;
case 0x2:
rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f)<<1);
break;
case 0x1:
rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f)<<1) ;
break;
case 0x0:
rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f)<<1) ;
break;
}
}
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
/* Modification for ext-LNA board */
if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
if ((cck_agc_rpt>>7) == 0) {
PWDB_ALL = (PWDB_ALL > 94) ? 100 : (PWDB_ALL+6);
} else {
if (PWDB_ALL > 38)
PWDB_ALL -= 16;
else
PWDB_ALL = (PWDB_ALL <= 16) ? (PWDB_ALL>>2) : (PWDB_ALL-12);
}
/* CCK modification */
if (PWDB_ALL > 25 && PWDB_ALL <= 60)
PWDB_ALL += 6;
} else { /* Modification for int-LNA board */
if (PWDB_ALL > 99)
PWDB_ALL -= 8;
else if (PWDB_ALL > 50 && PWDB_ALL <= 68)
PWDB_ALL += 4;
}
pPhyInfo->RxPWDBAll = PWDB_ALL;
pPhyInfo->BTRxRSSIPercentage = PWDB_ALL;
pPhyInfo->RecvSignalPower = rx_pwr_all;
/* (3) Get Signal Quality (EVM) */
if (pPktinfo->bPacketMatchBSSID) {
u8 SQ, SQ_rpt;
SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all;
if (SQ_rpt > 64)
SQ = 0;
else if (SQ_rpt < 20)
SQ = 100;
else
SQ = ((64-SQ_rpt) * 100) / 44;
pPhyInfo->SignalQuality = SQ;
pPhyInfo->RxMIMOSignalQuality[RF_PATH_A] = SQ;
pPhyInfo->RxMIMOSignalQuality[RF_PATH_B] = -1;
}
} else { /* is OFDM rate */
pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++;
/* (1)Get RSSI for HT rate */
for (i = RF_PATH_A; i < RF_PATH_MAX; i++) {
/* 2008/01/30 MH we will judge RF RX path now. */
if (pDM_Odm->RFPathRxEnable & BIT(i))
rf_rx_num++;
rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain & 0x3F)*2) - 110;
pPhyInfo->RxPwr[i] = rx_pwr[i];
/* Translate DBM to percentage. */
RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]);
total_rssi += RSSI;
/* Modification for ext-LNA board */
if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
if ((pPhyStaRpt->path_agc[i].trsw) == 1)
RSSI = (RSSI > 94) ? 100 : (RSSI+6);
else
RSSI = (RSSI <= 16) ? (RSSI>>3) : (RSSI-16);
if ((RSSI <= 34) && (RSSI >= 4))
RSSI -= 4;
}
pPhyInfo->RxMIMOSignalStrength[i] = (u8) RSSI;
/* Get Rx snr value in DB */
pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s32)(pPhyStaRpt->path_rxsnr[i]/2);
}
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f)-110;
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
PWDB_ALL_BT = PWDB_ALL;
pPhyInfo->RxPWDBAll = PWDB_ALL;
pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT;
pPhyInfo->RxPower = rx_pwr_all;
pPhyInfo->RecvSignalPower = rx_pwr_all;
/* (3)EVM of HT rate */
if (pPktinfo->Rate >= DESC92C_RATEMCS8 && pPktinfo->Rate <= DESC92C_RATEMCS15)
Max_spatial_stream = 2; /* both spatial stream make sense */
else
Max_spatial_stream = 1; /* only spatial stream 1 makes sense */
for (i = 0; i < Max_spatial_stream; i++) {
/* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */
/* fill most significant bit to "zero" when doing shifting operation which may change a negative */
/* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */
EVM = odm_EVMdbToPercentage((pPhyStaRpt->stream_rxevm[i])); /* dbm */
if (pPktinfo->bPacketMatchBSSID) {
if (i == RF_PATH_A) {
/* Fill value in RFD, Get the first spatial stream only */
pPhyInfo->SignalQuality = (u8)(EVM & 0xff);
}
pPhyInfo->RxMIMOSignalQuality[i] = (u8)(EVM & 0xff);
}
}
}
/* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */
/* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */
if (isCCKrate) {
pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/* PWDB_ALL; */
} else {
if (rf_rx_num != 0)
pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, total_rssi /= rf_rx_num));
}
}
void odm_Init_RSSIForDM23a(struct dm_odm_t *pDM_Odm)
{
}
static void odm_Process_RSSIForDM(struct dm_odm_t *pDM_Odm,
struct odm_phy_info *pPhyInfo,
struct odm_packet_info *pPktinfo)
{
s32 UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK;
s32 UndecoratedSmoothedOFDM, RSSI_Ave;
u8 isCCKrate = 0;
u8 RSSI_max, RSSI_min, i;
u32 OFDM_pkt = 0;
u32 Weighting = 0;
struct sta_info *pEntry;
if (pPktinfo->StationID == 0xFF)
return;
pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID];
if (!IS_STA_VALID(pEntry))
return;
if ((!pPktinfo->bPacketMatchBSSID))
return;
isCCKrate = (pPktinfo->Rate <= DESC92C_RATE11M) ? true : false;
/* Smart Antenna Debug Message------------------*/
UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK;
UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM;
UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB;
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) {
if (!isCCKrate) { /* ofdm rate */
if (pPhyInfo->RxMIMOSignalStrength[RF_PATH_B] == 0) {
RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[RF_PATH_A];
} else {
if (pPhyInfo->RxMIMOSignalStrength[RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[RF_PATH_B]) {
RSSI_max = pPhyInfo->RxMIMOSignalStrength[RF_PATH_A];
RSSI_min = pPhyInfo->RxMIMOSignalStrength[RF_PATH_B];
} else {
RSSI_max = pPhyInfo->RxMIMOSignalStrength[RF_PATH_B];
RSSI_min = pPhyInfo->RxMIMOSignalStrength[RF_PATH_A];
}
if ((RSSI_max - RSSI_min) < 3)
RSSI_Ave = RSSI_max;
else if ((RSSI_max - RSSI_min) < 6)
RSSI_Ave = RSSI_max - 1;
else if ((RSSI_max - RSSI_min) < 10)
RSSI_Ave = RSSI_max - 2;
else
RSSI_Ave = RSSI_max - 3;
}
/* 1 Process OFDM RSSI */
if (UndecoratedSmoothedOFDM <= 0) {
/* initialize */
UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll;
} else {
if (pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedOFDM) {
UndecoratedSmoothedOFDM =
(((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
(RSSI_Ave)) / (Rx_Smooth_Factor);
UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1;
} else {
UndecoratedSmoothedOFDM =
(((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
(RSSI_Ave)) / (Rx_Smooth_Factor);
}
}
pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0;
} else {
RSSI_Ave = pPhyInfo->RxPWDBAll;
/* 1 Process CCK RSSI */
if (UndecoratedSmoothedCCK <= 0) {
/* initialize */
UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll;
} else {
if (pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedCCK) {
UndecoratedSmoothedCCK =
(((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
(pPhyInfo->RxPWDBAll)) / (Rx_Smooth_Factor);
UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1;
} else {
UndecoratedSmoothedCCK =
(((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
(pPhyInfo->RxPWDBAll)) / (Rx_Smooth_Factor);
}
}
pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1;
}
/* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */
if (pEntry->rssi_stat.ValidBit >= 64)
pEntry->rssi_stat.ValidBit = 64;
else
pEntry->rssi_stat.ValidBit++;
for (i = 0; i < pEntry->rssi_stat.ValidBit; i++)
OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
if (pEntry->rssi_stat.ValidBit == 64) {
Weighting = ((OFDM_pkt<<4) > 64)?64:(OFDM_pkt<<4);
UndecoratedSmoothedPWDB = (Weighting*UndecoratedSmoothedOFDM+(64-Weighting)*UndecoratedSmoothedCCK)>>6;
} else {
if (pEntry->rssi_stat.ValidBit != 0)
UndecoratedSmoothedPWDB = (OFDM_pkt*UndecoratedSmoothedOFDM+(pEntry->rssi_stat.ValidBit-OFDM_pkt)*UndecoratedSmoothedCCK)/pEntry->rssi_stat.ValidBit;
else
UndecoratedSmoothedPWDB = 0;
}
pEntry->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK;
pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM;
pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
}
}
/* Endianness before calling this API */
static void ODM_PhyStatusQuery23a_92CSeries(struct dm_odm_t *pDM_Odm,
struct odm_phy_info *pPhyInfo,
u8 *pPhyStatus,
struct odm_packet_info *pPktinfo)
{
odm_RxPhyStatus92CSeries_Parsing(pDM_Odm, pPhyInfo,
pPhyStatus, pPktinfo);
if (pDM_Odm->RSSI_test) {
/* Select the packets to do RSSI checking for antenna switching. */
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
ODM_SwAntDivChkPerPktRssi(pDM_Odm, pPktinfo->StationID, pPhyInfo);
} else {
odm_Process_RSSIForDM(pDM_Odm, pPhyInfo, pPktinfo);
}
}
void ODM_PhyStatusQuery23a(struct dm_odm_t *pDM_Odm, struct odm_phy_info *pPhyInfo,
u8 *pPhyStatus, struct odm_packet_info *pPktinfo)
{
ODM_PhyStatusQuery23a_92CSeries(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo);
}
/* For future use. */
void ODM_MacStatusQuery23a(struct dm_odm_t *pDM_Odm, u8 *pMacStatus, u8 MacID,
bool bPacketMatchBSSID, bool bPacketToSelf,
bool bPacketBeacon)
{
/* 2011/10/19 Driver team will handle in the future. */
}
enum hal_status
ODM_ConfigRFWithHeaderFile23a(
struct dm_odm_t *pDM_Odm,
enum RF_RADIO_PATH Content,
enum RF_RADIO_PATH eRFPath
)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("===>ODM_ConfigRFWithHeaderFile23a\n"));
if (pDM_Odm->SupportICType == ODM_RTL8723A) {
if (eRFPath == RF_PATH_A)
READ_AND_CONFIG_MP(8723A, _RadioA_1T_);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
(" ===> ODM_ConfigRFWithHeaderFile23a() Radio_A:Rtl8723RadioA_1TArray\n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
(" ===> ODM_ConfigRFWithHeaderFile23a() Radio_B:Rtl8723RadioB_1TArray\n"));
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("ODM_ConfigRFWithHeaderFile23a: Radio No %x\n", eRFPath));
return HAL_STATUS_SUCCESS;
}
enum hal_status
ODM_ConfigBBWithHeaderFile23a(
struct dm_odm_t *pDM_Odm,
enum odm_bb_config_type ConfigType
)
{
if (pDM_Odm->SupportICType == ODM_RTL8723A) {
if (ConfigType == CONFIG_BB_PHY_REG)
READ_AND_CONFIG_MP(8723A, _PHY_REG_1T_);
else if (ConfigType == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8723A, _AGC_TAB_1T_);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
(" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8723AGCTAB_1TArray\n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
(" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8723PHY_REG_1TArray\n"));
}
return HAL_STATUS_SUCCESS;
}
enum hal_status
ODM_ConfigMACWithHeaderFile23a(
struct dm_odm_t *pDM_Odm
)
{
u8 result = HAL_STATUS_SUCCESS;
if (pDM_Odm->SupportICType == ODM_RTL8723A)
READ_AND_CONFIG_MP(8723A, _MAC_REG_);
return result;
}

162
drivers/staging/rtl8723au/hal/odm_RegConfig8723A.c Normal file
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@ -0,0 +1,162 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "odm_precomp.h"
void
odm_ConfigRFReg_8723A(
struct dm_odm_t *pDM_Odm,
u32 Addr,
u32 Data,
enum RF_RADIO_PATH RF_PATH,
u32 RegAddr
)
{
if (Addr == 0xfe) {
msleep(50);
} else if (Addr == 0xfd) {
mdelay(5);
} else if (Addr == 0xfc) {
mdelay(1);
} else if (Addr == 0xfb) {
udelay(50);
} else if (Addr == 0xfa) {
udelay(5);
} else if (Addr == 0xf9) {
udelay(1);
} else {
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
/* Add 1us delay between BB/RF register setting. */
udelay(1);
}
}
void odm_ConfigRF_RadioA_8723A(struct dm_odm_t *pDM_Odm,
u32 Addr,
u32 Data
)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskforPhySet = (u32)(content&0xE000);
odm_ConfigRFReg_8723A(pDM_Odm, Addr, Data, RF_PATH_A,
Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("===> ODM_ConfigRFWithHeaderFile23a: [RadioA] %08X %08X\n",
Addr, Data));
}
void odm_ConfigRF_RadioB_8723A(struct dm_odm_t *pDM_Odm,
u32 Addr,
u32 Data
)
{
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskforPhySet = (u32)(content&0xE000);
odm_ConfigRFReg_8723A(pDM_Odm, Addr, Data, RF_PATH_B,
Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("===> ODM_ConfigRFWithHeaderFile23a: [RadioB] %08X %08X\n",
Addr, Data));
}
void odm_ConfigMAC_8723A(struct dm_odm_t *pDM_Odm,
u32 Addr,
u8 Data
)
{
ODM_Write1Byte(pDM_Odm, Addr, Data);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("===> ODM_ConfigMACWithHeaderFile23a: [MAC_REG] %08X %08X\n",
Addr, Data));
}
void
odm_ConfigBB_AGC_8723A(
struct dm_odm_t *pDM_Odm,
u32 Addr,
u32 Bitmask,
u32 Data
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
/* Add 1us delay between BB/RF register setting. */
udelay(1);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("===> ODM_ConfigBBWithHeaderFile23a: [AGC_TAB] %08X %08X\n",
Addr, Data));
}
void
odm_ConfigBB_PHY_REG_PG_8723A(
struct dm_odm_t *pDM_Odm,
u32 Addr,
u32 Bitmask,
u32 Data
)
{
if (Addr == 0xfe)
msleep(50);
else if (Addr == 0xfd)
mdelay(5);
else if (Addr == 0xfc)
mdelay(1);
else if (Addr == 0xfb)
udelay(50);
else if (Addr == 0xfa)
udelay(5);
else if (Addr == 0xf9)
udelay(1);
/* TODO: ODM_StorePwrIndexDiffRateOffset(...) */
/* storePwrIndexDiffRateOffset(Adapter, Addr, Bitmask, Data); */
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("===> ODM_ConfigBBWithHeaderFile23a: [PHY_REG] %08X %08X %08X\n",
Addr, Bitmask, Data));
}
void
odm_ConfigBB_PHY_8723A(
struct dm_odm_t *pDM_Odm,
u32 Addr,
u32 Bitmask,
u32 Data
)
{
if (Addr == 0xfe)
msleep(50);
else if (Addr == 0xfd)
mdelay(5);
else if (Addr == 0xfc)
mdelay(1);
else if (Addr == 0xfb)
udelay(50);
else if (Addr == 0xfa)
udelay(5);
else if (Addr == 0xf9)
udelay(1);
else if (Addr == 0xa24)
pDM_Odm->RFCalibrateInfo.RegA24 = Data;
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
/* Add 1us delay between BB/RF register setting. */
udelay(1);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("===> ODM_ConfigBBWithHeaderFile23a: [PHY_REG] %08X %08X\n",
Addr, Data));
}

24
drivers/staging/rtl8723au/hal/odm_debug.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "odm_precomp.h"
void ODM_InitDebugSetting23a(struct dm_odm_t *pDM_Odm)
{
pDM_Odm->DebugLevel = ODM_DBG_TRACE;
pDM_Odm->DebugComponents = 0;
}
u32 GlobalDebugLevel23A;

236
drivers/staging/rtl8723au/hal/odm_interface.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/* */
/* include files */
/* */
#include "odm_precomp.h"
/* */
/* ODM IO Relative API. */
/* */
u8 ODM_Read1Byte(struct dm_odm_t *pDM_Odm,
u32 RegAddr
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
return rtw_read8(Adapter, RegAddr);
}
u16 ODM_Read2Byte(struct dm_odm_t *pDM_Odm,
u32 RegAddr
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
return rtw_read16(Adapter, RegAddr);
}
u32 ODM_Read4Byte(struct dm_odm_t *pDM_Odm,
u32 RegAddr
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
return rtw_read32(Adapter, RegAddr);
}
void ODM_Write1Byte(
struct dm_odm_t *pDM_Odm,
u32 RegAddr,
u8 Data
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
rtw_write8(Adapter, RegAddr, Data);
}
void ODM_Write2Byte(
struct dm_odm_t *pDM_Odm,
u32 RegAddr,
u16 Data
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
rtw_write16(Adapter, RegAddr, Data);
}
void ODM_Write4Byte(
struct dm_odm_t *pDM_Odm,
u32 RegAddr,
u32 Data
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
rtw_write32(Adapter, RegAddr, Data);
}
void ODM_SetMACReg(
struct dm_odm_t *pDM_Odm,
u32 RegAddr,
u32 BitMask,
u32 Data
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
}
u32 ODM_GetMACReg(
struct dm_odm_t *pDM_Odm,
u32 RegAddr,
u32 BitMask
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
}
void ODM_SetBBReg(
struct dm_odm_t *pDM_Odm,
u32 RegAddr,
u32 BitMask,
u32 Data
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
}
u32 ODM_GetBBReg(
struct dm_odm_t *pDM_Odm,
u32 RegAddr,
u32 BitMask
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
}
void ODM_SetRFReg(
struct dm_odm_t *pDM_Odm,
enum RF_RADIO_PATH eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data);
}
u32 ODM_GetRFReg(
struct dm_odm_t *pDM_Odm,
enum RF_RADIO_PATH eRFPath,
u32 RegAddr,
u32 BitMask
)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask);
}
/* */
/* ODM Memory relative API. */
/* */
void ODM_AllocateMemory(
struct dm_odm_t *pDM_Odm,
void **pPtr,
u32 length
)
{
*pPtr = rtw_zvmalloc(length);
}
/* length could be ignored, used to detect memory leakage. */
void ODM_FreeMemory(
struct dm_odm_t *pDM_Odm,
void *pPtr,
u32 length
)
{
rtw_vmfree(pPtr, length);
}
/* */
/* ODM MISC relative API. */
/* */
void
ODM_AcquireSpinLock(
struct dm_odm_t *pDM_Odm,
enum rt_spinlock_type type
)
{
}
void ODM_ReleaseSpinLock(
struct dm_odm_t *pDM_Odm,
enum rt_spinlock_type type
)
{
}
/* */
/* Work item relative API. FOr MP driver only~! */
/* */
void ODM_InitializeWorkItem(
struct dm_odm_t *pDM_Odm,
void *pRtWorkItem,
RT_WORKITEM_CALL_BACK RtWorkItemCallback,
void *pContext,
const char *szID
)
{
}
/* */
/* ODM Timer relative API. */
/* */
void ODM_SetTimer(struct dm_odm_t *pDM_Odm, struct timer_list *pTimer, u32 msDelay)
{
mod_timer(pTimer, jiffies + msecs_to_jiffies(msDelay)); /* ms */
}
void ODM_ReleaseTimer(struct dm_odm_t *pDM_Odm, struct timer_list *pTimer)
{
}
/* */
/* ODM FW relative API. */
/* */
u32 ODM_FillH2CCmd(
u8 *pH2CBuffer,
u32 H2CBufferLen,
u32 CmdNum,
u32 *pElementID,
u32 *pCmdLen,
u8 **pCmbBuffer,
u8 *CmdStartSeq
)
{
return true;
}

11304
drivers/staging/rtl8723au/hal/rtl8723a_bt-coexist.c Normal file
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845
drivers/staging/rtl8723au/hal/rtl8723a_cmd.c Normal file
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@ -0,0 +1,845 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _RTL8723A_CMD_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <recv_osdep.h>
#include <cmd_osdep.h>
#include <mlme_osdep.h>
#include <rtw_ioctl_set.h>
#include <rtl8723a_hal.h>
#define RTL92C_MAX_H2C_BOX_NUMS 4
#define RTL92C_MAX_CMD_LEN 5
#define MESSAGE_BOX_SIZE 4
#define EX_MESSAGE_BOX_SIZE 2
static u8 _is_fw_read_cmd_down(struct rtw_adapter *padapter, u8 msgbox_num)
{
u8 read_down = false;
int retry_cnts = 100;
u8 valid;
do {
valid = rtw_read8(padapter, REG_HMETFR) & BIT(msgbox_num);
if (0 == valid)
read_down = true;
} while ((!read_down) && (retry_cnts--));
return read_down;
}
/*****************************************
* H2C Msg format :
*| 31 - 8 |7 | 6 - 0 |
*| h2c_msg |Ext_bit |CMD_ID |
*
******************************************/
s32 FillH2CCmd(struct rtw_adapter *padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
{
u8 bcmd_down = false;
s32 retry_cnts = 100;
u8 h2c_box_num;
u32 msgbox_addr;
u32 msgbox_ex_addr;
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
u32 h2c_cmd = 0;
u16 h2c_cmd_ex = 0;
s32 ret = _FAIL;
padapter = GET_PRIMARY_ADAPTER(padapter);
pHalData = GET_HAL_DATA(padapter);
mutex_lock(&adapter_to_dvobj(padapter)->h2c_fwcmd_mutex);
if (!pCmdBuffer)
goto exit;
if (CmdLen > RTL92C_MAX_CMD_LEN)
goto exit;
if (padapter->bSurpriseRemoved == true)
goto exit;
/* pay attention to if race condition happened in H2C cmd setting. */
do {
h2c_box_num = pHalData->LastHMEBoxNum;
if (!_is_fw_read_cmd_down(padapter, h2c_box_num)) {
DBG_8723A(" fw read cmd failed...\n");
goto exit;
}
if (CmdLen <= 3) {
memcpy((u8 *)(&h2c_cmd)+1, pCmdBuffer, CmdLen);
} else {
memcpy((u8 *)(&h2c_cmd_ex), pCmdBuffer, EX_MESSAGE_BOX_SIZE);
memcpy((u8 *)(&h2c_cmd)+1, pCmdBuffer+2, (CmdLen-EX_MESSAGE_BOX_SIZE));
*(u8 *)(&h2c_cmd) |= BIT(7);
}
*(u8 *)(&h2c_cmd) |= ElementID;
if (h2c_cmd & BIT(7)) {
msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);
h2c_cmd_ex = le16_to_cpu(h2c_cmd_ex);
rtw_write16(padapter, msgbox_ex_addr, h2c_cmd_ex);
}
msgbox_addr = REG_HMEBOX_0 + (h2c_box_num * MESSAGE_BOX_SIZE);
h2c_cmd = le32_to_cpu(h2c_cmd);
rtw_write32(padapter, msgbox_addr, h2c_cmd);
bcmd_down = true;
pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL92C_MAX_H2C_BOX_NUMS;
} while ((!bcmd_down) && (retry_cnts--));
ret = _SUCCESS;
exit:
mutex_unlock(&adapter_to_dvobj(padapter)->h2c_fwcmd_mutex);
return ret;
}
u8 rtl8723a_set_rssi_cmd(struct rtw_adapter *padapter, u8 *param)
{
u8 res = _SUCCESS;
*((u32 *)param) = cpu_to_le32(*((u32 *)param));
FillH2CCmd(padapter, RSSI_SETTING_EID, 3, param);
return res;
}
u8 rtl8723a_set_raid_cmd(struct rtw_adapter *padapter, u32 mask, u8 arg)
{
u8 buf[5];
u8 res = _SUCCESS;
memset(buf, 0, 5);
mask = cpu_to_le32(mask);
memcpy(buf, &mask, 4);
buf[4] = arg;
FillH2CCmd(padapter, MACID_CONFIG_EID, 5, buf);
return res;
}
/* bitmap[0:27] = tx_rate_bitmap */
/* bitmap[28:31]= Rate Adaptive id */
/* arg[0:4] = macid */
/* arg[5] = Short GI */
void rtl8723a_add_rateatid(struct rtw_adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi_level)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
u8 macid = arg&0x1f;
u8 raid = (bitmap>>28) & 0x0f;
bitmap &= 0x0fffffff;
if (rssi_level != DM_RATR_STA_INIT)
bitmap = ODM_Get_Rate_Bitmap23a(&pHalData->odmpriv, macid, bitmap, rssi_level);
bitmap |= ((raid<<28)&0xf0000000);
if (pHalData->fw_ractrl == true) {
rtl8723a_set_raid_cmd(pAdapter, bitmap, arg);
} else {
u8 init_rate, shortGIrate = false;
init_rate = get_highest_rate_idx23a(bitmap&0x0fffffff)&0x3f;
shortGIrate = (arg&BIT(5)) ? true:false;
if (shortGIrate == true)
init_rate |= BIT(6);
rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate);
}
}
void rtl8723a_set_FwPwrMode_cmd(struct rtw_adapter *padapter, u8 Mode)
{
struct setpwrmode_parm H2CSetPwrMode;
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
DBG_8723A("%s: Mode =%d SmartPS =%d UAPSD =%d BcnMode = 0x%02x\n", __FUNCTION__,
Mode, pwrpriv->smart_ps, padapter->registrypriv.uapsd_enable, pwrpriv->bcn_ant_mode);
/* Forece leave RF low power mode for 1T1R to
prevent conficting setting in Fw power */
/* saving sequence. 2010.06.07. Added by tynli.
Suggested by SD3 yschang. */
if ((Mode != PS_MODE_ACTIVE) &&
(!IS_92C_SERIAL(pHalData->VersionID))) {
ODM_RF_Saving23a(&pHalData->odmpriv, true);
}
H2CSetPwrMode.Mode = Mode;
H2CSetPwrMode.SmartPS = pwrpriv->smart_ps;
H2CSetPwrMode.AwakeInterval = 1;
H2CSetPwrMode.bAllQueueUAPSD = padapter->registrypriv.uapsd_enable;
H2CSetPwrMode.BcnAntMode = pwrpriv->bcn_ant_mode;
FillH2CCmd(padapter, SET_PWRMODE_EID, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode);
}
static void ConstructBeacon(struct rtw_adapter *padapter, u8 *pframe, u32 *pLength)
{
struct ieee80211_hdr *pwlanhdr;
u16 *fctrl;
u32 rate_len, pktlen;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
/* DBG_8723A("%s\n", __FUNCTION__); */
pwlanhdr = (struct ieee80211_hdr *)pframe;
fctrl = &pwlanhdr->frame_control;
*(fctrl) = 0;
memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
memcpy(pwlanhdr->addr2, myid(&padapter->eeprompriv), ETH_ALEN);
memcpy(pwlanhdr->addr3, get_my_bssid23a(cur_network), ETH_ALEN);
SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
/* pmlmeext->mgnt_seq++; */
SetFrameSubType(pframe, WIFI_BEACON);
pframe += sizeof(struct ieee80211_hdr_3addr);
pktlen = sizeof (struct ieee80211_hdr_3addr);
/* timestamp will be inserted by hardware */
pframe += 8;
pktlen += 8;
/* beacon interval: 2 bytes */
memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval23a_from_ie(cur_network->IEs)), 2);
pframe += 2;
pktlen += 2;
/* capability info: 2 bytes */
memcpy(pframe, (unsigned char *)(rtw_get_capability23a_from_ie(cur_network->IEs)), 2);
pframe += 2;
pktlen += 2;
if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
/* DBG_8723A("ie len =%d\n", cur_network->IELength); */
pktlen += cur_network->IELength - sizeof(struct ndis_802_11_fixed_ies);
memcpy(pframe, cur_network->IEs+sizeof(struct ndis_802_11_fixed_ies), pktlen);
goto _ConstructBeacon;
}
/* below for ad-hoc mode */
/* SSID */
pframe = rtw_set_ie23a(pframe, _SSID_IE_, cur_network->Ssid.ssid_len,
cur_network->Ssid.ssid, &pktlen);
/* supported rates... */
rate_len = rtw_get_rateset_len23a(cur_network->SupportedRates);
pframe = rtw_set_ie23a(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ?
8 : rate_len), cur_network->SupportedRates, &pktlen);
/* DS parameter set */
pframe = rtw_set_ie23a(pframe, _DSSET_IE_, 1, (unsigned char *)&cur_network->Configuration.DSConfig, &pktlen);
if ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) {
u32 ATIMWindow;
/* IBSS Parameter Set... */
/* ATIMWindow = cur->Configuration.ATIMWindow; */
ATIMWindow = 0;
pframe = rtw_set_ie23a(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
}
/* todo: ERP IE */
/* EXTERNDED SUPPORTED RATE */
if (rate_len > 8)
pframe = rtw_set_ie23a(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
/* todo:HT for adhoc */
_ConstructBeacon:
if ((pktlen + TXDESC_SIZE) > 512) {
DBG_8723A("beacon frame too large\n");
return;
}
*pLength = pktlen;
/* DBG_8723A("%s bcn_sz =%d\n", __FUNCTION__, pktlen); */
}
static void ConstructPSPoll(struct rtw_adapter *padapter, u8 *pframe, u32 *pLength)
{
struct ieee80211_hdr *pwlanhdr;
u16 *fctrl;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
pwlanhdr = (struct ieee80211_hdr *)pframe;
/* Frame control. */
fctrl = &pwlanhdr->frame_control;
*(fctrl) = 0;
SetPwrMgt(fctrl);
SetFrameSubType(pframe, WIFI_PSPOLL);
/* AID. */
SetDuration(pframe, (pmlmeinfo->aid | 0xc000));
/* BSSID. */
memcpy(pwlanhdr->addr1, get_my_bssid23a(&pmlmeinfo->network), ETH_ALEN);
/* TA. */
memcpy(pwlanhdr->addr2, myid(&padapter->eeprompriv), ETH_ALEN);
*pLength = 16;
}
static void ConstructNullFunctionData(
struct rtw_adapter *padapter,
u8 *pframe,
u32 *pLength,
u8 *StaAddr,
u8 bQoS,
u8 AC,
u8 bEosp,
u8 bForcePowerSave)
{
struct ieee80211_hdr *pwlanhdr;
u16 *fctrl;
u32 pktlen;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct wlan_network *cur_network = &pmlmepriv->cur_network;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
pwlanhdr = (struct ieee80211_hdr *)pframe;
fctrl = &pwlanhdr->frame_control;
*(fctrl) = 0;
if (bForcePowerSave)
SetPwrMgt(fctrl);
switch (cur_network->network.InfrastructureMode) {
case Ndis802_11Infrastructure:
SetToDs(fctrl);
memcpy(pwlanhdr->addr1,
get_my_bssid23a(&pmlmeinfo->network), ETH_ALEN);
memcpy(pwlanhdr->addr2, myid(&padapter->eeprompriv),
ETH_ALEN);
memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN);
break;
case Ndis802_11APMode:
SetFrDs(fctrl);
memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
memcpy(pwlanhdr->addr2,
get_my_bssid23a(&pmlmeinfo->network), ETH_ALEN);
memcpy(pwlanhdr->addr3, myid(&padapter->eeprompriv),
ETH_ALEN);
break;
case Ndis802_11IBSS:
default:
memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
memcpy(pwlanhdr->addr2, myid(&padapter->eeprompriv), ETH_ALEN);
memcpy(pwlanhdr->addr3,
get_my_bssid23a(&pmlmeinfo->network), ETH_ALEN);
break;
}
SetSeqNum(pwlanhdr, 0);
if (bQoS == true) {
struct ieee80211_qos_hdr *pwlanqoshdr;
SetFrameSubType(pframe, WIFI_QOS_DATA_NULL);
pwlanqoshdr = (struct ieee80211_qos_hdr *)pframe;
SetPriority(&pwlanqoshdr->qos_ctrl, AC);
SetEOSP(&pwlanqoshdr->qos_ctrl, bEosp);
pktlen = sizeof(struct ieee80211_qos_hdr);
} else {
SetFrameSubType(pframe, WIFI_DATA_NULL);
pktlen = sizeof(struct ieee80211_hdr_3addr);
}
*pLength = pktlen;
}
static void ConstructProbeRsp(struct rtw_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, bool bHideSSID)
{
struct ieee80211_hdr *pwlanhdr;
u16 *fctrl;
u8 *mac, *bssid;
u32 pktlen;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
/* DBG_8723A("%s\n", __FUNCTION__); */
pwlanhdr = (struct ieee80211_hdr *)pframe;
mac = myid(&padapter->eeprompriv);
bssid = cur_network->MacAddress;
fctrl = &pwlanhdr->frame_control;
*(fctrl) = 0;
memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
SetSeqNum(pwlanhdr, 0);
SetFrameSubType(fctrl, WIFI_PROBERSP);
pktlen = sizeof(struct ieee80211_hdr_3addr);
pframe += pktlen;
if (cur_network->IELength > MAX_IE_SZ)
return;
memcpy(pframe, cur_network->IEs, cur_network->IELength);
pframe += cur_network->IELength;
pktlen += cur_network->IELength;
*pLength = pktlen;
}
/* To check if reserved page content is destroyed by beacon beacuse beacon is too large. */
void CheckFwRsvdPageContent23a(struct rtw_adapter *Adapter)
{
}
/* */
/* Description: Fill the reserved packets that FW will use to RSVD page. */
/* Now we just send 4 types packet to rsvd page. */
/* (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. */
/* Input: */
/* bDLFinished - false: At the first time we will send all the packets as a large packet to Hw, */
/* so we need to set the packet length to total lengh. */
/* true: At the second time, we should send the first packet (default:beacon) */
/* to Hw again and set the lengh in descriptor to the real beacon lengh. */
/* 2009.10.15 by tynli. */
static void SetFwRsvdPagePkt(struct rtw_adapter *padapter, bool bDLFinished)
{
struct hal_data_8723a *pHalData;
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
struct xmit_priv *pxmitpriv;
struct mlme_ext_priv *pmlmeext;
struct mlme_ext_info *pmlmeinfo;
u32 BeaconLength = 0, ProbeRspLength = 0, PSPollLength;
u32 NullDataLength, QosNullLength, BTQosNullLength;
u8 *ReservedPagePacket;
u8 PageNum, PageNeed, TxDescLen;
u16 BufIndex;
u32 TotalPacketLen;
struct rsvdpage_loc RsvdPageLoc;
DBG_8723A("%s\n", __FUNCTION__);
ReservedPagePacket = kzalloc(1000, GFP_KERNEL);
if (ReservedPagePacket == NULL) {
DBG_8723A("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
return;
}
pHalData = GET_HAL_DATA(padapter);
pxmitpriv = &padapter->xmitpriv;
pmlmeext = &padapter->mlmeextpriv;
pmlmeinfo = &pmlmeext->mlmext_info;
TxDescLen = TXDESC_SIZE;
PageNum = 0;
/* 3 (1) beacon */
BufIndex = TXDESC_OFFSET;
ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength);
/* When we count the first page size, we need to reserve description size for the RSVD */
/* packet, it will be filled in front of the packet in TXPKTBUF. */
PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength);
/* To reserved 2 pages for beacon buffer. 2010.06.24. */
if (PageNeed == 1)
PageNeed += 1;
PageNum += PageNeed;
pHalData->FwRsvdPageStartOffset = PageNum;
BufIndex += PageNeed*128;
/* 3 (2) ps-poll */
RsvdPageLoc.LocPsPoll = PageNum;
ConstructPSPoll(padapter, &ReservedPagePacket[BufIndex], &PSPollLength);
rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, true, false);
PageNeed = (u8)PageNum_128(TxDescLen + PSPollLength);
PageNum += PageNeed;
BufIndex += PageNeed*128;
/* 3 (3) null data */
RsvdPageLoc.LocNullData = PageNum;
ConstructNullFunctionData(
padapter,
&ReservedPagePacket[BufIndex],
&NullDataLength,
get_my_bssid23a(&pmlmeinfo->network),
false, 0, 0, false);
rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], NullDataLength, false, false);
PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength);
PageNum += PageNeed;
BufIndex += PageNeed*128;
/* 3 (4) probe response */
RsvdPageLoc.LocProbeRsp = PageNum;
ConstructProbeRsp(
padapter,
&ReservedPagePacket[BufIndex],
&ProbeRspLength,
get_my_bssid23a(&pmlmeinfo->network),
false);
rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], ProbeRspLength, false, false);
PageNeed = (u8)PageNum_128(TxDescLen + ProbeRspLength);
PageNum += PageNeed;
BufIndex += PageNeed*128;
/* 3 (5) Qos null data */
RsvdPageLoc.LocQosNull = PageNum;
ConstructNullFunctionData(
padapter,
&ReservedPagePacket[BufIndex],
&QosNullLength,
get_my_bssid23a(&pmlmeinfo->network),
true, 0, 0, false);
rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], QosNullLength, false, false);
PageNeed = (u8)PageNum_128(TxDescLen + QosNullLength);
PageNum += PageNeed;
BufIndex += PageNeed*128;
/* 3 (6) BT Qos null data */
RsvdPageLoc.LocBTQosNull = PageNum;
ConstructNullFunctionData(
padapter,
&ReservedPagePacket[BufIndex],
&BTQosNullLength,
get_my_bssid23a(&pmlmeinfo->network),
true, 0, 0, false);
rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], BTQosNullLength, false, true);
TotalPacketLen = BufIndex + BTQosNullLength;
pmgntframe = alloc_mgtxmitframe23a(pxmitpriv);
if (pmgntframe == NULL)
goto exit;
/* update attribute */
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib23a(padapter, pattrib);
pattrib->qsel = 0x10;
pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET;
memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen);
rtw_hal_mgnt_xmit23a(padapter, pmgntframe);
DBG_8723A("%s: Set RSVD page location to Fw\n", __FUNCTION__);
FillH2CCmd(padapter, RSVD_PAGE_EID, sizeof(RsvdPageLoc), (u8 *)&RsvdPageLoc);
exit:
kfree(ReservedPagePacket);
}
void rtl8723a_set_FwJoinBssReport_cmd(struct rtw_adapter *padapter, u8 mstatus)
{
struct joinbssrpt_parm JoinBssRptParm;
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
DBG_8723A("%s mstatus(%x)\n", __FUNCTION__, mstatus);
if (mstatus == 1) {
bool bRecover = false;
u8 v8;
/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
/* Suggested by filen. Added by tynli. */
rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));
/* Do not set TSF again here or vWiFi beacon DMA INT will not work. */
/* correct_TSF23a(padapter, pmlmeext); */
/* Hw sequende enable by dedault. 2010.06.23. by tynli. */
/* rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); */
/* rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); */
/* set REG_CR bit 8 */
v8 = rtw_read8(padapter, REG_CR+1);
v8 |= BIT(0); /* ENSWBCN */
rtw_write8(padapter, REG_CR+1, v8);
/* Disable Hw protection for a time which revserd for Hw sending beacon. */
/* Fix download reserved page packet fail that access collision with the protection time. */
/* 2010.05.11. Added by tynli. */
/* SetBcnCtrlReg23a(padapter, 0, BIT(3)); */
/* SetBcnCtrlReg23a(padapter, BIT(4), 0); */
SetBcnCtrlReg23a(padapter, BIT(4), BIT(3));
/* Set FWHW_TXQ_CTRL 0x422[6]= 0 to tell Hw the packet is not a real beacon frame. */
if (pHalData->RegFwHwTxQCtrl & BIT(6))
bRecover = true;
/* To tell Hw the packet is not a real beacon frame. */
/* U1bTmp = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2); */
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl & ~BIT(6));
pHalData->RegFwHwTxQCtrl &= ~BIT(6);
SetFwRsvdPagePkt(padapter, 0);
/* 2010.05.11. Added by tynli. */
SetBcnCtrlReg23a(padapter, BIT(3), BIT(4));
/* To make sure that if there exists an adapter which would like to send beacon. */
/* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
/* the beacon cannot be sent by HW. */
/* 2010.06.23. Added by tynli. */
if (bRecover) {
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl | BIT(6));
pHalData->RegFwHwTxQCtrl |= BIT(6);
}
/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
v8 = rtw_read8(padapter, REG_CR+1);
v8 &= ~BIT(0); /* ~ENSWBCN */
rtw_write8(padapter, REG_CR+1, v8);
}
JoinBssRptParm.OpMode = mstatus;
FillH2CCmd(padapter, JOINBSS_RPT_EID, sizeof(JoinBssRptParm), (u8 *)&JoinBssRptParm);
}
#ifdef CONFIG_8723AU_BT_COEXIST
static void SetFwRsvdPagePkt_BTCoex(struct rtw_adapter *padapter)
{
struct hal_data_8723a *pHalData;
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
struct xmit_priv *pxmitpriv;
struct mlme_ext_priv *pmlmeext;
struct mlme_ext_info *pmlmeinfo;
u8 fakemac[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x00};
u32 NullDataLength, BTQosNullLength;
u8 *ReservedPagePacket;
u8 PageNum, PageNeed, TxDescLen;
u16 BufIndex;
u32 TotalPacketLen;
struct rsvdpage_loc RsvdPageLoc;
DBG_8723A("+%s\n", __FUNCTION__);
ReservedPagePacket = kzalloc(1024, GFP_KERNEL);
if (ReservedPagePacket == NULL) {
DBG_8723A("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
return;
}
pHalData = GET_HAL_DATA(padapter);
pxmitpriv = &padapter->xmitpriv;
pmlmeext = &padapter->mlmeextpriv;
pmlmeinfo = &pmlmeext->mlmext_info;
TxDescLen = TXDESC_SIZE;
PageNum = 0;
/* 3 (1) beacon */
BufIndex = TXDESC_OFFSET;
/* skip Beacon Packet */
PageNeed = 3;
PageNum += PageNeed;
pHalData->FwRsvdPageStartOffset = PageNum;
BufIndex += PageNeed*128;
/* 3 (3) null data */
RsvdPageLoc.LocNullData = PageNum;
ConstructNullFunctionData(
padapter,
&ReservedPagePacket[BufIndex],
&NullDataLength,
fakemac,
false, 0, 0, false);
rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], NullDataLength, false, false);
PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength);
PageNum += PageNeed;
BufIndex += PageNeed*128;
/* 3 (6) BT Qos null data */
RsvdPageLoc.LocBTQosNull = PageNum;
ConstructNullFunctionData(
padapter,
&ReservedPagePacket[BufIndex],
&BTQosNullLength,
fakemac,
true, 0, 0, false);
rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], BTQosNullLength, false, true);
TotalPacketLen = BufIndex + BTQosNullLength;
pmgntframe = alloc_mgtxmitframe23a(pxmitpriv);
if (pmgntframe == NULL)
goto exit;
/* update attribute */
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib23a(padapter, pattrib);
pattrib->qsel = 0x10;
pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET;
memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen);
rtw_hal_mgnt_xmit23a(padapter, pmgntframe);
DBG_8723A("%s: Set RSVD page location to Fw\n", __FUNCTION__);
FillH2CCmd(padapter, RSVD_PAGE_EID, sizeof(RsvdPageLoc), (u8 *)&RsvdPageLoc);
exit:
kfree(ReservedPagePacket);
}
void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(struct rtw_adapter *padapter)
{
struct hal_data_8723a *pHalData;
u8 bRecover = false;
DBG_8723A("+%s\n", __FUNCTION__);
pHalData = GET_HAL_DATA(padapter);
/* Set FWHW_TXQ_CTRL 0x422[6]= 0 to tell Hw the packet is not a real beacon frame. */
if (pHalData->RegFwHwTxQCtrl & BIT(6))
bRecover = true;
/* To tell Hw the packet is not a real beacon frame. */
pHalData->RegFwHwTxQCtrl &= ~BIT(6);
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
SetFwRsvdPagePkt_BTCoex(padapter);
/* To make sure that if there exists an adapter which would like to send beacon. */
/* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
/* the beacon cannot be sent by HW. */
/* 2010.06.23. Added by tynli. */
if (bRecover) {
pHalData->RegFwHwTxQCtrl |= BIT(6);
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
}
}
#endif
#ifdef CONFIG_8723AU_P2P
void rtl8723a_set_p2p_ps_offload_cmd(struct rtw_adapter *padapter, u8 p2p_ps_state)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
struct P2P_PS_Offload_t *p2p_ps_offload = &pHalData->p2p_ps_offload;
u8 i;
switch (p2p_ps_state) {
case P2P_PS_DISABLE:
DBG_8723A("P2P_PS_DISABLE \n");
memset(p2p_ps_offload, 0, 1);
break;
case P2P_PS_ENABLE:
DBG_8723A("P2P_PS_ENABLE \n");
/* update CTWindow value. */
if (pwdinfo->ctwindow > 0) {
p2p_ps_offload->CTWindow_En = 1;
rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow);
}
/* hw only support 2 set of NoA */
for (i = 0; i < pwdinfo->noa_num; i++) {
/* To control the register setting for which NOA */
rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4));
if (i == 0)
p2p_ps_offload->NoA0_En = 1;
else
p2p_ps_offload->NoA1_En = 1;
/* config P2P NoA Descriptor Register */
rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]);
rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]);
rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]);
rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]);
}
if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {
/* rst p2p circuit */
rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4));
p2p_ps_offload->Offload_En = 1;
if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
p2p_ps_offload->role = 1;
p2p_ps_offload->AllStaSleep = 0;
} else {
p2p_ps_offload->role = 0;
}
p2p_ps_offload->discovery = 0;
}
break;
case P2P_PS_SCAN:
DBG_8723A("P2P_PS_SCAN \n");
p2p_ps_offload->discovery = 1;
break;
case P2P_PS_SCAN_DONE:
DBG_8723A("P2P_PS_SCAN_DONE \n");
p2p_ps_offload->discovery = 0;
pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
break;
default:
break;
}
FillH2CCmd(padapter, P2P_PS_OFFLOAD_EID, 1, (u8 *)p2p_ps_offload);
}
#endif /* CONFIG_8723AU_P2P */

273
drivers/staging/rtl8723au/hal/rtl8723a_dm.c Normal file
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@ -0,0 +1,273 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/* */
/* Description: */
/* */
/* This file is for 92CE/92CU dynamic mechanism only */
/* */
/* */
/* */
#define _RTL8723A_DM_C_
/* */
/* include files */
/* */
#include <osdep_service.h>
#include <drv_types.h>
#include <rtl8723a_hal.h>
/* */
/* Global var */
/* */
static void dm_CheckStatistics(struct rtw_adapter *Adapter)
{
}
static void dm_CheckPbcGPIO(struct rtw_adapter *padapter)
{
u8 tmp1byte;
u8 bPbcPressed = false;
if (!padapter->registrypriv.hw_wps_pbc)
return;
tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as output mode */
tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IN, tmp1byte); /* reset the floating voltage level */
tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as input mode */
tmp1byte = rtw_read8(padapter, GPIO_IN);
if (tmp1byte == 0xff)
return;
if (tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT)
bPbcPressed = true;
if (bPbcPressed) {
/* Here we only set bPbcPressed to true */
/* After trigger PBC, the variable will be set to false */
DBG_8723A("CheckPbcGPIO - PBC is pressed\n");
if (padapter->pid[0] == 0) {
/* 0 is the default value and it means the application
* monitors the HW PBC doesn't privde its pid to driver.
*/
return;
}
rtw_signal_process(padapter->pid[0], SIGUSR1);
}
}
/* Initialize GPIO setting registers */
/* functions */
static void Init_ODM_ComInfo_8723a(struct rtw_adapter *Adapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
u8 cut_ver, fab_ver;
/* */
/* Init Value */
/* */
memset(pDM_Odm, 0, sizeof(*pDM_Odm));
pDM_Odm->Adapter = Adapter;
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_PLATFORM, 0x04);
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_INTERFACE, RTW_USB);/* RTL871X_HCI_TYPE */
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8723A);
if (IS_8723A_A_CUT(pHalData->VersionID)) {
fab_ver = ODM_UMC;
cut_ver = ODM_CUT_A;
} else if (IS_8723A_B_CUT(pHalData->VersionID)) {
fab_ver = ODM_UMC;
cut_ver = ODM_CUT_B;
} else {
fab_ver = ODM_TSMC;
cut_ver = ODM_CUT_A;
}
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_FAB_VER, fab_ver);
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_CUT_VER, cut_ver);
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->VersionID));
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, pHalData->BoardType);
if (pHalData->BoardType == BOARD_USB_High_PA) {
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_EXT_LNA, true);
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_EXT_PA, true);
}
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
ODM_CmnInfoInit23a(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, Adapter->registrypriv.wifi_spec);
if (pHalData->rf_type == RF_1T1R)
ODM_CmnInfoUpdate23a(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R);
else if (pHalData->rf_type == RF_2T2R)
ODM_CmnInfoUpdate23a(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R);
else if (pHalData->rf_type == RF_1T2R)
ODM_CmnInfoUpdate23a(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R);
}
static void Update_ODM_ComInfo_8723a(struct rtw_adapter *Adapter)
{
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
int i;
pdmpriv->InitODMFlag = ODM_BB_DIG |
ODM_BB_RA_MASK |
ODM_BB_DYNAMIC_TXPWR |
ODM_BB_FA_CNT |
ODM_BB_RSSI_MONITOR |
ODM_BB_CCK_PD |
ODM_BB_PWR_SAVE |
ODM_MAC_EDCA_TURBO |
ODM_RF_TX_PWR_TRACK |
ODM_RF_CALIBRATION;
/* Pointer reference */
ODM_CmnInfoUpdate23a(pDM_Odm, ODM_CMNINFO_ABILITY, pdmpriv->InitODMFlag);
ODM23a_CmnInfoHook(pDM_Odm, ODM_CMNINFO_TX_UNI,
&Adapter->xmitpriv.tx_bytes);
ODM23a_CmnInfoHook(pDM_Odm, ODM_CMNINFO_RX_UNI,
&Adapter->recvpriv.rx_bytes);
ODM23a_CmnInfoHook(pDM_Odm, ODM_CMNINFO_WM_MODE,
&pmlmeext->cur_wireless_mode);
ODM23a_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET,
&pHalData->nCur40MhzPrimeSC);
ODM23a_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_MODE,
&Adapter->securitypriv.dot11PrivacyAlgrthm);
ODM23a_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BW,
&pHalData->CurrentChannelBW);
ODM23a_CmnInfoHook(pDM_Odm, ODM_CMNINFO_CHNL,
&pHalData->CurrentChannel);
ODM23a_CmnInfoHook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &Adapter->net_closed);
ODM23a_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SCAN, &pmlmepriv->bScanInProcess);
ODM23a_CmnInfoHook(pDM_Odm, ODM_CMNINFO_POWER_SAVING,
&pwrctrlpriv->bpower_saving);
for (i = 0; i < NUM_STA; i++)
ODM_CmnInfoPtrArrayHook23a(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL);
}
void rtl8723a_InitHalDm(struct rtw_adapter *Adapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
u8 i;
pdmpriv->DM_Type = DM_Type_ByDriver;
pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE;
#ifdef CONFIG_8723AU_BT_COEXIST
pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
#endif
pdmpriv->InitDMFlag = pdmpriv->DMFlag;
Update_ODM_ComInfo_8723a(Adapter);
ODM23a_DMInit(pDM_Odm);
/* Save REG_INIDATA_RATE_SEL value for TXDESC. */
for (i = 0; i < 32; i++)
pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL+i) & 0x3f;
}
void
rtl8723a_HalDmWatchDog(
struct rtw_adapter *Adapter
)
{
bool bFwCurrentInPSMode = false;
bool bFwPSAwake = true;
u8 hw_init_completed = false;
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
hw_init_completed = Adapter->hw_init_completed;
if (hw_init_completed == false)
goto skip_dm;
bFwCurrentInPSMode = Adapter->pwrctrlpriv.bFwCurrentInPSMode;
rtw23a_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake));
#ifdef CONFIG_8723AU_P2P
/* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */
/* modifed by thomas. 2011.06.11. */
if (Adapter->wdinfo.p2p_ps_mode)
bFwPSAwake = false;
#endif /* CONFIG_8723AU_P2P */
if ((hw_init_completed) && ((!bFwCurrentInPSMode) && bFwPSAwake)) {
/* Calculate Tx/Rx statistics. */
dm_CheckStatistics(Adapter);
/* Read REG_INIDATA_RATE_SEL value for TXDESC. */
if (check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE)) {
pdmpriv->INIDATA_RATE[0] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL) & 0x3f;
} else {
u8 i;
for (i = 1 ; i < (Adapter->stapriv.asoc_sta_count + 1); i++)
pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, (REG_INIDATA_RATE_SEL+i)) & 0x3f;
}
}
/* ODM */
if (hw_init_completed == true) {
u8 bLinked = false;
if (rtw_linked_check(Adapter))
bLinked = true;
ODM_CmnInfoUpdate23a(&pHalData->odmpriv, ODM_CMNINFO_LINK,
bLinked);
ODM_DMWatchdog23a(&pHalData->odmpriv);
}
skip_dm:
/* Check GPIO to determine current RF on/off and Pbc status. */
/* Check Hardware Radio ON/OFF or not */
dm_CheckPbcGPIO(Adapter);
}
void rtl8723a_init_dm_priv(struct rtw_adapter *Adapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
memset(pdmpriv, 0, sizeof(struct dm_priv));
Init_ODM_ComInfo_8723a(Adapter);
}
void rtl8723a_deinit_dm_priv(struct rtw_adapter *Adapter)
{
}

3452
drivers/staging/rtl8723au/hal/rtl8723a_hal_init.c Normal file
View File

File diff suppressed because it is too large Load Diff

1162
drivers/staging/rtl8723au/hal/rtl8723a_phycfg.c Normal file
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File diff suppressed because it is too large Load Diff

507
drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c Normal file
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@ -0,0 +1,507 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/******************************************************************************
*
*
* Module: rtl8192c_rf6052.c (Source C File)
*
* Note: Provide RF 6052 series relative API.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
* 11/05/2008 MHC Add API for tw power setting.
*
*
******************************************************************************/
#define _RTL8723A_RF6052_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <rtl8723a_hal.h>
/*---------------------------Define Local Constant---------------------------*/
/* Define local structure for debug!!!!! */
struct rf_shadow_compare_map {
/* Shadow register value */
u32 Value;
/* Compare or not flag */
u8 Compare;
/* Record If it had ever modified unpredicted */
u8 ErrorOrNot;
/* Recorver Flag */
u8 Recorver;
/* */
u8 Driver_Write;
};
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWMode23aCallback8190Pci() only
*
* Input: struct rtw_adapter * Adapter
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
void rtl8723a_phy_rf6052set_bw(
struct rtw_adapter *Adapter,
enum ht_channel_width Bandwidth) /* 20M or 40M */
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
switch (Bandwidth) {
case HT_CHANNEL_WIDTH_20:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400);
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
case HT_CHANNEL_WIDTH_40:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff));
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
default:
break;
}
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetCckTxPower
*
* Overview:
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/05/2008 MHC Simulate 8192series..
*
*---------------------------------------------------------------------------*/
void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, u8 *pPowerlevel)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
u32 TxAGC[2] = {0, 0}, tmpval = 0;
bool TurboScanOff = false;
u8 idx1, idx2;
u8 *ptr;
/* According to SD3 eechou's suggestion, we need to disable turbo scan for RU. */
/* Otherwise, external PA will be broken if power index > 0x20. */
if (pHalData->EEPROMRegulatory != 0 || pHalData->ExternalPA)
TurboScanOff = true;
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
TxAGC[RF_PATH_A] = 0x3f3f3f3f;
TxAGC[RF_PATH_B] = 0x3f3f3f3f;
TurboScanOff = true;/* disable turbo scan */
if (TurboScanOff) {
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
/* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */
if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
TxAGC[idx1] = 0x20;
}
}
} else {
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
TxAGC[RF_PATH_A] = 0x10101010;
TxAGC[RF_PATH_B] = 0x10101010;
} else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
TxAGC[RF_PATH_A] = 0x00000000;
TxAGC[RF_PATH_B] = 0x00000000;
} else {
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
}
if (pHalData->EEPROMRegulatory == 0) {
tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
(pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
TxAGC[RF_PATH_A] += tmpval;
tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
(pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);
TxAGC[RF_PATH_B] += tmpval;
}
}
}
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
ptr = (u8 *)(&TxAGC[idx1]);
for (idx2 = 0; idx2 < 4; idx2++) {
if (*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR;
ptr++;
}
}
/* rf-A cck tx power */
tmpval = TxAGC[RF_PATH_A]&0xff;
PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
tmpval = TxAGC[RF_PATH_A]>>8;
PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
/* rf-B cck tx power */
tmpval = TxAGC[RF_PATH_B]>>24;
PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
} /* PHY_RF6052SetCckTxPower */
/* powerbase0 for OFDM rates */
/* powerbase1 for HT MCS rates */
static void getPowerBase(
struct rtw_adapter *Adapter,
u8 *pPowerLevel,
u8 Channel,
u32 *OfdmBase,
u32 *MCSBase
)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
u32 powerBase0, powerBase1;
u8 Legacy_pwrdiff = 0;
s8 HT20_pwrdiff = 0;
u8 i, powerlevel[2];
for (i = 0; i < 2; i++) {
powerlevel[i] = pPowerLevel[i];
Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];
powerBase0 = powerlevel[i] + Legacy_pwrdiff;
powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
*(OfdmBase+i) = powerBase0;
}
for (i = 0; i < 2; i++) {
/* Check HT20 to HT40 diff */
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) {
HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1];
powerlevel[i] += HT20_pwrdiff;
}
powerBase1 = powerlevel[i];
powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
*(MCSBase+i) = powerBase1;
}
}
static void getTxPowerWriteValByRegulatory(
struct rtw_adapter *Adapter,
u8 Channel,
u8 index,
u32 *powerBase0,
u32 *powerBase1,
u32 *pOutWriteVal
)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 i, chnlGroup = 0, pwr_diff_limit[4];
u32 writeVal, customer_limit, rf;
/* Index 0 & 1 = legacy OFDM, 2-5 = HT_MCS rate */
for (rf = 0; rf < 2; rf++) {
switch (pHalData->EEPROMRegulatory) {
case 0: /* Realtek better performance */
/* increase power diff defined by Realtek for large power */
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 1: /* Realtek regulatory */
/* increase power diff defined by Realtek for regulatory */
if (pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
if (pHalData->pwrGroupCnt >= 3) {
if (Channel <= 3)
chnlGroup = 0;
else if (Channel >= 4 && Channel <= 9)
chnlGroup = 1;
else if (Channel > 9)
chnlGroup = 2;
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
chnlGroup++;
else
chnlGroup += 4;
}
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 2: /* Better regulatory */
/* don't increase any power diff */
writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 3: /* Customer defined power diff. */
chnlGroup = 0;
for (i = 0; i < 4; i++) {
pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index +
(rf ? 8 : 0)]&(0x7f << (i*8))) >> (i*8));
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) {
if (pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1])
pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1];
} else {
if (pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1])
pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1];
}
}
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
break;
default:
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
}
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
writeVal = 0x14141414;
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
writeVal = 0x00000000;
/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
writeVal = writeVal - 0x06060606;
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
writeVal = writeVal;
*(pOutWriteVal+rf) = writeVal;
}
}
static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
u16 RegOffset_A[6] = {
rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12
};
u16 RegOffset_B[6] = {
rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12
};
u8 i, rf, pwr_val[4];
u32 writeVal;
u16 RegOffset;
for (rf = 0; rf < 2; rf++) {
writeVal = pValue[rf];
for (i = 0; i < 4; i++) {
pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
if (pwr_val[i] > RF6052_MAX_TX_PWR)
pwr_val[i] = RF6052_MAX_TX_PWR;
}
writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |
(pwr_val[1]<<8) | pwr_val[0];
if (rf == 0)
RegOffset = RegOffset_A[index];
else
RegOffset = RegOffset_B[index];
PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
if (((pHalData->rf_type == RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs15_Mcs12 ||
RegOffset == rTxAGC_B_Mcs15_Mcs12)) ||
((pHalData->rf_type != RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs07_Mcs04 ||
RegOffset == rTxAGC_B_Mcs07_Mcs04))) {
writeVal = pwr_val[3];
if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
RegOffset = 0xc90;
if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
RegOffset = 0xc98;
for (i = 0; i < 3; i++) {
if (i != 2)
writeVal = (writeVal > 8) ? (writeVal-8) : 0;
else
writeVal = (writeVal > 6) ? (writeVal-6) : 0;
rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal);
}
}
}
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetOFDMTxPower
*
* Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
* different channel and read original value in TX power register area from
* 0xe00. We increase offset and original value to be correct tx pwr.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/05/2008 MHC Simulate 8192 series method.
* 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
* A/B pwr difference or legacy/HT pwr diff.
* 2. We concern with path B legacy/HT OFDM difference.
* 01/22/2009 MHC Support new EPRO format from SD3.
*
*---------------------------------------------------------------------------*/
void rtl8723a_PHY_RF6052SetOFDMTxPower(struct rtw_adapter *Adapter, u8 *pPowerLevel, u8 Channel)
{
u32 writeVal[2], powerBase0[2], powerBase1[2];
u8 index = 0;
getPowerBase(Adapter, pPowerLevel, Channel, &powerBase0[0], &powerBase1[0]);
for (index = 0; index < 6; index++) {
getTxPowerWriteValByRegulatory(Adapter, Channel, index,
&powerBase0[0], &powerBase1[0], &writeVal[0]);
writeOFDMPowerReg(Adapter, index, &writeVal[0]);
}
}
static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter)
{
u32 u4RegValue = 0;
u8 eRFPath;
struct bb_reg_define *pPhyReg;
int rtStatus = _SUCCESS;
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
static char sz8723RadioAFile[] = RTL8723_PHY_RADIO_A;
static char sz8723RadioBFile[] = RTL8723_PHY_RADIO_B;
char *pszRadioAFile, *pszRadioBFile;
pszRadioAFile = sz8723RadioAFile;
pszRadioBFile = sz8723RadioBFile;
/* 3----------------------------------------------------------------- */
/* 3 <2> Initialize RF */
/* 3----------------------------------------------------------------- */
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch (eRFPath) {
case RF_PATH_A:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF_PATH_B:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
udelay(1);/* PlatformStallExecution(1); */
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
udelay(1);/* PlatformStallExecution(1); */
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
udelay(1);/* PlatformStallExecution(1); */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
udelay(1);/* PlatformStallExecution(1); */
/*----Initialize RF fom connfiguration file----*/
switch (eRFPath) {
case RF_PATH_A:
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile23a(&pHalData->odmpriv, (enum RF_RADIO_PATH)eRFPath, (enum RF_RADIO_PATH)eRFPath))
rtStatus = _FAIL;
break;
case RF_PATH_B:
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile23a(&pHalData->odmpriv, (enum RF_RADIO_PATH)eRFPath, (enum RF_RADIO_PATH)eRFPath))
rtStatus = _FAIL;
break;
}
/*----Restore RFENV control type----*/;
switch (eRFPath) {
case RF_PATH_A:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF_PATH_B:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if (rtStatus != _SUCCESS) {
/* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */
goto phy_RF6052_Config_ParaFile_Fail;
}
}
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
int PHY_RF6052_Config8723A(struct rtw_adapter *Adapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS;
/* Initialize general global value */
/* TODO: Extend RF_PATH_C and RF_PATH_D in the future */
if (pHalData->rf_type == RF_1T1R)
pHalData->NumTotalRFPath = 1;
else
pHalData->NumTotalRFPath = 2;
/* Config BB and RF */
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
return rtStatus;
}
/* End of HalRf6052.c */

69
drivers/staging/rtl8723au/hal/rtl8723a_rxdesc.c Normal file
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@ -0,0 +1,69 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _RTL8723A_REDESC_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <rtl8723a_hal.h>
static void process_rssi(struct rtw_adapter *padapter,
struct recv_frame *prframe)
{
struct rx_pkt_attrib *pattrib = &prframe->attrib;
struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data;
if (signal_stat->update_req) {
signal_stat->total_num = 0;
signal_stat->total_val = 0;
signal_stat->update_req = 0;
}
signal_stat->total_num++;
signal_stat->total_val += pattrib->phy_info.SignalStrength;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
}
static void process_link_qual(struct rtw_adapter *padapter,
struct recv_frame *prframe)
{
struct rx_pkt_attrib *pattrib;
struct signal_stat *signal_stat;
if (prframe == NULL || padapter == NULL)
return;
pattrib = &prframe->attrib;
signal_stat = &padapter->recvpriv.signal_qual_data;
if (signal_stat->update_req) {
signal_stat->total_num = 0;
signal_stat->total_val = 0;
signal_stat->update_req = 0;
}
signal_stat->total_num++;
signal_stat->total_val += pattrib->phy_info.SignalQuality;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
}
/* void rtl8723a_process_phy_info(struct rtw_adapter *padapter, union recv_frame *prframe) */
void rtl8723a_process_phy_info(struct rtw_adapter *padapter, void *prframe)
{
struct recv_frame *precvframe = prframe;
/* Check RSSI */
process_rssi(padapter, precvframe);
/* Check EVM */
process_link_qual(padapter, precvframe);
}

73
drivers/staging/rtl8723au/hal/rtl8723a_sreset.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _RTL8723A_SRESET_C_
#include <rtl8723a_sreset.h>
#include <rtl8723a_hal.h>
void rtl8723a_sreset_xmit_status_check(struct rtw_adapter *padapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
unsigned long current_time;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
unsigned int diff_time;
u32 txdma_status;
txdma_status = rtw_read32(padapter, REG_TXDMA_STATUS);
if (txdma_status != 0) {
DBG_8723A("%s REG_TXDMA_STATUS:0x%08x\n", __func__, txdma_status);
rtw_hal_sreset_reset23a(padapter);
}
current_time = jiffies;
if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
diff_time = jiffies_to_msecs(jiffies - psrtpriv->last_tx_time);
if (diff_time > 2000) {
if (psrtpriv->last_tx_complete_time == 0) {
psrtpriv->last_tx_complete_time = current_time;
} else {
diff_time = jiffies_to_msecs(jiffies - psrtpriv->last_tx_complete_time);
if (diff_time > 4000) {
/* padapter->Wifi_Error_Status = WIFI_TX_HANG; */
DBG_8723A("%s tx hang\n", __func__);
rtw_hal_sreset_reset23a(padapter);
}
}
}
}
if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset23a(padapter);
return;
}
}
void rtl8723a_sreset_linked_status_check(struct rtw_adapter *padapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset23a(padapter);
return;
}
}

52
drivers/staging/rtl8723au/hal/rtl8723a_xmit.c Normal file
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@ -0,0 +1,52 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _RTL8723A_XMIT_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <rtl8723a_hal.h>
void dump_txrpt_ccx_8723a(void *buf)
{
struct txrpt_ccx_8723a *txrpt_ccx = buf;
DBG_8723A("%s:\n"
"tag1:%u, rsvd:%u, int_bt:%u, int_tri:%u, int_ccx:%u\n"
"mac_id:%u, pkt_drop:%u, pkt_ok:%u, bmc:%u\n"
"retry_cnt:%u, lifetime_over:%u, retry_over:%u\n"
"ccx_qtime:%u\n"
"final_data_rate:0x%02x\n"
"qsel:%u, sw:0x%03x\n"
, __func__
, txrpt_ccx->tag1, txrpt_ccx->rsvd, txrpt_ccx->int_bt, txrpt_ccx->int_tri, txrpt_ccx->int_ccx
, txrpt_ccx->mac_id, txrpt_ccx->pkt_drop, txrpt_ccx->pkt_ok, txrpt_ccx->bmc
, txrpt_ccx->retry_cnt, txrpt_ccx->lifetime_over, txrpt_ccx->retry_over
, txrpt_ccx_qtime_8723a(txrpt_ccx)
, txrpt_ccx->final_data_rate
, txrpt_ccx->qsel, txrpt_ccx_sw_8723a(txrpt_ccx)
);
}
void handle_txrpt_ccx_8723a(struct rtw_adapter *adapter, void *buf)
{
struct txrpt_ccx_8723a *txrpt_ccx = buf;
if (txrpt_ccx->int_ccx) {
if (txrpt_ccx->pkt_ok)
rtw_ack_tx_done23a(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
else
rtw_ack_tx_done23a(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
}
}

113
drivers/staging/rtl8723au/hal/rtl8723au_led.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "drv_types.h"
#include "rtl8723a_hal.h"
#include "rtl8723a_led.h"
/* */
/* LED object. */
/* */
/* */
/* Prototype of protected function. */
/* */
/* */
/* LED_819xUsb routines. */
/* */
/* Description: */
/* Turn on LED according to LedPin specified. */
void SwLedOn23a(struct rtw_adapter *padapter, struct led_8723a *pLed)
{
u8 LedCfg = 0;
if ((padapter->bSurpriseRemoved == true) || (padapter->bDriverStopped == true))
return;
switch (pLed->LedPin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
rtw_write8(padapter, REG_LEDCFG0, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */
break;
case LED_PIN_LED1:
rtw_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT6); /* SW control led1 on. */
break;
case LED_PIN_LED2:
LedCfg = rtw_read8(padapter, REG_LEDCFG2);
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT5); /* SW control led1 on. */
break;
default:
break;
}
pLed->bLedOn = true;
}
/* Description: */
/* Turn off LED according to LedPin specified. */
void SwLedOff23a(struct rtw_adapter *padapter, struct led_8723a *pLed)
{
u8 LedCfg = 0;
/* struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); */
if ((padapter->bSurpriseRemoved) || (padapter->bDriverStopped))
goto exit;
switch (pLed->LedPin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
rtw_write8(padapter, REG_LEDCFG0, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */
break;
case LED_PIN_LED1:
rtw_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT5|BIT6); /* SW control led1 on. */
break;
case LED_PIN_LED2:
LedCfg = rtw_read8(padapter, REG_LEDCFG2);
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT3|BIT5); /* SW control led1 on. */
break;
default:
break;
}
exit:
pLed->bLedOn = false;
}
/* Interface to manipulate LED objects. */
/* Description: */
/* Initialize all LED_871x objects. */
void
rtl8723au_InitSwLeds(struct rtw_adapter *padapter)
{
struct led_priv *pledpriv = &padapter->ledpriv;
pledpriv->LedControlHandler = LedControl871x23a;
/* 8723as-vau wifi used led2 */
InitLed871x23a(padapter, &pledpriv->SwLed0, LED_PIN_LED2);
/* InitLed871x23a(padapter,&pledpriv->SwLed1, LED_PIN_LED2); */
}
/* Description: */
/* DeInitialize all LED_819xUsb objects. */
void
rtl8723au_DeInitSwLeds(struct rtw_adapter *padapter)
{
struct led_priv *ledpriv = &padapter->ledpriv;
DeInitLed871x23a(&ledpriv->SwLed0);
}

247
drivers/staging/rtl8723au/hal/rtl8723au_recv.c Normal file
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@ -0,0 +1,247 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _RTL8192CU_RECV_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <recv_osdep.h>
#include <mlme_osdep.h>
#include <linux/ip.h>
#include <linux/if_ether.h>
#include <ethernet.h>
#include <usb_ops.h>
#include <wifi.h>
#include <rtl8723a_hal.h>
void rtl8723au_init_recvbuf(struct rtw_adapter *padapter,
struct recv_buf *precvbuf)
{
}
int rtl8723au_init_recv_priv(struct rtw_adapter *padapter)
{
struct recv_priv *precvpriv = &padapter->recvpriv;
int i, size, res = _SUCCESS;
struct recv_buf *precvbuf;
unsigned long tmpaddr;
unsigned long alignment;
struct sk_buff *pskb;
tasklet_init(&precvpriv->recv_tasklet,
(void(*)(unsigned long))rtl8723au_recv_tasklet,
(unsigned long)padapter);
precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL);
if (!precvpriv->int_in_urb)
DBG_8723A("alloc_urb for interrupt in endpoint fail !!!!\n");
precvpriv->int_in_buf = kzalloc(USB_INTR_CONTENT_LENGTH, GFP_KERNEL);
if (!precvpriv->int_in_buf)
DBG_8723A("alloc_mem for interrupt in endpoint fail !!!!\n");
/* init recv_buf */
_rtw_init_queue23a(&precvpriv->free_recv_buf_queue);
size = NR_RECVBUFF * sizeof(struct recv_buf);
precvpriv->precv_buf = kzalloc(size, GFP_KERNEL);
if (!precvpriv->precv_buf) {
res = _FAIL;
RT_TRACE(_module_rtl871x_recv_c_, _drv_err_,
("alloc recv_buf fail!\n"));
goto exit;
}
precvbuf = (struct recv_buf *)precvpriv->precv_buf;
for (i = 0; i < NR_RECVBUFF; i++) {
INIT_LIST_HEAD(&precvbuf->list);
res = rtw_os_recvbuf_resource_alloc23a(padapter, precvbuf);
if (res == _FAIL)
break;
precvbuf->adapter = padapter;
precvbuf++;
}
precvpriv->free_recv_buf_queue_cnt = NR_RECVBUFF;
skb_queue_head_init(&precvpriv->rx_skb_queue);
skb_queue_head_init(&precvpriv->free_recv_skb_queue);
for (i = 0; i < NR_PREALLOC_RECV_SKB; i++) {
size = MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ;
pskb = __netdev_alloc_skb(padapter->pnetdev, size, GFP_KERNEL);
if (pskb) {
pskb->dev = padapter->pnetdev;
tmpaddr = (unsigned long)pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
}
pskb = NULL;
}
exit:
return res;
}
void rtl8723au_free_recv_priv(struct rtw_adapter *padapter)
{
int i;
struct recv_buf *precvbuf;
struct recv_priv *precvpriv = &padapter->recvpriv;
precvbuf = (struct recv_buf *)precvpriv->precv_buf;
for (i = 0; i < NR_RECVBUFF; i++) {
rtw_os_recvbuf_resource_free23a(padapter, precvbuf);
precvbuf++;
}
kfree(precvpriv->precv_buf);
usb_free_urb(precvpriv->int_in_urb);
kfree(precvpriv->int_in_buf);
if (skb_queue_len(&precvpriv->rx_skb_queue))
DBG_8723A(KERN_WARNING "rx_skb_queue not empty\n");
skb_queue_purge(&precvpriv->rx_skb_queue);
if (skb_queue_len(&precvpriv->free_recv_skb_queue)) {
DBG_8723A(KERN_WARNING "free_recv_skb_queue not empty, %d\n",
skb_queue_len(&precvpriv->free_recv_skb_queue));
}
skb_queue_purge(&precvpriv->free_recv_skb_queue);
}
void update_recvframe_attrib(struct recv_frame *precvframe,
struct recv_stat *prxstat)
{
struct rx_pkt_attrib *pattrib;
struct recv_stat report;
struct rxreport_8723a *prxreport;
report.rxdw0 = le32_to_cpu(prxstat->rxdw0);
report.rxdw1 = le32_to_cpu(prxstat->rxdw1);
report.rxdw2 = le32_to_cpu(prxstat->rxdw2);
report.rxdw3 = le32_to_cpu(prxstat->rxdw3);
report.rxdw4 = le32_to_cpu(prxstat->rxdw4);
report.rxdw5 = le32_to_cpu(prxstat->rxdw5);
prxreport = (struct rxreport_8723a *)&report;
pattrib = &precvframe->attrib;
memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
/* update rx report to recv_frame attribute */
pattrib->pkt_len = (u16)prxreport->pktlen;
pattrib->drvinfo_sz = (u8)(prxreport->drvinfosize << 3);
pattrib->physt = (u8)prxreport->physt;
pattrib->crc_err = (u8)prxreport->crc32;
pattrib->icv_err = (u8)prxreport->icverr;
pattrib->bdecrypted = (u8)(prxreport->swdec ? 0 : 1);
pattrib->encrypt = (u8)prxreport->security;
pattrib->qos = (u8)prxreport->qos;
pattrib->priority = (u8)prxreport->tid;
pattrib->amsdu = (u8)prxreport->amsdu;
pattrib->seq_num = (u16)prxreport->seq;
pattrib->frag_num = (u8)prxreport->frag;
pattrib->mfrag = (u8)prxreport->mf;
pattrib->mdata = (u8)prxreport->md;
pattrib->mcs_rate = (u8)prxreport->rxmcs;
pattrib->rxht = (u8)prxreport->rxht;
}
void update_recvframe_phyinfo(struct recv_frame *precvframe,
struct phy_stat *pphy_status)
{
struct rtw_adapter *padapter = precvframe->adapter;
struct rx_pkt_attrib *pattrib = &precvframe->attrib;
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct odm_phy_info *pPHYInfo = (struct odm_phy_info *)(&pattrib->phy_info);
struct odm_packet_info pkt_info;
u8 *sa = NULL, *da;
struct sta_priv *pstapriv;
struct sta_info *psta;
struct sk_buff *skb = precvframe->pkt;
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
u8 *wlanhdr = skb->data;
pkt_info.bPacketMatchBSSID = false;
pkt_info.bPacketToSelf = false;
pkt_info.bPacketBeacon = false;
pkt_info.bPacketMatchBSSID =
(!ieee80211_is_ctl(hdr->frame_control) &&
!pattrib->icv_err &&
!pattrib->crc_err &&
!memcmp(get_hdr_bssid(wlanhdr),
get_bssid(&padapter->mlmepriv), ETH_ALEN));
da = ieee80211_get_DA(hdr);
pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID &&
(!memcmp(da, myid(&padapter->eeprompriv), ETH_ALEN));
pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID &&
ieee80211_is_beacon(hdr->frame_control);
pkt_info.StationID = 0xFF;
if (pkt_info.bPacketBeacon) {
if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == true)
sa = padapter->mlmepriv.cur_network.network.MacAddress;
/* to do Ad-hoc */
} else {
sa = ieee80211_get_SA(hdr);
}
pstapriv = &padapter->stapriv;
psta = rtw_get_stainfo23a(pstapriv, sa);
if (psta) {
pkt_info.StationID = psta->mac_id;
/* printk("%s ==> StationID(%d)\n", __FUNCTION__, pkt_info.StationID); */
}
pkt_info.Rate = pattrib->mcs_rate;
ODM_PhyStatusQuery23a(&pHalData->odmpriv, pPHYInfo,
(u8 *)pphy_status, &pkt_info);
precvframe->psta = NULL;
if (pkt_info.bPacketMatchBSSID &&
(check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true)) {
if (psta) {
precvframe->psta = psta;
rtl8723a_process_phy_info(padapter, precvframe);
}
} else if (pkt_info.bPacketToSelf || pkt_info.bPacketBeacon) {
if (check_fwstate(&padapter->mlmepriv,
WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) ==
true) {
if (psta)
precvframe->psta = psta;
}
rtl8723a_process_phy_info(padapter, precvframe);
}
}

548
drivers/staging/rtl8723au/hal/rtl8723au_xmit.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _RTL8192C_XMIT_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <wifi.h>
#include <osdep_intf.h>
#include <usb_ops.h>
/* include <rtl8192c_hal.h> */
#include <rtl8723a_hal.h>
s32 rtl8723au_init_xmit_priv(struct rtw_adapter *padapter)
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
tasklet_init(&pxmitpriv->xmit_tasklet,
(void(*)(unsigned long))rtl8723au_xmit_tasklet,
(unsigned long)padapter);
return _SUCCESS;
}
void rtl8723au_free_xmit_priv(struct rtw_adapter *padapter)
{
}
static void do_queue_select(struct rtw_adapter *padapter, struct pkt_attrib *pattrib)
{
u8 qsel;
qsel = pattrib->priority;
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_,
("### do_queue_select priority =%d , qsel = %d\n",
pattrib->priority, qsel));
pattrib->qsel = qsel;
}
static int urb_zero_packet_chk(struct rtw_adapter *padapter, int sz)
{
int blnSetTxDescOffset;
struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
if (pdvobj->ishighspeed) {
if (((sz + TXDESC_SIZE) % 512) == 0)
blnSetTxDescOffset = 1;
else
blnSetTxDescOffset = 0;
} else {
if (((sz + TXDESC_SIZE) % 64) == 0)
blnSetTxDescOffset = 1;
else
blnSetTxDescOffset = 0;
}
return blnSetTxDescOffset;
}
static void rtl8192cu_cal_txdesc_chksum(struct tx_desc *ptxdesc)
{
u16 *usPtr = (u16 *)ptxdesc;
u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */
u32 index;
u16 checksum = 0;
/* Clear first */
ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
for (index = 0 ; index < count ; index++)
checksum = checksum ^ le16_to_cpu(*(usPtr + index));
ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff&checksum);
}
static void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc)
{
if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
switch (pattrib->encrypt) {
/* SEC_TYPE */
case _WEP40_:
case _WEP104_:
ptxdesc->txdw1 |= cpu_to_le32((0x01<<22)&0x00c00000);
break;
case _TKIP_:
case _TKIP_WTMIC_:
/* ptxdesc->txdw1 |= cpu_to_le32((0x02<<22)&0x00c00000); */
ptxdesc->txdw1 |= cpu_to_le32((0x01<<22)&0x00c00000);
break;
case _AES_:
ptxdesc->txdw1 |= cpu_to_le32((0x03<<22)&0x00c00000);
break;
case _NO_PRIVACY_:
default:
break;
}
}
}
static void fill_txdesc_vcs(struct pkt_attrib *pattrib, u32 *pdw)
{
/* DBG_8723A("cvs_mode =%d\n", pattrib->vcs_mode); */
switch (pattrib->vcs_mode) {
case RTS_CTS:
*pdw |= cpu_to_le32(BIT(12));
break;
case CTS_TO_SELF:
*pdw |= cpu_to_le32(BIT(11));
break;
case NONE_VCS:
default:
break;
}
if (pattrib->vcs_mode) {
*pdw |= cpu_to_le32(BIT(13));
/* Set RTS BW */
if (pattrib->ht_en) {
*pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(27)) : 0;
if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
*pdw |= cpu_to_le32((0x01<<28)&0x30000000);
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
*pdw |= cpu_to_le32((0x02<<28)&0x30000000);
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
*pdw |= 0;
else
*pdw |= cpu_to_le32((0x03<<28)&0x30000000);
}
}
}
static void fill_txdesc_phy(struct pkt_attrib *pattrib, u32 *pdw)
{
if (pattrib->ht_en) {
*pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(25)) : 0;
if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
*pdw |= cpu_to_le32((0x01<<20)&0x003f0000);
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
*pdw |= cpu_to_le32((0x02<<20)&0x003f0000);
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
*pdw |= 0;
else
*pdw |= cpu_to_le32((0x03<<20)&0x003f0000);
}
}
static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bagg_pkt)
{
int pull = 0;
uint qsel;
struct rtw_adapter *padapter = pxmitframe->padapter;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
int bmcst = is_multicast_ether_addr(pattrib->ra);
if ((!bagg_pkt) && (urb_zero_packet_chk(padapter, sz) == 0)) {
ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ);
pull = 1;
pxmitframe->pkt_offset--;
}
memset(ptxdesc, 0, sizeof(struct tx_desc));
if ((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) {
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x1f);
qsel = (uint)(pattrib->qsel & 0x0000001f);
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<<16) & 0x000f0000);
fill_txdesc_sectype(pattrib, ptxdesc);
if (pattrib->ampdu_en)
ptxdesc->txdw1 |= cpu_to_le32(BIT(5));/* AGG EN */
else
ptxdesc->txdw1 |= cpu_to_le32(BIT(6));/* AGG BK */
/* offset 8 */
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0xffff0000);
/* offset 16 , offset 20 */
if (pattrib->qos_en)
ptxdesc->txdw4 |= cpu_to_le32(BIT(6));/* QoS */
if ((pattrib->ether_type != 0x888e) &&
(pattrib->ether_type != 0x0806) &&
(pattrib->dhcp_pkt != 1)) {
/* Non EAP & ARP & DHCP type data packet */
fill_txdesc_vcs(pattrib, &ptxdesc->txdw4);
fill_txdesc_phy(pattrib, &ptxdesc->txdw4);
ptxdesc->txdw4 |= cpu_to_le32(0x00000008);/* RTS Rate = 24M */
ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* */
/* use REG_INIDATA_RATE_SEL value */
ptxdesc->txdw5 |= cpu_to_le32(pdmpriv->INIDATA_RATE[pattrib->mac_id]);
} else {
/* EAP data packet and ARP packet. */
/* Use the 1M data rate to send the EAP/ARP packet. */
/* This will maybe make the handshake smooth. */
ptxdesc->txdw1 |= cpu_to_le32(BIT(6));/* AGG BK */
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
ptxdesc->txdw4 |= cpu_to_le32(BIT(24));/* DATA_SHORT */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate23a(pmlmeext->tx_rate));
}
} else if ((pxmitframe->frame_tag&0x0f) == MGNT_FRAMETAG) {
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x1f);
qsel = (uint)(pattrib->qsel&0x0000001f);
ptxdesc->txdw1 |= cpu_to_le32((qsel<<QSEL_SHT)&0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<<16) & 0x000f0000);
/* offset 8 */
/* CCX-TXRPT ack for xmit mgmt frames. */
if (pxmitframe->ack_report)
ptxdesc->txdw2 |= cpu_to_le32(BIT(19));
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0xffff0000);
/* offset 16 */
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(BIT(17));/* retry limit enable */
ptxdesc->txdw5 |= cpu_to_le32(0x00180000);/* retry limit = 6 */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate23a(pmlmeext->tx_rate));
} else if ((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG) {
DBG_8723A("pxmitframe->frame_tag == TXAGG_FRAMETAG\n");
} else {
DBG_8723A("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag);
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32((4)&0x1f);/* CAM_ID(MAC_ID) */
ptxdesc->txdw1 |= cpu_to_le32((6<<16) & 0x000f0000);/* raid */
/* offset 8 */
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0xffff0000);
/* offset 16 */
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate23a(pmlmeext->tx_rate));
}
/* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
/* mgnt frame should be controled by Hw because Fw will also send null data */
/* which we cannot control when Fw LPS enable. */
/* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
/* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
/* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
if (!pattrib->qos_en) {
/* Hw set sequence number */
ptxdesc->txdw4 |= cpu_to_le32(BIT(7));
/* set bit3 to 1. */
ptxdesc->txdw3 |= cpu_to_le32((8 << 28));
}
/* offset 0 */
ptxdesc->txdw0 |= cpu_to_le32(sz&0x0000ffff);
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000);/* 32 bytes for TX Desc */
if (bmcst)
ptxdesc->txdw0 |= cpu_to_le32(BIT(24));
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("offset0-txdesc = 0x%x\n", ptxdesc->txdw0));
/* offset 4 */
/* pkt_offset, unit:8 bytes padding */
if (pxmitframe->pkt_offset > 0)
ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
rtl8192cu_cal_txdesc_chksum(ptxdesc);
return pull;
}
static s32 rtw_dump_xframe(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe)
{
s32 ret = _SUCCESS;
s32 inner_ret = _SUCCESS;
int t, sz, w_sz, pull = 0;
u8 *mem_addr;
u32 ff_hwaddr;
struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
(pxmitframe->attrib.ether_type != 0x0806) &&
(pxmitframe->attrib.ether_type != 0x888e) &&
(pxmitframe->attrib.dhcp_pkt != 1))
rtw_issue_addbareq_cmd23a(padapter, pxmitframe);
mem_addr = pxmitframe->buf_addr;
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_dump_xframe()\n"));
for (t = 0; t < pattrib->nr_frags; t++) {
if (inner_ret != _SUCCESS && ret == _SUCCESS)
ret = _FAIL;
if (t != (pattrib->nr_frags - 1)) {
RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_,
("pattrib->nr_frags =%d\n", pattrib->nr_frags));
sz = pxmitpriv->frag_len;
sz = sz - 4 - pattrib->icv_len;
} else {
/* no frag */
sz = pattrib->last_txcmdsz;
}
pull = update_txdesc(pxmitframe, mem_addr, sz, false);
if (pull) {
mem_addr += PACKET_OFFSET_SZ; /* pull txdesc head */
pxmitframe->buf_addr = mem_addr;
w_sz = sz + TXDESC_SIZE;
} else {
w_sz = sz + TXDESC_SIZE + PACKET_OFFSET_SZ;
}
ff_hwaddr = rtw_get_ff_hwaddr23a(pxmitframe);
inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, pxmitbuf);
rtw_count_tx_stats23a(padapter, pxmitframe, sz);
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_,
("rtw_write_port, w_sz =%d\n", w_sz));
mem_addr += w_sz;
mem_addr = PTR_ALIGN(mem_addr, 4);
}
rtw_free_xmitframe23a(pxmitpriv, pxmitframe);
if (ret != _SUCCESS)
rtw23a_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
return ret;
}
s32 rtl8723au_xmitframe_complete(struct rtw_adapter *padapter,
struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
{
struct hw_xmit *phwxmits;
struct xmit_frame *pxmitframe;
int hwentry;
int res = _SUCCESS, xcnt = 0;
phwxmits = pxmitpriv->hwxmits;
hwentry = pxmitpriv->hwxmit_entry;
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("xmitframe_complete()\n"));
if (pxmitbuf == NULL) {
pxmitbuf = rtw_alloc_xmitbuf23a(pxmitpriv);
if (!pxmitbuf)
return false;
}
pxmitframe = rtw_dequeue_xframe23a(pxmitpriv, phwxmits, hwentry);
if (pxmitframe) {
pxmitframe->pxmitbuf = pxmitbuf;
pxmitframe->buf_addr = pxmitbuf->pbuf;
pxmitbuf->priv_data = pxmitframe;
if ((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) {
if (pxmitframe->attrib.priority <= 15)/* TID0~15 */
res = rtw_xmitframe_coalesce23a(padapter, pxmitframe->pkt, pxmitframe);
rtw_os_xmit_complete23a(padapter, pxmitframe);/* always return ndis_packet after rtw_xmitframe_coalesce23a */
}
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("xmitframe_complete(): rtw_dump_xframe\n"));
if (res == _SUCCESS) {
rtw_dump_xframe(padapter, pxmitframe);
} else {
rtw_free_xmitbuf23a(pxmitpriv, pxmitbuf);
rtw_free_xmitframe23a(pxmitpriv, pxmitframe);
}
xcnt++;
} else {
rtw_free_xmitbuf23a(pxmitpriv, pxmitbuf);
return false;
}
return true;
}
static s32 xmitframe_direct(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe)
{
s32 res = _SUCCESS;
res = rtw_xmitframe_coalesce23a(padapter, pxmitframe->pkt, pxmitframe);
if (res == _SUCCESS)
rtw_dump_xframe(padapter, pxmitframe);
return res;
}
/*
* Return
* true dump packet directly
* false enqueue packet
*/
static s32 pre_xmitframe(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe)
{
s32 res;
struct xmit_buf *pxmitbuf = NULL;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
do_queue_select(padapter, pattrib);
spin_lock_bh(&pxmitpriv->lock);
#ifdef CONFIG_8723AU_AP_MODE
if (xmitframe_enqueue_for_sleeping_sta23a(padapter, pxmitframe)) {
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
spin_unlock_bh(&pxmitpriv->lock);
if (pattrib->psta)
psta = pattrib->psta;
else
psta = rtw_get_stainfo23a(pstapriv, pattrib->ra);
if (psta) {
if (psta->sleepq_len > (NR_XMITFRAME>>3))
wakeup_sta_to_xmit23a(padapter, psta);
}
return false;
}
#endif
if (rtw_txframes_sta_ac_pending23a(padapter, pattrib) > 0)
goto enqueue;
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == true)
goto enqueue;
pxmitbuf = rtw_alloc_xmitbuf23a(pxmitpriv);
if (pxmitbuf == NULL)
goto enqueue;
spin_unlock_bh(&pxmitpriv->lock);
pxmitframe->pxmitbuf = pxmitbuf;
pxmitframe->buf_addr = pxmitbuf->pbuf;
pxmitbuf->priv_data = pxmitframe;
if (xmitframe_direct(padapter, pxmitframe) != _SUCCESS) {
rtw_free_xmitbuf23a(pxmitpriv, pxmitbuf);
rtw_free_xmitframe23a(pxmitpriv, pxmitframe);
}
return true;
enqueue:
res = rtw_xmitframe_enqueue23a(padapter, pxmitframe);
spin_unlock_bh(&pxmitpriv->lock);
if (res != _SUCCESS) {
RT_TRACE(_module_xmit_osdep_c_, _drv_err_,
("pre_xmitframe: enqueue xmitframe fail\n"));
rtw_free_xmitframe23a(pxmitpriv, pxmitframe);
/* Trick, make the statistics correct */
pxmitpriv->tx_pkts--;
pxmitpriv->tx_drop++;
return true;
}
return false;
}
s32 rtl8723au_mgnt_xmit(struct rtw_adapter *padapter, struct xmit_frame *pmgntframe)
{
return rtw_dump_xframe(padapter, pmgntframe);
}
/*
* Return
* true dump packet directly ok
* false temporary can't transmit packets to hardware
*/
s32 rtl8723au_hal_xmit(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe)
{
return pre_xmitframe(padapter, pxmitframe);
}
s32 rtl8723au_hal_xmitframe_enqueue(struct rtw_adapter *padapter,
struct xmit_frame *pxmitframe)
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
s32 err;
err = rtw_xmitframe_enqueue23a(padapter, pxmitframe);
if (err != _SUCCESS) {
rtw_free_xmitframe23a(pxmitpriv, pxmitframe);
/* Trick, make the statistics correct */
pxmitpriv->tx_pkts--;
pxmitpriv->tx_drop++;
} else {
tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
}
return err;
}

1834
drivers/staging/rtl8723au/hal/usb_halinit.c Normal file
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File diff suppressed because it is too large Load Diff

848
drivers/staging/rtl8723au/hal/usb_ops_linux.c Normal file
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@ -0,0 +1,848 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#define _HCI_OPS_OS_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <osdep_intf.h>
#include <usb_ops.h>
#include <recv_osdep.h>
#include <rtl8723a_hal.h>
#include <rtl8723a_recv.h>
static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype)
{
struct rtw_adapter *padapter = pintfhdl->padapter ;
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
struct usb_device *udev = pdvobjpriv->pusbdev;
unsigned int pipe;
int status = 0;
u8 reqtype;
u8 *pIo_buf;
int vendorreq_times = 0;
if ((padapter->bSurpriseRemoved) || (padapter->pwrctrlpriv.pnp_bstop_trx)) {
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usbctrl_vendorreq:(padapter->bSurpriseRemoved||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
status = -EPERM;
goto exit;
}
if (len > MAX_VENDOR_REQ_CMD_SIZE) {
DBG_8723A("[%s] Buffer len error , vendor request failed\n", __FUNCTION__);
status = -EINVAL;
goto exit;
}
mutex_lock(&pdvobjpriv->usb_vendor_req_mutex);
/* Acquire IO memory for vendorreq */
pIo_buf = pdvobjpriv->usb_vendor_req_buf;
if (pIo_buf == NULL) {
DBG_8723A("[%s] pIo_buf == NULL \n", __FUNCTION__);
status = -ENOMEM;
goto release_mutex;
}
while (++vendorreq_times <= MAX_USBCTRL_VENDORREQ_TIMES) {
memset(pIo_buf, 0, len);
if (requesttype == 0x01) {
pipe = usb_rcvctrlpipe(udev, 0);/* read_in */
reqtype = REALTEK_USB_VENQT_READ;
} else {
pipe = usb_sndctrlpipe(udev, 0);/* write_out */
reqtype = REALTEK_USB_VENQT_WRITE;
memcpy(pIo_buf, pdata, len);
}
status = rtw_usb_control_msg(udev, pipe, request, reqtype,
value, index, pIo_buf, len,
RTW_USB_CONTROL_MSG_TIMEOUT);
if (status == len) { /* Success this control transfer. */
rtw_reset_continual_urb_error(pdvobjpriv);
if (requesttype == 0x01) {
/* For Control read transfer, we have to copy
* the read data from pIo_buf to pdata.
*/
memcpy(pdata, pIo_buf, len);
}
} else { /* error cases */
DBG_8723A("reg 0x%x, usb %s %u fail, status:%d value ="
" 0x%x, vendorreq_times:%d\n",
value, (requesttype == 0x01) ? "read" : "write",
len, status, *(u32 *)pdata, vendorreq_times);
if (status < 0) {
if (status == (-ESHUTDOWN) || status == -ENODEV) {
padapter->bSurpriseRemoved = true;
} else {
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.Wifi_Error_Status = USB_VEN_REQ_CMD_FAIL;
}
} else { /* status != len && status >= 0 */
if (status > 0) {
if (requesttype == 0x01) {
/* For Control read transfer, we have to copy
* the read data from pIo_buf to pdata.
*/
memcpy(pdata, pIo_buf, len);
}
}
}
if (rtw_inc_and_chk_continual_urb_error(pdvobjpriv)) {
padapter->bSurpriseRemoved = true;
break;
}
}
/* firmware download is checksumed, don't retry */
if ((value >= FW_8723A_START_ADDRESS && value <= FW_8723A_END_ADDRESS) || status == len)
break;
}
release_mutex:
mutex_unlock(&pdvobjpriv->usb_vendor_req_mutex);
exit:
return status;
}
static u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr)
{
u8 request;
u8 requesttype;
u16 wvalue;
u16 index;
u16 len;
u8 data = 0;
request = 0x05;
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 1;
usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
return data;
}
static u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr)
{
u8 request;
u8 requesttype;
u16 wvalue;
u16 index;
u16 len;
u16 data = 0;
request = 0x05;
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 2;
usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
return data;
}
static u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr)
{
u8 request;
u8 requesttype;
u16 wvalue;
u16 index;
u16 len;
u32 data = 0;
request = 0x05;
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 4;
usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
return data;
}
static int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
{
u8 request;
u8 requesttype;
u16 wvalue;
u16 index;
u16 len;
u8 data;
int ret;
request = 0x05;
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 1;
data = val;
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
return ret;
}
static int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
{
u8 request;
u8 requesttype;
u16 wvalue;
u16 index;
u16 len;
u16 data;
int ret;
request = 0x05;
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 2;
data = val;
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
return ret;
}
static int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
{
u8 request;
u8 requesttype;
u16 wvalue;
u16 index;
u16 len;
u32 data;
int ret;
request = 0x05;
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 4;
data = val;
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
return ret;
}
static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata)
{
u8 request;
u8 requesttype;
u16 wvalue;
u16 index;
u16 len;
u8 buf[VENDOR_CMD_MAX_DATA_LEN] = {0};
int ret;
request = 0x05;
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = length;
memcpy(buf, pdata, len);
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, buf, len, requesttype);
return ret;
}
/*
* Description:
* Recognize the interrupt content by reading the interrupt
* register or content and masking interrupt mask (IMR)
* if it is our NIC's interrupt. After recognizing, we may clear
* the all interrupts (ISR).
* Arguments:
* [in] Adapter -
* The adapter context.
* [in] pContent -
* Under PCI interface, this field is ignord.
* Under USB interface, the content is the interrupt
* content pointer.
* Under SDIO interface, this is the interrupt type which
* is Local interrupt or system interrupt.
* [in] ContentLen -
* The length in byte of pContent.
* Return:
* If any interrupt matches the mask (IMR), return true, and
* return false otherwise.
*/
static bool
InterruptRecognized8723AU(struct rtw_adapter *Adapter, void *pContent,
u32 ContentLen)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
u8 *buffer = (u8 *)pContent;
struct reportpwrstate_parm report;
memcpy(&pHalData->IntArray[0], &buffer[USB_INTR_CONTENT_HISR_OFFSET],
4);
pHalData->IntArray[0] &= pHalData->IntrMask[0];
/* For HISR extension. Added by tynli. 2009.10.07. */
memcpy(&pHalData->IntArray[1],
&buffer[USB_INTR_CONTENT_HISRE_OFFSET], 4);
pHalData->IntArray[1] &= pHalData->IntrMask[1];
/* We sholud remove this function later because DDK suggest
* not to executing too many operations in MPISR */
memcpy(&report.state, &buffer[USB_INTR_CPWM_OFFSET], 1);
return ((pHalData->IntArray[0])&pHalData->IntrMask[0]) != 0 ||
((pHalData->IntArray[1])&pHalData->IntrMask[1]) != 0;
}
static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs)
{
int err;
struct rtw_adapter *padapter = (struct rtw_adapter *)purb->context;
if (padapter->bSurpriseRemoved || padapter->bDriverStopped ||
padapter->bReadPortCancel) {
DBG_8723A("%s() RX Warning! bDriverStopped(%d) OR "
"bSurpriseRemoved(%d) bReadPortCancel(%d)\n",
__FUNCTION__, padapter->bDriverStopped,
padapter->bSurpriseRemoved,
padapter->bReadPortCancel);
return;
}
if (purb->status == 0) {
struct c2h_evt_hdr *c2h_evt;
c2h_evt = (struct c2h_evt_hdr *)purb->transfer_buffer;
if (purb->actual_length > USB_INTR_CONTENT_LENGTH) {
DBG_8723A("usb_read_interrupt_complete: purb->actual_"
"length > USB_INTR_CONTENT_LENGTH\n");
goto urb_submit;
}
InterruptRecognized8723AU(padapter, purb->transfer_buffer,
purb->actual_length);
if (c2h_evt_exist(c2h_evt)) {
if (c2h_id_filter_ccx_8723a(c2h_evt->id)) {
/* Handle CCX report here */
handle_txrpt_ccx_8723a(padapter, (void *)(c2h_evt->payload));
/* Replace with special pointer to
trigger c2h_evt_clear23a */
if (rtw_cbuf_push23a(padapter->evtpriv.c2h_queue,
(void *)&padapter->evtpriv) !=
_SUCCESS)
DBG_8723A("%s rtw_cbuf_push23a fail\n",
__func__);
schedule_work(&padapter->evtpriv.c2h_wk);
} else if ((c2h_evt = (struct c2h_evt_hdr *)
kmalloc(16, GFP_ATOMIC))) {
memcpy(c2h_evt, purb->transfer_buffer, 16);
if (rtw_cbuf_push23a(padapter->evtpriv.c2h_queue,
(void *)c2h_evt) != _SUCCESS)
DBG_8723A("%s rtw_cbuf_push23a fail\n",
__func__);
schedule_work(&padapter->evtpriv.c2h_wk);
} else {
/* Error handling for malloc fail */
if (rtw_cbuf_push23a(padapter->evtpriv.c2h_queue,
(void *)NULL) != _SUCCESS)
DBG_8723A("%s rtw_cbuf_push23a fail\n",
__func__);
schedule_work(&padapter->evtpriv.c2h_wk);
}
}
urb_submit:
err = usb_submit_urb(purb, GFP_ATOMIC);
if (err && (err != -EPERM)) {
DBG_8723A("cannot submit interrupt in-token(err = "
"0x%08x), urb_status = %d\n",
err, purb->status);
}
} else {
DBG_8723A("###=> usb_read_interrupt_complete => urb "
"status(%d)\n", purb->status);
switch (purb->status) {
case -EINVAL:
case -EPIPE:
case -ENODEV:
case -ESHUTDOWN:
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port_complete:bSurpriseRemoved ="
"true\n"));
/* Fall Through here */
case -ENOENT:
padapter->bDriverStopped = true;
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port_complete:bDriverStopped ="
"true\n"));
break;
case -EPROTO:
break;
case -EINPROGRESS:
DBG_8723A("ERROR: URB IS IN PROGRESS!/n");
break;
default:
break;
}
}
}
static u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr)
{
int err;
unsigned int pipe;
u32 ret = _SUCCESS;
struct rtw_adapter *adapter = pintfhdl->padapter;
struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter);
struct recv_priv *precvpriv = &adapter->recvpriv;
struct usb_device *pusbd = pdvobj->pusbdev;
/* translate DMA FIFO addr to pipehandle */
pipe = ffaddr2pipehdl23a(pdvobj, addr);
usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe,
precvpriv->int_in_buf, USB_INTR_CONTENT_LENGTH,
usb_read_interrupt_complete, adapter, 1);
err = usb_submit_urb(precvpriv->int_in_urb, GFP_ATOMIC);
if (err && (err != -EPERM)) {
DBG_8723A("cannot submit interrupt in-token(err = 0x%08x),"
"urb_status = %d\n", err,
precvpriv->int_in_urb->status);
ret = _FAIL;
}
return ret;
}
static int recvbuf2recvframe(struct rtw_adapter *padapter, struct sk_buff *pskb)
{
u8 *pbuf;
u8 shift_sz = 0;
u16 pkt_cnt;
u32 pkt_offset, skb_len, alloc_sz;
s32 transfer_len;
struct recv_stat *prxstat;
struct phy_stat *pphy_info = NULL;
struct sk_buff *pkt_copy = NULL;
struct recv_frame *precvframe = NULL;
struct rx_pkt_attrib *pattrib = NULL;
struct recv_priv *precvpriv = &padapter->recvpriv;
struct rtw_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
transfer_len = (s32)pskb->len;
pbuf = pskb->data;
prxstat = (struct recv_stat *)pbuf;
pkt_cnt = (le32_to_cpu(prxstat->rxdw2) >> 16) & 0xff;
do {
RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
("recvbuf2recvframe: rxdesc = offsset 0:0x%08x, "
"4:0x%08x, 8:0x%08x, C:0x%08x\n", prxstat->rxdw0,
prxstat->rxdw1, prxstat->rxdw2, prxstat->rxdw4));
prxstat = (struct recv_stat *)pbuf;
precvframe = rtw_alloc_recvframe23a(pfree_recv_queue);
if (!precvframe) {
RT_TRACE(_module_rtl871x_recv_c_, _drv_err_,
("recvbuf2recvframe: precvframe == NULL\n"));
DBG_8723A("%s()-%d: rtw_alloc_recvframe23a() failed! RX "
"Drop!\n", __FUNCTION__, __LINE__);
goto _exit_recvbuf2recvframe;
}
INIT_LIST_HEAD(&precvframe->list);
update_recvframe_attrib(precvframe, prxstat);
pattrib = &precvframe->attrib;
if (pattrib->crc_err) {
DBG_8723A("%s()-%d: RX Warning! rx CRC ERROR !!\n",
__FUNCTION__, __LINE__);
rtw_free_recvframe23a(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz +
pattrib->shift_sz + pattrib->pkt_len;
if ((pattrib->pkt_len <= 0) || (pkt_offset > transfer_len)) {
RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
("recvbuf2recvframe: pkt_len<= 0\n"));
DBG_8723A("%s()-%d: RX Warning!\n",
__FUNCTION__, __LINE__);
rtw_free_recvframe23a(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
/* Modified by Albert 20101213 */
/* For 8 bytes IP header alignment. */
/* Qos data, wireless lan header length is 26 */
if (pattrib->qos) {
shift_sz = 6;
} else {
shift_sz = 0;
}
skb_len = pattrib->pkt_len;
/* for first fragment packet, driver need allocate
* 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
* modify alloc_sz for recvive crc error packet
* by thomas 2011-06-02 */
if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
/* alloc_sz = 1664; 1664 is 128 alignment. */
if (skb_len <= 1650)
alloc_sz = 1664;
else
alloc_sz = skb_len + 14;
} else {
alloc_sz = skb_len;
/* 6 is for IP header 8 bytes alignment in QoS packet case. */
/* 8 is for skb->data 4 bytes alignment. */
alloc_sz += 14;
}
pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz);
if (pkt_copy) {
pkt_copy->dev = padapter->pnetdev;
precvframe->pkt = pkt_copy;
skb_reserve(pkt_copy, 8 - ((unsigned long)(pkt_copy->data) & 7));/* force pkt_copy->data at 8-byte alignment address */
/*force ip_hdr at 8-byte alignment address according to shift_sz. */
skb_reserve(pkt_copy, shift_sz);
memcpy(pkt_copy->data, (pbuf + pattrib->shift_sz + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len);
skb_put(pkt_copy, skb_len);
} else {
if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
DBG_8723A("recvbuf2recvframe: alloc_skb fail, "
"drop frag frame \n");
rtw_free_recvframe23a(precvframe,
pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
precvframe->pkt = skb_clone(pskb, GFP_ATOMIC);
if (!precvframe->pkt) {
DBG_8723A("recvbuf2recvframe: skb_clone "
"fail\n");
rtw_free_recvframe23a(precvframe,
pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
}
if (pattrib->physt) {
pphy_info = (struct phy_stat *)(pbuf + RXDESC_OFFSET);
update_recvframe_phyinfo(precvframe, pphy_info);
}
if (rtw_recv_entry23a(precvframe) != _SUCCESS)
RT_TRACE(_module_rtl871x_recv_c_, _drv_err_,
("recvbuf2recvframe: rtw_recv_entry23a"
"(precvframe) != _SUCCESS\n"));
pkt_cnt--;
transfer_len -= pkt_offset;
pbuf += pkt_offset;
precvframe = NULL;
pkt_copy = NULL;
if (transfer_len > 0 && pkt_cnt == 0)
pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
} while ((transfer_len > 0) && (pkt_cnt > 0));
_exit_recvbuf2recvframe:
return _SUCCESS;
}
void rtl8723au_recv_tasklet(void *priv)
{
struct sk_buff *pskb;
struct rtw_adapter *padapter = (struct rtw_adapter *)priv;
struct recv_priv *precvpriv = &padapter->recvpriv;
while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue))) {
if ((padapter->bDriverStopped) ||
(padapter->bSurpriseRemoved)) {
DBG_8723A("recv_tasklet => bDriverStopped or "
"bSurpriseRemoved \n");
dev_kfree_skb_any(pskb);
break;
}
recvbuf2recvframe(padapter, pskb);
skb_reset_tail_pointer(pskb);
pskb->len = 0;
skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
}
}
static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
{
struct recv_buf *precvbuf = (struct recv_buf *)purb->context;
struct rtw_adapter *padapter = (struct rtw_adapter *)precvbuf->adapter;
struct recv_priv *precvpriv = &padapter->recvpriv;
struct hal_data_8723a *pHalData;
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port_complete!!!\n"));
precvpriv->rx_pending_cnt--;
if (padapter->bSurpriseRemoved || padapter->bDriverStopped ||
padapter->bReadPortCancel) {
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port_complete:bDriverStopped(%d) OR "
"bSurpriseRemoved(%d)\n", padapter->bDriverStopped,
padapter->bSurpriseRemoved));
DBG_8723A("%s()-%d: RX Warning! bDriverStopped(%d) OR "
"bSurpriseRemoved(%d) bReadPortCancel(%d)\n",
__FUNCTION__, __LINE__, padapter->bDriverStopped,
padapter->bSurpriseRemoved, padapter->bReadPortCancel);
return;
}
if (purb->status == 0) {
if ((purb->actual_length > MAX_RECVBUF_SZ) ||
(purb->actual_length < RXDESC_SIZE)) {
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port_complete: (purb->actual_"
"length > MAX_RECVBUF_SZ) || (purb->actual_"
"length < RXDESC_SIZE)\n"));
rtw_read_port(padapter, precvpriv->ff_hwaddr, 0,
precvbuf);
DBG_8723A("%s()-%d: RX Warning!\n",
__FUNCTION__, __LINE__);
} else {
rtw_reset_continual_urb_error(
adapter_to_dvobj(padapter));
skb_put(precvbuf->pskb, purb->actual_length);
skb_queue_tail(&precvpriv->rx_skb_queue,
precvbuf->pskb);
if (skb_queue_len(&precvpriv->rx_skb_queue) <= 1)
tasklet_schedule(&precvpriv->recv_tasklet);
precvbuf->pskb = NULL;
rtw_read_port(padapter, precvpriv->ff_hwaddr, 0,
precvbuf);
}
} else {
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port_complete : purb->status(%d) != 0 \n",
purb->status));
skb_put(precvbuf->pskb, purb->actual_length);
precvbuf->pskb = NULL;
DBG_8723A("###=> usb_read_port_complete => urb status(%d)\n",
purb->status);
if (rtw_inc_and_chk_continual_urb_error(
adapter_to_dvobj(padapter))) {
padapter->bSurpriseRemoved = true;
}
switch (purb->status) {
case -EINVAL:
case -EPIPE:
case -ENODEV:
case -ESHUTDOWN:
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port_complete:bSurprise"
"Removed = true\n"));
/* Intentional fall through here */
case -ENOENT:
padapter->bDriverStopped = true;
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port_complete:"
"bDriverStopped = true\n"));
break;
case -EPROTO:
case -EOVERFLOW:
pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.Wifi_Error_Status =
USB_READ_PORT_FAIL;
rtw_read_port(padapter, precvpriv->ff_hwaddr,
0, precvbuf);
break;
case -EINPROGRESS:
DBG_8723A("ERROR: URB IS IN PROGRESS!/n");
break;
default:
break;
}
}
}
static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt,
struct recv_buf *precvbuf)
{
int err;
unsigned int pipe;
unsigned long tmpaddr = 0;
unsigned long alignment = 0;
u32 ret = _SUCCESS;
struct urb *purb = NULL;
struct rtw_adapter *adapter = pintfhdl->padapter;
struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter);
struct recv_priv *precvpriv = &adapter->recvpriv;
struct usb_device *pusbd = pdvobj->pusbdev;
if (adapter->bDriverStopped || adapter->bSurpriseRemoved ||
adapter->pwrctrlpriv.pnp_bstop_trx) {
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port:(padapter->bDriverStopped ||"
"padapter->bSurpriseRemoved ||adapter->"
"pwrctrlpriv.pnp_bstop_trx)!!!\n"));
return _FAIL;
}
if (!precvbuf) {
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port:precvbuf == NULL\n"));
return _FAIL;
}
if (!precvbuf->pskb)
precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue);
rtl8723au_init_recvbuf(adapter, precvbuf);
/* re-assign for linux based on skb */
if (!precvbuf->pskb) {
precvbuf->pskb = netdev_alloc_skb(adapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
if (precvbuf->pskb == NULL) {
RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("init_recvbuf(): alloc_skb fail!\n"));
return _FAIL;
}
tmpaddr = (unsigned long)precvbuf->pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
}
precvpriv->rx_pending_cnt++;
purb = precvbuf->purb;
/* translate DMA FIFO addr to pipehandle */
pipe = ffaddr2pipehdl23a(pdvobj, addr);
usb_fill_bulk_urb(purb, pusbd, pipe, precvbuf->pskb->data,
MAX_RECVBUF_SZ, usb_read_port_complete,
precvbuf);/* context is precvbuf */
err = usb_submit_urb(purb, GFP_ATOMIC);
if ((err) && (err != -EPERM)) {
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("cannot submit rx in-token(err = 0x%.8x), URB_STATUS "
"= 0x%.8x", err, purb->status));
DBG_8723A("cannot submit rx in-token(err = 0x%08x), urb_status "
"= %d\n", err, purb->status);
ret = _FAIL;
}
return ret;
}
void rtl8723au_xmit_tasklet(void *priv)
{
int ret = false;
struct rtw_adapter *padapter = (struct rtw_adapter *)priv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (check_fwstate(&padapter->mlmepriv, _FW_UNDER_SURVEY))
return;
while (1) {
if ((padapter->bDriverStopped) ||
(padapter->bSurpriseRemoved) ||
(padapter->bWritePortCancel)) {
DBG_8723A("xmit_tasklet => bDriverStopped or "
"bSurpriseRemoved or bWritePortCancel\n");
break;
}
ret = rtl8723au_xmitframe_complete(padapter, pxmitpriv, NULL);
if (!ret)
break;
}
}
void rtl8723au_set_intf_ops(struct _io_ops *pops)
{
memset((u8 *)pops, 0, sizeof(struct _io_ops));
pops->_read8 = &usb_read8;
pops->_read16 = &usb_read16;
pops->_read32 = &usb_read32;
pops->_read_mem = &usb_read_mem23a;
pops->_read_port = &usb_read_port;
pops->_write8 = &usb_write8;
pops->_write16 = &usb_write16;
pops->_write32 = &usb_write32;
pops->_writeN = &usb_writeN;
pops->_write_mem = &usb_write_mem23a;
pops->_write_port = &usb_write_port23a;
pops->_read_port_cancel = &usb_read_port_cancel23a;
pops->_write_port_cancel = &usb_write_port23a_cancel;
pops->_read_interrupt = &usb_read_interrupt;
}
void rtl8723au_set_hw_type(struct rtw_adapter *padapter)
{
padapter->chip_type = RTL8723A;
padapter->HardwareType = HARDWARE_TYPE_RTL8723AU;
DBG_8723A("CHIP TYPE: RTL8723A\n");
}

230
drivers/staging/rtl8723au/include/Hal8723APhyCfg.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*
******************************************************************************/
#ifndef __INC_HAL8723PHYCFG_H__
#define __INC_HAL8723PHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 /* us */
#define AntennaDiversityValue 0x80
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define MAX_AGGR_NUM 0x0909
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
enum swchnlcmdid {
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
CmdID_WritePortUlong,
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
};
/* 1. Switch channel related */
struct swchnlcmd {
enum swchnlcmdid CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
};
enum HW90_BLOCK {
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, /* Never use this */
};
enum RF_RADIO_PATH {
RF_PATH_A = 0, /* Radio Path A */
RF_PATH_B = 1, /* Radio Path B */
RF_PATH_MAX /* Max RF number 90 support */
};
#define CHANNEL_MAX_NUMBER 14 /* 14 is the max channel number */
#define CHANNEL_GROUP_MAX 3 /* ch1~3, ch4~9, ch10~14 total three groups */
enum WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
};
enum baseband_config_type {
BaseBand_Config_PHY_REG = 0, /* Radio Path A */
BaseBand_Config_AGC_TAB = 1, /* Radio Path B */
};
enum ra_offset_area {
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
};
/* BB/RF related */
enum rf_type_8190p {
RF_TYPE_MIN, /* 0 */
RF_8225 = 1, /* 1 11b/g RF for verification only */
RF_8256 = 2, /* 2 11b/g/n */
RF_8258 = 3, /* 3 11a/b/g/n RF */
RF_6052 = 4, /* 4 11b/g/n RF */
RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */
};
struct bb_reg_define {
u32 rfintfs; /* set software control: */
/* 0x870~0x877[8 bytes] */
u32 rfintfi; /* readback data: */
/* 0x8e0~0x8e7[8 bytes] */
u32 rfintfo; /* output data: */
/* 0x860~0x86f [16 bytes] */
u32 rfintfe; /* output enable: */
/* 0x860~0x86f [16 bytes] */
u32 rf3wireOffset; /* LSSI data: */
/* 0x840~0x84f [16 bytes] */
u32 rfLSSI_Select; /* BB Band Select: */
/* 0x878~0x87f [8 bytes] */
u32 rfTxGainStage; /* Tx gain stage: */
/* 0x80c~0x80f [4 bytes] */
u32 rfHSSIPara1; /* wire parameter control1 : */
/* 0x820~0x823, 0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] */
u32 rfHSSIPara2; /* wire parameter control2 : */
/* 0x824~0x827, 0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
u32 rfSwitchControl; /* Tx Rx antenna control : */
/* 0x858~0x85f [16 bytes] */
u32 rfAGCControl1; /* AGC parameter control1 : */
/* 0xc50~0xc53, 0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
u32 rfAGCControl2; /* AGC parameter control2 : */
/* 0xc54~0xc57, 0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
/* 0xc14~0xc17, 0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : */
/* 0xc10~0xc13, 0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
/* 0xc80~0xc83, 0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
/* 0xc84~0xc87, 0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
/* 0x8a0~0x8af [16 bytes] */
u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
};
struct r_antenna_sel_ofdm {
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
u32 r_ant_non_ht_s1:4;
u32 OFDM_TXSC:2;
u32 Reserved:2;
};
struct r_antenna_sel_cck {
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
};
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Macro Definition---------------------------*/
/*------------------------Export Macro Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
/* */
/* BB and RF register read/write */
/* */
u32 PHY_QueryBBReg(struct rtw_adapter *Adapter, u32 RegAddr,
u32 BitMask);
void PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr,
u32 BitMask, u32 Data);
u32 PHY_QueryRFReg(struct rtw_adapter *Adapter,
enum RF_RADIO_PATH eRFPath, u32 RegAddr,
u32 BitMask);
void PHY_SetRFReg(struct rtw_adapter *Adapter,
enum RF_RADIO_PATH eRFPath, u32 RegAddr,
u32 BitMask, u32 Data);
/* */
/* BB TX Power R/W */
/* */
void PHY_SetTxPowerLevel8723A(struct rtw_adapter *Adapter, u8 channel);
/* */
/* Switch bandwidth for 8723A */
/* */
void PHY_SetBWMode23a8723A(struct rtw_adapter *pAdapter,
enum ht_channel_width ChnlWidth,
unsigned char Offset);
/* */
/* channel switch related funciton */
/* */
void PHY_SwChnl8723A(struct rtw_adapter *pAdapter, u8 channel);
/* Call after initialization */
void ChkFwCmdIoDone(struct rtw_adapter *Adapter);
/* */
/* Modify the value of the hw register when beacon interval be changed. */
/* */
void
rtl8192c_PHY_SetBeaconHwReg(struct rtw_adapter *Adapter, u16 BeaconInterval);
void PHY_SwitchEphyParameter(struct rtw_adapter *Adapter);
void PHY_EnableHostClkReq(struct rtw_adapter *Adapter);
bool
SetAntennaConfig92C(struct rtw_adapter *Adapter, u8 DefaultAnt);
/*--------------------------Exported Function prototype---------------------*/
#define PHY_SetMacReg PHY_SetBBReg
/* MAC/BB/RF HAL config */
int PHY_BBConfig8723A(struct rtw_adapter *Adapter);
int PHY_RFConfig8723A(struct rtw_adapter *Adapter);
s32 PHY_MACConfig8723A(struct rtw_adapter *padapter);
#endif

1078
drivers/staging/rtl8723au/include/Hal8723APhyReg.h Normal file
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150
drivers/staging/rtl8723au/include/Hal8723PwrSeq.h Normal file
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#ifndef __HAL8723PWRSEQ_H__
#define __HAL8723PWRSEQ_H__
/*
Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#include "HalPwrSeqCmd.h"
#include "rtl8723a_spec.h"
#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15
#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15
#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8723A_TRANS_END_STEPS 1
/* format
* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here
*/
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital , 1:isolation*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]= 0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]= 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
#define RTL8723A_TRANS_ACT_TO_CARDEMU \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital , 1:isolation*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
#define RTL8723A_TRANS_CARDEMU_TO_SUS \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723A_TRANS_SUS_TO_CARDEMU \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8723A_TRANS_CARDEMU_TO_PDN \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8723A_TRANS_PDN_TO_CARDEMU \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8723A_TRANS_ACT_TO_LPS \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
#define RTL8723A_TRANS_LPS_TO_ACT \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]= 0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8723A_TRANS_END \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
extern struct wlan_pwr_cfg rtl8723AU_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723AU_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723AU_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723AU_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723AU_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723AU_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723AU_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723AU_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723AU_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
#endif

29
drivers/staging/rtl8723au/include/Hal8723UHWImg_CE.h Normal file
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#ifndef __INC_HAL8723U_FW_IMG_H
#define __INC_HAL8723U_FW_IMG_H
/*Created on 2013/01/14, 15:51*/
/* FW v16 enable usb interrupt */
#define Rtl8723UImgArrayLength 22172
extern u8 Rtl8723UFwImgArray[Rtl8723UImgArrayLength];
#define Rtl8723UBTImgArrayLength 1
extern u8 Rtl8723UFwBTImgArray[Rtl8723UBTImgArrayLength];
#define Rtl8723UUMCBCutImgArrayWithBTLength 24118
#define Rtl8723UUMCBCutImgArrayWithoutBTLength 19200
extern u8 Rtl8723UFwUMCBCutImgArrayWithBT[Rtl8723UUMCBCutImgArrayWithBTLength];
extern u8 Rtl8723UFwUMCBCutImgArrayWithoutBT[Rtl8723UUMCBCutImgArrayWithoutBTLength];
#define Rtl8723SUMCBCutMPImgArrayLength 24174
extern const u8 Rtl8723SFwUMCBCutMPImgArray[Rtl8723SUMCBCutMPImgArrayLength];
#define Rtl8723EBTImgArrayLength 15276
extern u8 Rtl8723EFwBTImgArray[Rtl8723EBTImgArrayLength] ;
#define Rtl8723UPHY_REG_Array_PGLength 336
extern u32 Rtl8723UPHY_REG_Array_PG[Rtl8723UPHY_REG_Array_PGLength];
#define Rtl8723UMACPHY_Array_PGLength 1
extern u32 Rtl8723UMACPHY_Array_PG[Rtl8723UMACPHY_Array_PGLength];
#endif /* ifndef __INC_HAL8723U_FW_IMG_H */

64
drivers/staging/rtl8723au/include/HalDMOutSrc8723A.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*
******************************************************************************/
#ifndef __RTL8723A_ODM_H__
#define __RTL8723A_ODM_H__
/* */
#define RSSI_CCK 0
#define RSSI_OFDM 1
#define RSSI_DEFAULT 2
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
/* */
/* structure and define */
/* */
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/* define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} */
/* */
/* function prototype */
/* */
/* */
/* IQ calibrate */
/* */
void rtl8723a_phy_iq_calibrate(struct rtw_adapter *pAdapter, bool bReCovery);
/* */
/* LC calibrate */
/* */
void rtl8723a_phy_lc_calibrate(struct rtw_adapter *pAdapter);
/* */
/* AP calibrate */
/* */
void rtl8723a_phy_ap_calibrate(struct rtw_adapter *pAdapter, char delta);
void rtl8723a_odm_check_tx_power_tracking(struct rtw_adapter *Adapter);
#endif

44
drivers/staging/rtl8723au/include/HalHWImg8723A_BB.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*
******************************************************************************/
#ifndef __INC_BB_8723A_HW_IMG_H
#define __INC_BB_8723A_HW_IMG_H
/******************************************************************************
* AGC_TAB_1T.TXT
******************************************************************************/
void ODM_ReadAndConfig_AGC_TAB_1T_8723A(struct dm_odm_t *pDM_Odm);
/******************************************************************************
* PHY_REG_1T.TXT
******************************************************************************/
void ODM_ReadAndConfig_PHY_REG_1T_8723A(struct dm_odm_t *pDM_Odm);
/******************************************************************************
* PHY_REG_MP.TXT
******************************************************************************/
void ODM_ReadAndConfig_PHY_REG_MP_8723A(struct dm_odm_t *pDM_Odm);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void ODM_ReadAndConfig_PHY_REG_PG_8723A(struct dm_odm_t *pDM_Odm);
#endif /* end of HWIMG_SUPPORT */

28
drivers/staging/rtl8723au/include/HalHWImg8723A_FW.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*
******************************************************************************/
#ifndef __INC_FW_8723A_HW_IMG_H
#define __INC_FW_8723A_HW_IMG_H
/******************************************************************************
* rtl8723fw_B.TXT
******************************************************************************/
void ODM_ReadFirmware_8723A_rtl8723fw_B(struct dm_odm_t *pDM_Odm,
u8 *pFirmware, u32 *pFirmwareSize);
#endif /* end of HWIMG_SUPPORT */

26
drivers/staging/rtl8723au/include/HalHWImg8723A_MAC.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*
******************************************************************************/
#ifndef __INC_MAC_8723A_HW_IMG_H
#define __INC_MAC_8723A_HW_IMG_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void ODM_ReadAndConfig_MAC_REG_8723A(struct dm_odm_t *pDM_Odm);
#endif /* end of HWIMG_SUPPORT */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __INC_RF_8723A_HW_IMG_H
#define __INC_RF_8723A_HW_IMG_H
/******************************************************************************
* RadioA_1T.TXT
******************************************************************************/
void ODM_ReadAndConfig_RadioA_1T_8723A(struct dm_odm_t *pDM_Odm);
#endif /* end of HWIMG_SUPPORT */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*
******************************************************************************/
#ifndef __HALPWRSEQCMD_H__
#define __HALPWRSEQCMD_H__
#include <drv_types.h>
/*---------------------------------------------*/
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
/* offset: the read register offset */
/* msk: the mask of the read value */
/* value: N/A, left by 0 */
/* note: dirver shall implement this function by read & msk */
#define PWR_CMD_WRITE 0x01
/* offset: the read register offset */
/* msk: the mask of the write bits */
/* value: write value */
/* note: driver shall implement this cmd by read & msk after write */
#define PWR_CMD_POLLING 0x02
/* offset: the read register offset */
/* msk: the mask of the polled value */
/* value: the value to be polled, masked by the msd field. */
/* note: driver shall implement this cmd by */
/* do{ */
/* if( (Read(offset) & msk) == (value & msk) ) */
/* break; */
/* } while(not timeout); */
#define PWR_CMD_DELAY 0x03
/* offset: the value to delay */
/* msk: N/A */
/* value: the unit of delay, 0: us, 1: ms */
#define PWR_CMD_END 0x04
/* offset: N/A */
/* msk: N/A */
/* value: N/A */
/*---------------------------------------------*/
/* 3 The value of base: 4 bits */
/*---------------------------------------------*/
/* define the base address of each block */
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
/*---------------------------------------------*/
/* 3 The value of interface_msk: 4 bits */
/*---------------------------------------------*/
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
/* 3 The value of fab_msk: 4 bits */
/*---------------------------------------------*/
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
/* 3 The value of cut_msk: 8 bits */
/*---------------------------------------------*/
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
enum pwrseq_delay_unit {
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
};
struct wlan_pwr_cfg {
u16 offset;
u8 cut_msk;
u8 fab_msk:4;
u8 interface_msk:4;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 value;
};
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
/* */
/* Prototype of protected function. */
/* */
u8 HalPwrSeqCmdParsing23a(
struct rtw_adapter *padapter,
u8 CutVersion,
u8 FabVersion,
u8 InterfaceType,
struct wlan_pwr_cfg PwrCfgCmd[]);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __HAL_VERSION_DEF_H__
#define __HAL_VERSION_DEF_H__
enum hal_ic_type {
CHIP_8192S = 0,
CHIP_8188C = 1,
CHIP_8192C = 2,
CHIP_8192D = 3,
CHIP_8723A = 4,
CHIP_8188E = 5,
CHIP_8881A = 6,
CHIP_8812A = 7,
CHIP_8821A = 8,
CHIP_8723B = 9,
CHIP_8192E = 10,
};
enum hal_chip_type {
TEST_CHIP = 0,
NORMAL_CHIP = 1,
FPGA = 2,
};
enum hal_cut_version {
A_CUT_VERSION = 0,
B_CUT_VERSION = 1,
C_CUT_VERSION = 2,
D_CUT_VERSION = 3,
E_CUT_VERSION = 4,
F_CUT_VERSION = 5,
G_CUT_VERSION = 6,
};
/* HAL_Manufacturer */
enum hal_vendor {
CHIP_VENDOR_TSMC = 0,
CHIP_VENDOR_UMC = 1,
};
enum hal_rf_type {
RF_TYPE_1T1R = 0,
RF_TYPE_1T2R = 1,
RF_TYPE_2T2R = 2,
RF_TYPE_2T3R = 3,
RF_TYPE_2T4R = 4,
RF_TYPE_3T3R = 5,
RF_TYPE_3T4R = 6,
RF_TYPE_4T4R = 7,
};
struct hal_version {
enum hal_ic_type ICType;
enum hal_chip_type ChipType;
enum hal_cut_version CUTVersion;
enum hal_vendor VendorType;
enum hal_rf_type RFType;
u8 ROMVer;
};
/* Get element */
#define GET_CVID_IC_TYPE(version) ((version).ICType)
#define GET_CVID_CHIP_TYPE(version) ((version).ChipType)
#define GET_CVID_RF_TYPE(version) ((version).RFType)
#define GET_CVID_MANUFACTUER(version) ((version).VendorType)
#define GET_CVID_CUT_VERSION(version) ((version).CUTVersion)
#define GET_CVID_ROM_VERSION(version) (((version).ROMVer) & ROM_VERSION_MASK)
/* Common Macro. -- */
#define IS_81XXC(version) \
(((GET_CVID_IC_TYPE(version) == CHIP_8192C) || \
(GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? true : false)
#define IS_8723_SERIES(version) \
((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? true : false)
#define IS_TEST_CHIP(version) \
((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? true : false)
#define IS_NORMAL_CHIP(version) \
((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? true : false)
#define IS_A_CUT(version) \
((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? true : false)
#define IS_B_CUT(version) \
((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true : false)
#define IS_C_CUT(version) \
((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? true : false)
#define IS_D_CUT(version) \
((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? true : false)
#define IS_E_CUT(version) \
((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? true : false)
#define IS_CHIP_VENDOR_TSMC(version) \
((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? true : false)
#define IS_CHIP_VENDOR_UMC(version) \
((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? true : false)
#define IS_1T1R(version) \
((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? true : false)
#define IS_1T2R(version) \
((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? true : false)
#define IS_2T2R(version) \
((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? true : false)
/* Chip version Macro. -- */
#define IS_92C_SERIAL(version) \
((IS_81XXC(version) && IS_2T2R(version)) ? true : false)
#define IS_81xxC_VENDOR_UMC_A_CUT(version) \
(IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? \
(IS_A_CUT(version) ? true : false) : false) : false)
#define IS_81xxC_VENDOR_UMC_B_CUT(version) \
(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \
(IS_B_CUT(version) ? true : false) : false): false)
#define IS_81xxC_VENDOR_UMC_C_CUT(version) \
(IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? \
(IS_C_CUT(version) ? true : false) : false) : false)
#define IS_8723A_A_CUT(version) \
((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? true : false) : false)
#define IS_8723A_B_CUT(version) \
((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? true : false) : false)
#endif

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drivers/staging/rtl8723au/include/cmd_osdep.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __CMD_OSDEP_H_
#define __CMD_OSDEP_H_
#include <osdep_service.h>
#include <drv_types.h>
int _rtw_init_evt_priv23a(struct evt_priv *pevtpriv);
void _rtw_free_evt_priv23a(struct evt_priv *pevtpriv);
void _rtw_free_cmd_priv23a(struct cmd_priv *pcmdpriv);
int _rtw_enqueue_cmd23a(struct rtw_queue *queue, struct cmd_obj *obj);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/*-----------------------------------------------------------------------------
For type defines and data structure defines
------------------------------------------------------------------------------*/
#ifndef __DRV_TYPES_H__
#define __DRV_TYPES_H__
#include <osdep_service.h>
#include <wlan_bssdef.h>
enum _NIC_VERSION {
RTL8711_NIC,
RTL8712_NIC,
RTL8713_NIC,
RTL8716_NIC
};
#include <rtw_ht.h>
#include <rtw_cmd.h>
#include <wlan_bssdef.h>
#include <rtw_xmit.h>
#include <rtw_recv.h>
#include <hal_intf.h>
#include <hal_com.h>
#include <rtw_qos.h>
#include <rtw_security.h>
#include <rtw_pwrctrl.h>
#include <rtw_io.h>
#include <rtw_eeprom.h>
#include <sta_info.h>
#include <rtw_mlme.h>
#include <rtw_debug.h>
#include <rtw_rf.h>
#include <rtw_event.h>
#include <rtw_led.h>
#include <rtw_mlme_ext.h>
#include <rtw_p2p.h>
#include <rtw_ap.h>
#include "ioctl_cfg80211.h"
#define SPEC_DEV_ID_NONE BIT(0)
#define SPEC_DEV_ID_DISABLE_HT BIT(1)
#define SPEC_DEV_ID_ENABLE_PS BIT(2)
#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3)
#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4)
#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5)
struct specific_device_id {
u32 flags;
u16 idVendor;
u16 idProduct;
};
struct registry_priv {
u8 chip_version;
u8 rfintfs;
struct cfg80211_ssid ssid;
u8 channel;/* ad-hoc support requirement */
u8 wireless_mode;/* A, B, G, auto */
u8 scan_mode;/* active, passive */
u8 preamble;/* long, short, auto */
u8 vrtl_carrier_sense;/* Enable, Disable, Auto */
u8 vcs_type;/* RTS/CTS, CTS-to-self */
u16 rts_thresh;
u16 frag_thresh;
u8 adhoc_tx_pwr;
u8 soft_ap;
u8 power_mgnt;
u8 ips_mode;
u8 smart_ps;
u8 long_retry_lmt;
u8 short_retry_lmt;
u16 busy_thresh;
u8 ack_policy;
u8 software_encrypt;
u8 software_decrypt;
u8 acm_method;
/* UAPSD */
u8 wmm_enable;
u8 uapsd_enable;
struct wlan_bssid_ex dev_network;
u8 ht_enable;
u8 cbw40_enable;
u8 ampdu_enable;/* for tx */
u8 rx_stbc;
u8 ampdu_amsdu;/* A-MPDU Supports A-MSDU is permitted */
u8 lowrate_two_xmit;
u8 rf_config;
u8 low_power;
u8 wifi_spec;/* !turbo_mode */
u8 channel_plan;
#ifdef CONFIG_8723AU_BT_COEXIST
u8 btcoex;
u8 bt_iso;
u8 bt_sco;
u8 bt_ampdu;
#endif
bool bAcceptAddbaReq;
u8 antdiv_cfg;
u8 antdiv_type;
u8 usbss_enable;/* 0:disable,1:enable */
u8 hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */
u8 hwpwrp_detect;/* 0:disable,1:enable */
u8 hw_wps_pbc;/* 0:disable,1:enable */
u8 max_roaming_times; /* max number driver will try to roaming */
u8 enable80211d;
u8 ifname[16];
u8 if2name[16];
u8 notch_filter;
u8 regulatory_tid;
};
#define MAX_CONTINUAL_URB_ERR 4
#define GET_PRIMARY_ADAPTER(padapter) \
(((struct rtw_adapter *)padapter)->dvobj->if1)
enum _IFACE_ID {
IFACE_ID0, /* maping to PRIMARY_ADAPTER */
IFACE_ID1, /* maping to SECONDARY_ADAPTER */
IFACE_ID2,
IFACE_ID3,
IFACE_ID_MAX,
};
struct dvobj_priv {
struct rtw_adapter *if1; /* PRIMARY_ADAPTER */
struct rtw_adapter *if2; /* SECONDARY_ADAPTER */
/* for local/global synchronization */
struct mutex hw_init_mutex;
struct mutex h2c_fwcmd_mutex;
struct mutex setch_mutex;
struct mutex setbw_mutex;
unsigned char oper_channel; /* saved chan info when set chan bw */
unsigned char oper_bwmode;
unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */
struct rtw_adapter *padapters[IFACE_ID_MAX];
u8 iface_nums; /* total number of ifaces used runtime */
/* For 92D, DMDP have 2 interface. */
u8 InterfaceNumber;
u8 NumInterfaces;
/* In /Out Pipe information */
int RtInPipe[2];
int RtOutPipe[3];
u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */
u8 irq_alloc;
/*-------- below is for USB INTERFACE --------*/
u8 nr_endpoint;
u8 ishighspeed;
u8 RtNumInPipes;
u8 RtNumOutPipes;
int ep_num[5]; /* endpoint number */
int RegUsbSS;
struct semaphore usb_suspend_sema;
struct mutex usb_vendor_req_mutex;
u8 *usb_alloc_vendor_req_buf;
u8 *usb_vendor_req_buf;
struct usb_interface *pusbintf;
struct usb_device *pusbdev;
atomic_t continual_urb_error;
/*-------- below is for PCIE INTERFACE --------*/
};
static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
{
/* todo: get interface type from dvobj and the return the dev accordingly */
return &dvobj->pusbintf->dev;
}
enum _IFACE_TYPE {
IFACE_PORT0, /* mapping to port0 for C/D series chips */
IFACE_PORT1, /* mapping to port1 for C/D series chip */
MAX_IFACE_PORT,
};
enum _ADAPTER_TYPE {
PRIMARY_ADAPTER,
SECONDARY_ADAPTER,
MAX_ADAPTER,
};
struct rtw_adapter {
int pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */
int bDongle;/* build-in module or external dongle */
u16 chip_type;
u16 HardwareType;
struct dvobj_priv *dvobj;
struct mlme_priv mlmepriv;
struct mlme_ext_priv mlmeextpriv;
struct cmd_priv cmdpriv;
struct evt_priv evtpriv;
/* struct io_queue *pio_queue; */
struct io_priv iopriv;
struct xmit_priv xmitpriv;
struct recv_priv recvpriv;
struct sta_priv stapriv;
struct security_priv securitypriv;
struct registry_priv registrypriv;
struct pwrctrl_priv pwrctrlpriv;
struct eeprom_priv eeprompriv;
struct led_priv ledpriv;
#ifdef CONFIG_8723AU_AP_MODE
struct hostapd_priv *phostapdpriv;
#endif
struct cfg80211_wifidirect_info cfg80211_wdinfo;
u32 setband;
struct wifidirect_info wdinfo;
#ifdef CONFIG_8723AU_P2P
struct wifi_display_info wfd_info;
#endif /* CONFIG_8723AU_P2P */
void *HalData;
u32 hal_data_sz;
struct hal_ops HalFunc;
s32 bDriverStopped;
s32 bSurpriseRemoved;
s32 bCardDisableWOHSM;
u32 IsrContent;
u32 ImrContent;
u8 EepromAddressSize;
u8 hw_init_completed;
u8 bDriverIsGoingToUnload;
u8 init_adpt_in_progress;
u8 bHaltInProgress;
void *cmdThread;
void *evtThread;
void *xmitThread;
void *recvThread;
void (*intf_start)(struct rtw_adapter *adapter);
void (*intf_stop)(struct rtw_adapter *adapter);
struct net_device *pnetdev;
/* used by rtw_rereg_nd_name related function */
struct rereg_nd_name_data {
struct net_device *old_pnetdev;
char old_ifname[IFNAMSIZ];
u8 old_ips_mode;
u8 old_bRegUseLed;
} rereg_nd_name_priv;
int bup;
struct net_device_stats stats;
struct iw_statistics iwstats;
struct proc_dir_entry *dir_dev;/* for proc directory */
struct wireless_dev *rtw_wdev;
int net_closed;
u8 bFWReady;
u8 bBTFWReady;
u8 bReadPortCancel;
u8 bWritePortCancel;
u8 bRxRSSIDisplay;
/* The driver will show the desired chan nor when this flag is 1. */
u8 bNotifyChannelChange;
#ifdef CONFIG_8723AU_P2P
/* driver will show current P2P status when the application reads it*/
u8 bShowGetP2PState;
#endif
struct rtw_adapter *pbuddy_adapter;
/* extend to support multi interface */
/* IFACE_ID0 is equals to PRIMARY_ADAPTER */
/* IFACE_ID1 is equals to SECONDARY_ADAPTER */
u8 iface_id;
#ifdef CONFIG_BR_EXT
_lock br_ext_lock;
/* unsigned int macclone_completed; */
struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE];
int pppoe_connection_in_progress;
unsigned char pppoe_addr[MACADDRLEN];
unsigned char scdb_mac[MACADDRLEN];
unsigned char scdb_ip[4];
struct nat25_network_db_entry *scdb_entry;
unsigned char br_mac[MACADDRLEN];
unsigned char br_ip[4];
struct br_ext_info ethBrExtInfo;
#endif /* CONFIG_BR_EXT */
u8 fix_rate;
unsigned char in_cta_test;
};
#define adapter_to_dvobj(adapter) (adapter->dvobj)
int rtw_handle_dualmac23a(struct rtw_adapter *adapter, bool init);
static inline u8 *myid(struct eeprom_priv *peepriv)
{
return peepriv->mac_addr;
}
#endif /* __DRV_TYPES_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*
******************************************************************************/
/*! \file */
#ifndef __INC_ETHERNET_H
#define __INC_ETHERNET_H
#define LLC_HEADER_SIZE 6 /* LLC Header Length */
#endif /* #ifndef __INC_ETHERNET_H */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __HAL_COMMON_H__
#define __HAL_COMMON_H__
/* */
/* Rate Definition */
/* */
/* CCK */
#define RATR_1M 0x00000001
#define RATR_2M 0x00000002
#define RATR_55M 0x00000004
#define RATR_11M 0x00000008
/* OFDM */
#define RATR_6M 0x00000010
#define RATR_9M 0x00000020
#define RATR_12M 0x00000040
#define RATR_18M 0x00000080
#define RATR_24M 0x00000100
#define RATR_36M 0x00000200
#define RATR_48M 0x00000400
#define RATR_54M 0x00000800
/* MCS 1 Spatial Stream */
#define RATR_MCS0 0x00001000
#define RATR_MCS1 0x00002000
#define RATR_MCS2 0x00004000
#define RATR_MCS3 0x00008000
#define RATR_MCS4 0x00010000
#define RATR_MCS5 0x00020000
#define RATR_MCS6 0x00040000
#define RATR_MCS7 0x00080000
/* MCS 2 Spatial Stream */
#define RATR_MCS8 0x00100000
#define RATR_MCS9 0x00200000
#define RATR_MCS10 0x00400000
#define RATR_MCS11 0x00800000
#define RATR_MCS12 0x01000000
#define RATR_MCS13 0x02000000
#define RATR_MCS14 0x04000000
#define RATR_MCS15 0x08000000
/* CCK */
#define RATE_1M BIT(0)
#define RATE_2M BIT(1)
#define RATE_5_5M BIT(2)
#define RATE_11M BIT(3)
/* OFDM */
#define RATE_6M BIT(4)
#define RATE_9M BIT(5)
#define RATE_12M BIT(6)
#define RATE_18M BIT(7)
#define RATE_24M BIT(8)
#define RATE_36M BIT(9)
#define RATE_48M BIT(10)
#define RATE_54M BIT(11)
/* MCS 1 Spatial Stream */
#define RATE_MCS0 BIT(12)
#define RATE_MCS1 BIT(13)
#define RATE_MCS2 BIT(14)
#define RATE_MCS3 BIT(15)
#define RATE_MCS4 BIT(16)
#define RATE_MCS5 BIT(17)
#define RATE_MCS6 BIT(18)
#define RATE_MCS7 BIT(19)
/* MCS 2 Spatial Stream */
#define RATE_MCS8 BIT(20)
#define RATE_MCS9 BIT(21)
#define RATE_MCS10 BIT(22)
#define RATE_MCS11 BIT(23)
#define RATE_MCS12 BIT(24)
#define RATE_MCS13 BIT(25)
#define RATE_MCS14 BIT(26)
#define RATE_MCS15 BIT(27)
/* ALL CCK Rate */
#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
#define RATE_ALL_OFDM_AG \
(RATR_6M | RATR_9M | RATR_12M | RATR_18M | RATR_24M| \
RATR_36M|RATR_48M|RATR_54M)
#define RATE_ALL_OFDM_1SS \
(RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | RATR_MCS3 | \
RATR_MCS4 | RATR_MCS5 | RATR_MCS6 | RATR_MCS7)
#define RATE_ALL_OFDM_2SS \
(RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | RATR_MCS11| \
RATR_MCS12 | RATR_MCS13 | RATR_MCS14 | RATR_MCS15)
/*------------------------------ Tx Desc definition Macro ------------------------*/
/* pragma mark -- Tx Desc related definition. -- */
/* */
/* */
/* Rate */
/* */
/* CCK Rates, TxHT = 0 */
#define DESC_RATE1M 0x00
#define DESC_RATE2M 0x01
#define DESC_RATE5_5M 0x02
#define DESC_RATE11M 0x03
/* OFDM Rates, TxHT = 0 */
#define DESC_RATE6M 0x04
#define DESC_RATE9M 0x05
#define DESC_RATE12M 0x06
#define DESC_RATE18M 0x07
#define DESC_RATE24M 0x08
#define DESC_RATE36M 0x09
#define DESC_RATE48M 0x0a
#define DESC_RATE54M 0x0b
/* MCS Rates, TxHT = 1 */
#define DESC_RATEMCS0 0x0c
#define DESC_RATEMCS1 0x0d
#define DESC_RATEMCS2 0x0e
#define DESC_RATEMCS3 0x0f
#define DESC_RATEMCS4 0x10
#define DESC_RATEMCS5 0x11
#define DESC_RATEMCS6 0x12
#define DESC_RATEMCS7 0x13
#define DESC_RATEMCS8 0x14
#define DESC_RATEMCS9 0x15
#define DESC_RATEMCS10 0x16
#define DESC_RATEMCS11 0x17
#define DESC_RATEMCS12 0x18
#define DESC_RATEMCS13 0x19
#define DESC_RATEMCS14 0x1a
#define DESC_RATEMCS15 0x1b
#define DESC_RATEMCS15_SG 0x1c
#define DESC_RATEMCS32 0x20
#define REG_P2P_CTWIN 0x0572 /* 1 Byte long (in unit of TU) */
#define REG_NOA_DESC_SEL 0x05CF
#define REG_NOA_DESC_DURATION 0x05E0
#define REG_NOA_DESC_INTERVAL 0x05E4
#define REG_NOA_DESC_START 0x05E8
#define REG_NOA_DESC_COUNT 0x05EC
#include "HalVerDef.h"
void dump_chip_info23a(struct hal_version ChipVersion);
u8 /* return the final channel plan decision */
hal_com_get_channel_plan23a(
struct rtw_adapter *padapter,
u8 hw_channel_plan, /* channel plan from HW (efuse/eeprom) */
u8 sw_channel_plan, /* channel plan from SW (registry/module param) */
u8 def_channel_plan, /* channel plan used when the former two is invalid */
bool AutoLoadFail
);
u8 MRateToHwRate23a(u8 rate);
void HalSetBrateCfg23a(struct rtw_adapter *padapter, u8 *mBratesOS);
bool
Hal_MappingOutPipe23a(struct rtw_adapter *pAdapter, u8 NumOutPipe);
void hal_init_macaddr23a(struct rtw_adapter *adapter);
void c2h_evt_clear23a(struct rtw_adapter *adapter);
s32 c2h_evt_read23a(struct rtw_adapter *adapter, u8 *buf);
void rtl8723a_set_ampdu_min_space(struct rtw_adapter *padapter, u8 MinSpacingToSet);
void rtl8723a_set_ampdu_factor(struct rtw_adapter *padapter, u8 FactorToSet);
void rtl8723a_set_acm_ctrl(struct rtw_adapter *padapter, u8 ctrl);
void rtl8723a_set_media_status(struct rtw_adapter *padapter, u8 status);
void rtl8723a_set_media_status1(struct rtw_adapter *padapter, u8 status);
void rtl8723a_set_bcn_func(struct rtw_adapter *padapter, u8 val);
void rtl8723a_check_bssid(struct rtw_adapter *padapter, u8 val);
void rtl8723a_mlme_sitesurvey(struct rtw_adapter *padapter, u8 flag);
void rtl8723a_on_rcr_am(struct rtw_adapter *padapter);
void rtl8723a_off_rcr_am(struct rtw_adapter *padapter);
void rtl8723a_set_slot_time(struct rtw_adapter *padapter, u8 slottime);
void rtl8723a_ack_preamble(struct rtw_adapter *padapter, u8 bShortPreamble);
void rtl8723a_set_sec_cfg(struct rtw_adapter *padapter, u8 sec);
void rtl8723a_cam_empty_entry(struct rtw_adapter *padapter, u8 ucIndex);
void rtl8723a_cam_invalid_all(struct rtw_adapter *padapter);
void rtl8723a_cam_write(struct rtw_adapter *padapter, u32 val1, u32 val2);
void rtl8723a_fifo_cleanup(struct rtw_adapter *padapter);
void rtl8723a_set_apfm_on_mac(struct rtw_adapter *padapter, u8 val);
void rtl8723a_bcn_valid(struct rtw_adapter *padapter);
void rtl8723a_set_tx_pause(struct rtw_adapter *padapter, u8 pause);
void rtl8723a_set_beacon_interval(struct rtw_adapter *padapter, u16 interval);
void rtl8723a_set_resp_sifs(struct rtw_adapter *padapter,
u8 r2t1, u8 r2t2, u8 t2t1, u8 t2t2);
void rtl8723a_set_ac_param_vo(struct rtw_adapter *padapter, u32 vo);
void rtl8723a_set_ac_param_vi(struct rtw_adapter *padapter, u32 vi);
void rtl8723a_set_ac_param_be(struct rtw_adapter *padapter, u32 be);
void rtl8723a_set_ac_param_bk(struct rtw_adapter *padapter, u32 bk);
void rtl8723a_set_rxdma_agg_pg_th(struct rtw_adapter *padapter, u8 val);
void rtl8723a_set_nav_upper(struct rtw_adapter *padapter, u32 usNavUpper);
void rtl8723a_set_initial_gain(struct rtw_adapter *padapter, u32 rx_gain);
void rtl8723a_odm_support_ability_write(struct rtw_adapter *padapter, u32 val);
void rtl8723a_odm_support_ability_backup(struct rtw_adapter *padapter, u8 val);
void rtl8723a_odm_support_ability_set(struct rtw_adapter *padapter, u32 val);
void rtl8723a_odm_support_ability_clr(struct rtw_adapter *padapter, u32 val);
void rtl8723a_set_rpwm(struct rtw_adapter *padapter, u8 val);
#endif /* __HAL_COMMON_H__ */

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drivers/staging/rtl8723au/include/hal_intf.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __HAL_INTF_H__
#define __HAL_INTF_H__
#include <osdep_service.h>
#include <drv_types.h>
enum RTL871X_HCI_TYPE {
RTW_PCIE = BIT0,
RTW_USB = BIT1,
RTW_SDIO = BIT2,
RTW_GSPI = BIT3,
};
enum _CHIP_TYPE {
NULL_CHIP_TYPE,
RTL8712_8188S_8191S_8192S,
RTL8188C_8192C,
RTL8192D,
RTL8723A,
RTL8188E,
MAX_CHIP_TYPE
};
enum HW_VARIABLES {
HW_VAR_MEDIA_STATUS,
HW_VAR_MEDIA_STATUS1,
HW_VAR_SET_OPMODE,
HW_VAR_MAC_ADDR,
HW_VAR_BSSID,
HW_VAR_INIT_RTS_RATE,
HW_VAR_BASIC_RATE,
HW_VAR_TXPAUSE,
HW_VAR_BCN_FUNC,
HW_VAR_CORRECT_TSF,
HW_VAR_CHECK_BSSID,
HW_VAR_MLME_DISCONNECT,
HW_VAR_MLME_SITESURVEY,
HW_VAR_MLME_JOIN,
HW_VAR_ON_RCR_AM,
HW_VAR_OFF_RCR_AM,
HW_VAR_BEACON_INTERVAL,
HW_VAR_SLOT_TIME,
HW_VAR_RESP_SIFS,
HW_VAR_ACK_PREAMBLE,
HW_VAR_SEC_CFG,
HW_VAR_BCN_VALID,
HW_VAR_RF_TYPE,
HW_VAR_DM_FLAG,
HW_VAR_DM_FUNC_OP,
HW_VAR_DM_FUNC_SET,
HW_VAR_DM_FUNC_CLR,
HW_VAR_CAM_EMPTY_ENTRY,
HW_VAR_CAM_INVALID_ALL,
HW_VAR_CAM_WRITE,
HW_VAR_CAM_READ,
HW_VAR_AC_PARAM_VO,
HW_VAR_AC_PARAM_VI,
HW_VAR_AC_PARAM_BE,
HW_VAR_AC_PARAM_BK,
HW_VAR_ACM_CTRL,
HW_VAR_AMPDU_MIN_SPACE,
HW_VAR_AMPDU_FACTOR,
HW_VAR_RXDMA_AGG_PG_TH,
HW_VAR_SET_RPWM,
HW_VAR_H2C_FW_PWRMODE,
HW_VAR_H2C_FW_JOINBSSRPT,
HW_VAR_FWLPS_RF_ON,
HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
HW_VAR_TDLS_WRCR,
HW_VAR_TDLS_INIT_CH_SEN,
HW_VAR_TDLS_RS_RCR,
HW_VAR_TDLS_DONE_CH_SEN,
HW_VAR_INITIAL_GAIN,
HW_VAR_TRIGGER_GPIO_0,
HW_VAR_BT_SET_COEXIST,
HW_VAR_BT_ISSUE_DELBA,
HW_VAR_CURRENT_ANTENNA,
HW_VAR_ANTENNA_DIVERSITY_LINK,
HW_VAR_ANTENNA_DIVERSITY_SELECT,
HW_VAR_SWITCH_EPHY_WoWLAN,
HW_VAR_EFUSE_BYTES,
HW_VAR_EFUSE_BT_BYTES,
HW_VAR_FIFO_CLEARN_UP,
HW_VAR_CHECK_TXBUF,
HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
/* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */
/* Unit in microsecond. 0 means disable this function. */
HW_VAR_NAV_UPPER,
HW_VAR_RPT_TIMER_SETTING,
HW_VAR_TX_RPT_MAX_MACID,
HW_VAR_H2C_MEDIA_STATUS_RPT,
HW_VAR_CHK_HI_QUEUE_EMPTY,
HW_VAR_READ_LLT_TAB,
};
enum hal_def_variable {
HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
HAL_DEF_IS_SUPPORT_ANT_DIV,
HAL_DEF_CURRENT_ANTENNA,
HAL_DEF_DRVINFO_SZ,
HAL_DEF_MAX_RECVBUF_SZ,
HAL_DEF_RX_PACKET_OFFSET,
HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */
HAL_DEF_DBG_DM_FUNC,/* for dbg */
HAL_DEF_RA_DECISION_RATE,
HAL_DEF_RA_SGI,
HAL_DEF_PT_PWR_STATUS,
HW_VAR_MAX_RX_AMPDU_FACTOR,
HW_DEF_RA_INFO_DUMP,
HAL_DEF_DBG_DUMP_TXPKT,
HW_DEF_FA_CNT_DUMP,
HW_DEF_ODM_DBG_FLAG,
};
enum hal_odm_variable {
HAL_ODM_STA_INFO,
HAL_ODM_P2P_STATE,
HAL_ODM_WIFI_DISPLAY_STATE,
};
enum hal_intf_ps_func {
HAL_USB_SELECT_SUSPEND,
HAL_MAX_ID,
};
struct hal_ops {
u32 (*hal_power_on)(struct rtw_adapter *padapter);
u32 (*hal_init)(struct rtw_adapter *padapter);
u32 (*hal_deinit)(struct rtw_adapter *padapter);
void (*free_hal_data)(struct rtw_adapter *padapter);
u32 (*inirp_init)(struct rtw_adapter *padapter);
u32 (*inirp_deinit)(struct rtw_adapter *padapter);
s32 (*init_xmit_priv)(struct rtw_adapter *padapter);
void (*free_xmit_priv)(struct rtw_adapter *padapter);
s32 (*init_recv_priv)(struct rtw_adapter *padapter);
void (*free_recv_priv)(struct rtw_adapter *padapter);
void (*InitSwLeds)(struct rtw_adapter *padapter);
void (*DeInitSwLeds)(struct rtw_adapter *padapter);
void (*dm_init)(struct rtw_adapter *padapter);
void (*dm_deinit)(struct rtw_adapter *padapter);
void (*read_chip_version)(struct rtw_adapter *padapter);
void (*init_default_value)(struct rtw_adapter *padapter);
void (*intf_chip_configure)(struct rtw_adapter *padapter);
void (*read_adapter_info)(struct rtw_adapter *padapter);
void (*enable_interrupt)(struct rtw_adapter *padapter);
void (*disable_interrupt)(struct rtw_adapter *padapter);
s32 (*interrupt_handler)(struct rtw_adapter *padapter);
void (*set_bwmode_handler)(struct rtw_adapter *padapter,
enum ht_channel_width Bandwidth, u8 Offset);
void (*set_channel_handler)(struct rtw_adapter *padapter, u8 channel);
void (*hal_dm_watchdog)(struct rtw_adapter *padapter);
void (*SetHwRegHandler)(struct rtw_adapter *padapter,
u8 variable, u8 *val);
void (*GetHwRegHandler)(struct rtw_adapter *padapter,
u8 variable, u8 *val);
u8 (*GetHalDefVarHandler)(struct rtw_adapter *padapter,
enum hal_def_variable eVariable,
void *pValue);
u8 (*SetHalDefVarHandler)(struct rtw_adapter *padapter,
enum hal_def_variable eVariable,
void *pValue);
void (*GetHalODMVarHandler)(struct rtw_adapter *padapter,
enum hal_odm_variable eVariable,
void *pValue1, bool bSet);
void (*SetHalODMVarHandler)(struct rtw_adapter *padapter,
enum hal_odm_variable eVariable,
void *pValue1, bool bSet);
void (*UpdateRAMaskHandler)(struct rtw_adapter *padapter,
u32 mac_id, u8 rssi_level);
void (*SetBeaconRelatedRegistersHandler)(struct rtw_adapter *padapter);
void (*Add_RateATid)(struct rtw_adapter *padapter, u32 bitmap,
u8 arg, u8 rssi_level);
void (*run_thread)(struct rtw_adapter *padapter);
void (*cancel_thread)(struct rtw_adapter *padapter);
u8 (*interface_ps_func)(struct rtw_adapter *padapter,
enum hal_intf_ps_func efunc_id, u8 *val);
s32 (*hal_xmit)(struct rtw_adapter *padapter,
struct xmit_frame *pxmitframe);
s32 (*mgnt_xmit)(struct rtw_adapter *padapter,
struct xmit_frame *pmgntframe);
s32 (*hal_xmitframe_enqueue)(struct rtw_adapter *padapter,
struct xmit_frame *pxmitframe);
u32 (*read_bbreg)(struct rtw_adapter *padapter, u32 RegAddr,
u32 BitMask);
void (*write_bbreg)(struct rtw_adapter *padapter, u32 RegAddr,
u32 BitMask, u32 Data);
u32 (*read_rfreg)(struct rtw_adapter *padapter, u32 eRFPath,
u32 RegAddr, u32 BitMask);
void (*write_rfreg)(struct rtw_adapter *padapter, u32 eRFPath,
u32 RegAddr, u32 BitMask, u32 Data);
void (*EfusePowerSwitch)(struct rtw_adapter *padapter, u8 bWrite,
u8 PwrState);
void (*ReadEFuse)(struct rtw_adapter *padapter, u8 efuseType,
u16 _offset, u16 _size_byte, u8 *pbuf);
void (*EFUSEGetEfuseDefinition)(struct rtw_adapter *padapter,
u8 efuseType, u8 type, void *pOut);
u16 (*EfuseGetCurrentSize)(struct rtw_adapter *padapter, u8 efuseType);
int (*Efuse_PgPacketRead23a)(struct rtw_adapter *padapter,
u8 offset, u8 *data);
int (*Efuse_PgPacketWrite23a)(struct rtw_adapter *padapter,
u8 offset, u8 word_en, u8 *data);
u8 (*Efuse_WordEnableDataWrite23a)(struct rtw_adapter *padapter,
u16 efuse_addr, u8 word_en,
u8 *data);
bool (*Efuse_PgPacketWrite23a_BT)(struct rtw_adapter *padapter,
u8 offset, u8 word_en, u8 *data);
void (*sreset_init_value23a)(struct rtw_adapter *padapter);
void (*sreset_reset_value23a)(struct rtw_adapter *padapter);
void (*silentreset)(struct rtw_adapter *padapter);
void (*sreset_xmit_status_check)(struct rtw_adapter *padapter);
void (*sreset_linked_status_check) (struct rtw_adapter *padapter);
u8 (*sreset_get_wifi_status23a)(struct rtw_adapter *padapter);
bool (*sreset_inprogress)(struct rtw_adapter *padapter);
void (*hal_notch_filter)(struct rtw_adapter *adapter, bool enable);
void (*hal_reset_security_engine)(struct rtw_adapter *adapter);
s32 (*c2h_handler)(struct rtw_adapter *padapter, struct c2h_evt_hdr *c2h_evt);
c2h_id_filter c2h_id_filter_ccx;
};
enum rt_eeprom_type {
EEPROM_93C46,
EEPROM_93C56,
EEPROM_BOOT_EFUSE,
};
#define RF_CHANGE_BY_INIT 0
#define RF_CHANGE_BY_IPS BIT28
#define RF_CHANGE_BY_PS BIT29
#define RF_CHANGE_BY_HW BIT30
#define RF_CHANGE_BY_SW BIT31
enum hardware_type {
HARDWARE_TYPE_RTL8180,
HARDWARE_TYPE_RTL8185,
HARDWARE_TYPE_RTL8187,
HARDWARE_TYPE_RTL8188,
HARDWARE_TYPE_RTL8190P,
HARDWARE_TYPE_RTL8192E,
HARDWARE_TYPE_RTL819xU,
HARDWARE_TYPE_RTL8192SE,
HARDWARE_TYPE_RTL8192SU,
HARDWARE_TYPE_RTL8192CE,
HARDWARE_TYPE_RTL8192CU,
HARDWARE_TYPE_RTL8192DE,
HARDWARE_TYPE_RTL8192DU,
HARDWARE_TYPE_RTL8723AE,
HARDWARE_TYPE_RTL8723AU,
HARDWARE_TYPE_RTL8723AS,
HARDWARE_TYPE_RTL8188EE,
HARDWARE_TYPE_RTL8188EU,
HARDWARE_TYPE_RTL8188ES,
HARDWARE_TYPE_MAX,
};
#define GET_EEPROM_EFUSE_PRIV(adapter) (&adapter->eeprompriv)
#define is_boot_from_eeprom(adapter) (adapter->eeprompriv.EepromOrEfuse)
extern int rtw_ht_enable23A;
extern int rtw_cbw40_enable23A;
extern int rtw_ampdu_enable23A;/* for enable tx_ampdu */
void rtw_hal_def_value_init23a(struct rtw_adapter *padapter);
int pm_netdev_open23a(struct net_device *pnetdev, u8 bnormal);
int rtw_resume_process23a(struct rtw_adapter *padapter);
void rtw_hal_free_data23a(struct rtw_adapter *padapter);
void rtw_hal_dm_init23a(struct rtw_adapter *padapter);
void rtw_hal_dm_deinit23a(struct rtw_adapter *padapter);
void rtw_hal_sw_led_init23a(struct rtw_adapter *padapter);
void rtw_hal_sw_led_deinit23a(struct rtw_adapter *padapter);
u32 rtw_hal_power_on23a(struct rtw_adapter *padapter);
uint rtw_hal_init23a(struct rtw_adapter *padapter);
uint rtw_hal_deinit23a(struct rtw_adapter *padapter);
void rtw_hal_stop(struct rtw_adapter *padapter);
void rtw_hal_set_hwreg23a(struct rtw_adapter *padapter, u8 variable, u8 *val);
void rtw23a_hal_get_hwreg(struct rtw_adapter *padapter, u8 variable, u8 *val);
void rtw_hal_chip_configure23a(struct rtw_adapter *padapter);
void rtw_hal_read_chip_info23a(struct rtw_adapter *padapter);
void rtw_hal_read_chip_version23a(struct rtw_adapter *padapter);
u8 rtw_hal_set_def_var23a(struct rtw_adapter *padapter,
enum hal_def_variable eVariable,
void *pValue);
u8 rtw_hal_get_def_var23a(struct rtw_adapter *padapter,
enum hal_def_variable eVariable,
void *pValue);
void rtw_hal_set_odm_var23a(struct rtw_adapter *padapter,
enum hal_odm_variable eVariable,
void *pValue1, bool bSet);
void rtw_hal_get_odm_var23a(struct rtw_adapter *padapter,
enum hal_odm_variable eVariable,
void *pValue1, bool bSet);
void rtw_hal_enable_interrupt23a(struct rtw_adapter *padapter);
void rtw_hal_disable_interrupt23a(struct rtw_adapter *padapter);
u32 rtw_hal_inirp_init23a(struct rtw_adapter *padapter);
u32 rtw_hal_inirp_deinit23a(struct rtw_adapter *padapter);
u8 rtw_hal_intf_ps_func23a(struct rtw_adapter *padapter,
enum hal_intf_ps_func efunc_id, u8 *val);
s32 rtw_hal_xmit23aframe_enqueue(struct rtw_adapter *padapter,
struct xmit_frame *pxmitframe);
s32 rtw_hal_xmit23a(struct rtw_adapter *padapter,
struct xmit_frame *pxmitframe);
s32 rtw_hal_mgnt_xmit23a(struct rtw_adapter *padapter,
struct xmit_frame *pmgntframe);
s32 rtw_hal_init23a_xmit_priv(struct rtw_adapter *padapter);
void rtw_hal_free_xmit_priv23a(struct rtw_adapter *padapter);
s32 rtw_hal_init23a_recv_priv(struct rtw_adapter *padapter);
void rtw_hal_free_recv_priv23a(struct rtw_adapter *padapter);
void rtw_hal_update_ra_mask23a(struct sta_info *psta, u8 rssi_level);
void rtw_hal_add_ra_tid23a(struct rtw_adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level);
void rtw_hal_clone_data(struct rtw_adapter *dst_padapter, struct rtw_adapter *src_padapter);
void rtw_hal_start_thread23a(struct rtw_adapter *padapter);
void rtw_hal_stop_thread23a(struct rtw_adapter *padapter);
void rtw_hal_bcn_related_reg_setting23a(struct rtw_adapter *padapter);
u32 rtw_hal_read_bbreg23a(struct rtw_adapter *padapter, u32 RegAddr, u32 BitMask);
void rtw_hal_write_bbreg23a(struct rtw_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
u32 rtw_hal_read_rfreg23a(struct rtw_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask);
void rtw_hal_write_rfreg23a(struct rtw_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
s32 rtw_hal_interrupt_handler23a(struct rtw_adapter *padapter);
void rtw_hal_set_bwmode23a(struct rtw_adapter *padapter,
enum ht_channel_width Bandwidth, u8 Offset);
void rtw_hal_set_chan23a(struct rtw_adapter *padapter, u8 channel);
void rtw_hal_dm_watchdog23a(struct rtw_adapter *padapter);
void rtw_hal_sreset_init23a(struct rtw_adapter *padapter);
void rtw_hal_sreset_reset23a(struct rtw_adapter *padapter);
void rtw_hal_sreset_reset23a_value23a(struct rtw_adapter *padapter);
void rtw_hal_sreset_xmit_status_check23a(struct rtw_adapter *padapter);
void rtw_hal_sreset_linked_status_check23a (struct rtw_adapter *padapter);
u8 rtw_hal_sreset_get_wifi_status23a(struct rtw_adapter *padapter);
bool rtw_hal_sreset_inprogress(struct rtw_adapter *padapter);
void rtw_hal_notch_filter23a(struct rtw_adapter *adapter, bool enable);
void rtw_hal_reset_security_engine23a(struct rtw_adapter *adapter);
s32 rtw_hal_c2h_handler23a(struct rtw_adapter *adapter, struct c2h_evt_hdr *c2h_evt);
c2h_id_filter rtw_hal_c2h_id_filter_ccx23a(struct rtw_adapter *adapter);
#endif /* __HAL_INTF_H__ */

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drivers/staging/rtl8723au/include/ieee80211.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __IEEE80211_H
#define __IEEE80211_H
#include <osdep_service.h>
#include <drv_types.h>
#include "linux/ieee80211.h"
#include "wifi.h"
#include <linux/wireless.h>
#if (WIRELESS_EXT < 22)
#error "Obsolete pre 2007 wireless extensions are not supported"
#endif
#define MGMT_QUEUE_NUM 5
#ifdef CONFIG_8723AU_AP_MODE
/* STA flags */
#define WLAN_STA_AUTH BIT(0)
#define WLAN_STA_ASSOC BIT(1)
#define WLAN_STA_PS BIT(2)
#define WLAN_STA_TIM BIT(3)
#define WLAN_STA_PERM BIT(4)
#define WLAN_STA_AUTHORIZED BIT(5)
#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */
#define WLAN_STA_SHORT_PREAMBLE BIT(7)
#define WLAN_STA_PREAUTH BIT(8)
#define WLAN_STA_WME BIT(9)
#define WLAN_STA_MFP BIT(10)
#define WLAN_STA_HT BIT(11)
#define WLAN_STA_WPS BIT(12)
#define WLAN_STA_MAYBE_WPS BIT(13)
#define WLAN_STA_NONERP BIT(31)
#endif
#define IEEE_CMD_SET_WPA_PARAM 1
#define IEEE_CMD_SET_WPA_IE 2
#define IEEE_CMD_SET_ENCRYPTION 3
#define IEEE_CRYPT_ALG_NAME_LEN 16
#define WPA_CIPHER_NONE BIT(0)
#define WPA_CIPHER_WEP40 BIT(1)
#define WPA_CIPHER_WEP104 BIT(2)
#define WPA_CIPHER_TKIP BIT(3)
#define WPA_CIPHER_CCMP BIT(4)
#define WPA_SELECTOR_LEN 4
extern u8 RTW_WPA_OUI23A_TYPE[] ;
extern u16 RTW_WPA_VERSION23A ;
extern u8 WPA_AUTH_KEY_MGMT_NONE23A[];
extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X23A[];
extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X23A[];
extern u8 WPA_CIPHER_SUITE_NONE23A[];
extern u8 WPA_CIPHER_SUITE_WEP4023A[];
extern u8 WPA_CIPHER_SUITE_TKIP23A[];
extern u8 WPA_CIPHER_SUITE_WRAP23A[];
extern u8 WPA_CIPHER_SUITE_CCMP23A[];
extern u8 WPA_CIPHER_SUITE_WEP10423A[];
#define RSN_HEADER_LEN 4
#define RSN_SELECTOR_LEN 4
extern u16 RSN_VERSION_BSD23A;
extern u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X23A[];
extern u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X23A[];
extern u8 RSN_CIPHER_SUITE_NONE23A[];
extern u8 RSN_CIPHER_SUITE_WEP4023A[];
extern u8 RSN_CIPHER_SUITE_TKIP23A[];
extern u8 RSN_CIPHER_SUITE_WRAP23A[];
extern u8 RSN_CIPHER_SUITE_CCMP23A[];
extern u8 RSN_CIPHER_SUITE_WEP10423A[];
enum ratr_table_mode {
RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */
RATR_INX_WIRELESS_NG = 1, /* GN or N */
RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */
RATR_INX_WIRELESS_N = 3,
RATR_INX_WIRELESS_GB = 4,
RATR_INX_WIRELESS_G = 5,
RATR_INX_WIRELESS_B = 6,
RATR_INX_WIRELESS_MC = 7,
RATR_INX_WIRELESS_AC_N = 8,
};
enum NETWORK_TYPE
{
WIRELESS_INVALID = 0,
/* Sub-Element */
WIRELESS_11B = BIT(0), /* tx: cck only , rx: cck only, hw: cck */
WIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */
WIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */
WIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */
WIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */
/* WIRELESS_AUTO = BIT(5), */
WIRELESS_AC = BIT(6),
/* Combination */
WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */
WIRELESS_11G_24N = (WIRELESS_11G|WIRELESS_11_24N), /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */
WIRELESS_11A_5N = (WIRELESS_11A|WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
WIRELESS_11BG_24N = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */
WIRELESS_11AGN = (WIRELESS_11A|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N),
};
#define SUPPORTED_24G_NETTYPE_MSK (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N)
#define SUPPORTED_5G_NETTYPE_MSK (WIRELESS_11A | WIRELESS_11_5N)
#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? true : false)
#define IsSupported5G(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? true : false)
#define IsEnableHWCCK(NetType) IsSupported24G(NetType)
#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11_24N|SUPPORTED_5G_NETTYPE_MSK) ? true : false)
#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType)
#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType)
#define IsSupportedRxMCS(NetType) IsEnableHWOFDM(NetType)
#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? true : false)
#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11A) ? true : false)
#define IsSupportedTxMCS(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? true : false)
struct ieee_param {
u32 cmd;
u8 sta_addr[ETH_ALEN];
union {
struct {
u8 name;
u32 value;
} wpa_param;
struct {
u32 len;
u8 reserved[32];
u8 data[0];
} wpa_ie;
struct{
int command;
int reason_code;
} mlme;
struct {
u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
u8 set_tx;
u32 err;
u8 idx;
u8 seq[8]; /* sequence counter (set: RX, get: TX) */
u16 key_len;
u8 key[0];
} crypt;
#ifdef CONFIG_8723AU_AP_MODE
struct {
u16 aid;
u16 capability;
int flags;
u8 tx_supp_rates[16];
struct ieee80211_ht_cap ht_cap;
} add_sta;
struct {
u8 reserved[2];/* for set max_num_sta */
u8 buf[0];
} bcn_ie;
#endif
} u;
};
#define MIN_FRAG_THRESHOLD 256U
#define MAX_FRAG_THRESHOLD 2346U
/* QoS,QOS */
#define NORMAL_ACK 0
#define NO_ACK 1
#define NON_EXPLICIT_ACK 2
#define BLOCK_ACK 3
/* IEEE 802.11 defines */
#define P80211_OUI_LEN 3
struct ieee80211_snap_hdr {
u8 dsap; /* always 0xAA */
u8 ssap; /* always 0xAA */
u8 ctrl; /* always 0x03 */
u8 oui[P80211_OUI_LEN]; /* organizational universal id */
} __attribute__ ((packed));
#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f)
#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG)
#define WLAN_GET_SEQ_SEQ(seq) ((seq) & RTW_IEEE80211_SCTL_SEQ)
#define WLAN_REASON_JOIN_WRONG_CHANNEL 65534
#define WLAN_REASON_EXPIRATION_CHK 65535
#define IEEE80211_STATMASK_SIGNAL (1<<0)
#define IEEE80211_STATMASK_RSSI (1<<1)
#define IEEE80211_STATMASK_NOISE (1<<2)
#define IEEE80211_STATMASK_RATE (1<<3)
#define IEEE80211_STATMASK_WEMASK 0x7
#define IEEE80211_CCK_MODULATION (1<<0)
#define IEEE80211_OFDM_MODULATION (1<<1)
#define IEEE80211_24GHZ_BAND (1<<0)
#define IEEE80211_52GHZ_BAND (1<<1)
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_NUM_OFDM_RATESLEN 8
#define IEEE80211_CCK_RATE_1MB 0x02
#define IEEE80211_CCK_RATE_2MB 0x04
#define IEEE80211_CCK_RATE_5MB 0x0B
#define IEEE80211_CCK_RATE_11MB 0x16
#define IEEE80211_OFDM_RATE_LEN 8
#define IEEE80211_OFDM_RATE_6MB 0x0C
#define IEEE80211_OFDM_RATE_9MB 0x12
#define IEEE80211_OFDM_RATE_12MB 0x18
#define IEEE80211_OFDM_RATE_18MB 0x24
#define IEEE80211_OFDM_RATE_24MB 0x30
#define IEEE80211_OFDM_RATE_36MB 0x48
#define IEEE80211_OFDM_RATE_48MB 0x60
#define IEEE80211_OFDM_RATE_54MB 0x6C
#define IEEE80211_BASIC_RATE_MASK 0x80
#define IEEE80211_CCK_RATE_1MB_MASK (1<<0)
#define IEEE80211_CCK_RATE_2MB_MASK (1<<1)
#define IEEE80211_CCK_RATE_5MB_MASK (1<<2)
#define IEEE80211_CCK_RATE_11MB_MASK (1<<3)
#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4)
#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5)
#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6)
#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7)
#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8)
#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9)
#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10)
#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11)
#define IEEE80211_CCK_RATES_MASK 0x0000000F
#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \
IEEE80211_CCK_RATE_2MB_MASK)
#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \
IEEE80211_CCK_RATE_5MB_MASK | \
IEEE80211_CCK_RATE_11MB_MASK)
#define IEEE80211_OFDM_RATES_MASK 0x00000FF0
#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \
IEEE80211_OFDM_RATE_12MB_MASK | \
IEEE80211_OFDM_RATE_24MB_MASK)
#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \
IEEE80211_OFDM_RATE_9MB_MASK | \
IEEE80211_OFDM_RATE_18MB_MASK | \
IEEE80211_OFDM_RATE_36MB_MASK | \
IEEE80211_OFDM_RATE_48MB_MASK | \
IEEE80211_OFDM_RATE_54MB_MASK)
#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \
IEEE80211_CCK_DEFAULT_RATES_MASK)
#define IEEE80211_NUM_OFDM_RATES 8
#define IEEE80211_NUM_CCK_RATES 4
#define IEEE80211_OFDM_SHIFT_MASK_A 4
#define WEP_KEYS 4
#define WEP_KEY_LEN 13
/*
802.11 data frame from AP
,-------------------------------------------------------------------.
Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 |
|------|------|---------|---------|---------|------|---------|------|
Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs |
| | tion | (BSSID) | | | ence | data | |
`-------------------------------------------------------------------'
Total: 28-2340 bytes
*/
struct ieee80211_header_data {
u16 frame_ctl;
u16 duration_id;
u8 addr1[6];
u8 addr2[6];
u8 addr3[6];
u16 seq_ctrl;
};
struct ieee80211_info_element_hdr {
u8 id;
u8 len;
} __attribute__ ((packed));
struct ieee80211_info_element {
u8 id;
u8 len;
u8 data[0];
} __attribute__ ((packed));
struct ieee80211_txb {
u8 nr_frags;
u8 encrypted;
u16 reserved;
u16 frag_size;
u16 payload_size;
struct sk_buff *fragments[0];
};
/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs
* only use 8, and then use extended rates for the remaining supported
* rates. Other APs, however, stick all of their supported rates on the
* main rates information element... */
#define MAX_RATES_LENGTH ((u8)12)
#define MAX_RATES_EX_LENGTH ((u8)16)
#define MAX_CHANNEL_NUMBER 161
#define MAX_WPA_IE_LEN (256)
#define MAX_WPS_IE_LEN (512)
#define MAX_P2P_IE_LEN (256)
#define MAX_WFD_IE_LEN (128)
#define IW_ESSID_MAX_SIZE 32
/*
join_res:
-1: authentication fail
-2: association fail
> 0: TID
*/
#define DEFAULT_MAX_SCAN_AGE (15 * HZ)
#define DEFAULT_FTS 2346
#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
#define CFG_IEEE80211_RESERVE_FCS (1<<0)
#define CFG_IEEE80211_COMPUTE_FCS (1<<1)
#define MAXTID 16
#define IEEE_A (1<<0)
#define IEEE_B (1<<1)
#define IEEE_G (1<<2)
#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G)
/* Baron move to ieee80211.c */
int ieee80211_is_empty_essid23a(const char *essid, int essid_len);
enum _PUBLIC_ACTION{
ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */
ACT_PUBLIC_DSE_ENABLE = 1,
ACT_PUBLIC_DSE_DEENABLE = 2,
ACT_PUBLIC_DSE_REG_LOCATION = 3,
ACT_PUBLIC_EXT_CHL_SWITCH = 4,
ACT_PUBLIC_DSE_MSR_REQ = 5,
ACT_PUBLIC_DSE_MSR_RPRT = 6,
ACT_PUBLIC_MP = 7, /* Measurement Pilot */
ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8,
ACT_PUBLIC_VENDOR = 9, /* for WIFI_DIRECT */
ACT_PUBLIC_GAS_INITIAL_REQ = 10,
ACT_PUBLIC_GAS_INITIAL_RSP = 11,
ACT_PUBLIC_GAS_COMEBACK_REQ = 12,
ACT_PUBLIC_GAS_COMEBACK_RSP = 13,
ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14,
ACT_PUBLIC_LOCATION_TRACK = 15,
ACT_PUBLIC_MAX
};
#define WME_OUI_TYPE 2
#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0
#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1
#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2
#define WME_VERSION 1
#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */
#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */
/* Represent channel details, subset of ieee80211_channel */
struct rtw_ieee80211_channel {
/* enum ieee80211_band band; */
/* u16 center_freq; */
u16 hw_value;
u32 flags;
/* int max_antenna_gain; */
/* int max_power; */
/* int max_reg_power; */
/* bool beacon_found; */
/* u32 orig_flags; */
/* int orig_mag; */
/* int orig_mpwr; */
};
#define CHAN_FMT \
/*"band:%d, "*/ \
/*"center_freq:%u, "*/ \
"hw_value:%u, " \
"flags:0x%08x" \
/*"max_antenna_gain:%d\n"*/ \
/*"max_power:%d\n"*/ \
/*"max_reg_power:%d\n"*/ \
/*"beacon_found:%u\n"*/ \
/*"orig_flags:0x%08x\n"*/ \
/*"orig_mag:%d\n"*/ \
/*"orig_mpwr:%d\n"*/
#define CHAN_ARG(channel) \
/*(channel)->band*/ \
/*, (channel)->center_freq*/ \
(channel)->hw_value \
, (channel)->flags \
/*, (channel)->max_antenna_gain*/ \
/*, (channel)->max_power*/ \
/*, (channel)->max_reg_power*/ \
/*, (channel)->beacon_found*/ \
/*, (channel)->orig_flags*/ \
/*, (channel)->orig_mag*/ \
/*, (channel)->orig_mpwr*/ \
/* Parsed Information Elements */
struct rtw_ieee802_11_elems {
u8 *ssid;
u8 ssid_len;
u8 *supp_rates;
u8 supp_rates_len;
u8 *fh_params;
u8 fh_params_len;
u8 *ds_params;
u8 ds_params_len;
u8 *cf_params;
u8 cf_params_len;
u8 *tim;
u8 tim_len;
u8 *ibss_params;
u8 ibss_params_len;
u8 *challenge;
u8 challenge_len;
u8 *erp_info;
u8 erp_info_len;
u8 *ext_supp_rates;
u8 ext_supp_rates_len;
u8 *wpa_ie;
u8 wpa_ie_len;
u8 *rsn_ie;
u8 rsn_ie_len;
u8 *wme;
u8 wme_len;
u8 *wme_tspec;
u8 wme_tspec_len;
u8 *wps_ie;
u8 wps_ie_len;
u8 *power_cap;
u8 power_cap_len;
u8 *supp_channels;
u8 supp_channels_len;
u8 *mdie;
u8 mdie_len;
u8 *ftie;
u8 ftie_len;
u8 *timeout_int;
u8 timeout_int_len;
u8 *ht_capabilities;
u8 ht_capabilities_len;
u8 *ht_operation;
u8 ht_operation_len;
u8 *vendor_ht_cap;
u8 vendor_ht_cap_len;
};
enum parse_res {
ParseOK = 0,
ParseUnknown = 1,
ParseFailed = -1
};
enum parse_res rtw_ieee802_11_parse_elems23a(u8 *start, uint len,
struct rtw_ieee802_11_elems *elems,
int show_errors);
u8 *rtw_set_fixed_ie23a(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen);
u8 *rtw_set_ie23a(u8 *pbuf, int index, uint len, u8 *source, uint *frlen);
enum secondary_ch_offset {
SCN = 0, /* no secondary channel */
SCA = 1, /* secondary channel above */
SCB = 3, /* secondary channel below */
};
u8 secondary_ch_offset_to_hal_ch_offset23a(u8 ch_offset);
u8 hal_ch_offset_to_secondary_ch_offset23a(u8 ch_offset);
u8 *rtw_set_ie23a_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 ch_switch_cnt);
u8 *rtw_set_ie23a_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset);
u8 *rtw_set_ie23a_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence);
u8 *rtw_get_ie23a(u8*pbuf, int index, int *len, int limit);
u8 *rtw_get_ie23a_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen);
int rtw_ies_remove_ie23a(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len);
void rtw_set_supported_rate23a(u8* SupportedRates, uint mode) ;
unsigned char *rtw_get_wpa_ie23a(unsigned char *pie, int *wpa_ie_len, int limit);
unsigned char *rtw_get_wpa2_ie23a(unsigned char *pie, int *rsn_ie_len, int limit);
int rtw_get_wpa_cipher_suite23a(u8 *s);
int rtw_get_wpa2_cipher_suite23a(u8 *s);
int rtw_parse_wpa_ie23a(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x);
int rtw_parse_wpa2_ie23a(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x);
int rtw_get_sec_ie23a(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16 *wpa_len);
u8 rtw_is_wps_ie23a(u8 *ie_ptr, uint *wps_ielen);
u8 *rtw_get_wps_ie23a(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen);
u8 *rtw_get_wps_attr23a(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_attr, u32 *len_attr);
u8 *rtw_get_wps_attr_content23a(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_content, uint *len_content);
/**
* for_each_ie - iterate over continuous IEs
* @ie:
* @buf:
* @buf_len:
*/
#define for_each_ie(ie, buf, buf_len) \
for (ie = (void*)buf; (((u8*)ie) - ((u8*)buf) + 1) < buf_len; ie = (void*)(((u8*)ie) + *(((u8*)ie)+1) + 2))
void dump_ies23a(u8 *buf, u32 buf_len);
void dump_wps_ie23a(u8 *ie, u32 ie_len);
#ifdef CONFIG_8723AU_P2P
void dump_p2p_ie23a(u8 *ie, u32 ie_len);
u8 *rtw_get_p2p_ie23a(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen);
u8 *rtw_get_p2p_attr23a(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr);
u8 *rtw_get_p2p_attr23a_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content);
u32 rtw_set_p2p_attr_content23a(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr);
void rtw_wlan_bssid_ex_remove_p2p_attr23a(struct wlan_bssid_ex *bss_ex, u8 attr_id);
#endif
#ifdef CONFIG_8723AU_P2P
int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen);
int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id ,u8 *attr_content, uint *attr_contentlen);
#endif /* CONFIG_8723AU_P2P */
uint rtw_get_rateset_len23a(u8 *rateset);
struct registry_priv;
int rtw_generate_ie23a(struct registry_priv *pregistrypriv);
int rtw_get_bit_value_from_ieee_value23a(u8 val);
uint rtw_is_cckrates_included23a(u8 *rate);
uint rtw_is_cckratesonly_included23a(u8 *rate);
int rtw_check_network_type23a(unsigned char *rate, int ratelen, int channel);
void rtw_get_bcn_info23a(struct wlan_network *pnetwork);
void rtw_macaddr_cfg23a(u8 *mac_addr);
u16 rtw_mcs_rate23a(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char * MCS_rate);
int rtw_action_frame_parse23a(const u8 *frame, u32 frame_len, u8* category, u8 *action);
const char *action_public_str23a(u8 action);
#endif /* IEEE80211_H */

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drivers/staging/rtl8723au/include/ioctl_cfg80211.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __IOCTL_CFG80211_H__
#define __IOCTL_CFG80211_H__
struct rtw_wdev_invit_info {
u8 token;
u8 flags;
u8 status;
u8 req_op_ch;
u8 rsp_op_ch;
};
#define rtw_wdev_invit_info_init(invit_info) \
do { \
(invit_info)->token = 0; \
(invit_info)->flags = 0x00; \
(invit_info)->status = 0xff; \
(invit_info)->req_op_ch = 0; \
(invit_info)->rsp_op_ch = 0; \
} while (0)
struct rtw_wdev_priv {
struct wireless_dev *rtw_wdev;
struct rtw_adapter *padapter;
struct cfg80211_scan_request *scan_request;
spinlock_t scan_req_lock;
struct net_device *pmon_ndev;/* for monitor interface */
char ifname_mon[IFNAMSIZ + 1]; /* name for monitor interface */
u8 p2p_enabled;
u8 provdisc_req_issued;
struct rtw_wdev_invit_info invit_info;
bool block;
bool power_mgmt;
};
#define wdev_to_priv(w) ((struct rtw_wdev_priv *)(wdev_priv(w)))
#define wiphy_to_adapter(x) \
(struct rtw_adapter *)(((struct rtw_wdev_priv *) \
wiphy_priv(x))->padapter)
#define wiphy_to_wdev(x) \
(struct wireless_dev *)(((struct rtw_wdev_priv *) \
wiphy_priv(x))->rtw_wdev)
int rtw_wdev_alloc(struct rtw_adapter *padapter, struct device *dev);
void rtw_wdev_free(struct wireless_dev *wdev);
void rtw_wdev_unregister(struct wireless_dev *wdev);
void rtw_cfg80211_init_wiphy(struct rtw_adapter *padapter);
void rtw_cfg80211_surveydone_event_callback(struct rtw_adapter *padapter);
void rtw_cfg80211_indicate_connect(struct rtw_adapter *padapter);
void rtw_cfg80211_indicate_disconnect(struct rtw_adapter *padapter);
void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv,
bool aborted);
#ifdef CONFIG_8723AU_AP_MODE
void rtw_cfg80211_indicate_sta_assoc(struct rtw_adapter *padapter,
u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_indicate_sta_disassoc(struct rtw_adapter *padapter,
unsigned char *da, unsigned short reason);
#endif /* CONFIG_8723AU_AP_MODE */
void rtw_cfg80211_issue_p2p_provision_request23a(struct rtw_adapter *padapter,
const u8 *buf, size_t len);
void rtw_cfg80211_rx_p2p_action_public(struct rtw_adapter *padapter,
u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action_p2p(struct rtw_adapter *padapter,
u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action(struct rtw_adapter *adapter, u8 *frame,
uint frame_len, const char*msg);
int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len,
int type);
bool rtw_cfg80211_pwr_mgmt(struct rtw_adapter *adapter);
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) \
cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, 0, gfp)
#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) \
cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len)
#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) \
cfg80211_mgmt_tx_status((adapter)->rtw_wdev, cookie, buf, \
len, ack, gfp)
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, \
channel_type, duration, gfp) \
cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, \
duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, \
chan_type, gfp) \
cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, \
cookie, chan, gfp)
#endif /* __IOCTL_CFG80211_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __MLME_OSDEP_H_
#define __MLME_OSDEP_H_
#include <osdep_service.h>
#include <drv_types.h>
void rtw_os_indicate_disconnect23a(struct rtw_adapter *adapter);
void rtw_os_indicate_connect23a(struct rtw_adapter *adapter);
void rtw_os_indicate_scan_done23a(struct rtw_adapter *padapter, bool aborted);
void rtw_report_sec_ie23a(struct rtw_adapter *adapter, u8 authmode, u8 *sec_ie);
void rtw_reset_securitypriv23a(struct rtw_adapter *adapter);
#endif /* _MLME_OSDEP_H_ */

342
drivers/staging/rtl8723au/include/mp_custom_oid.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __CUSTOM_OID_H
#define __CUSTOM_OID_H
/* 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit */
/* 0xFF818500 - 0xFF81850F RTL8185 Setup Utility */
/* 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility */
/* For Production Kit with Agilent Equipments */
/* in order to make our custom oids hopefully somewhat unique */
/* we will use 0xFF (indicating implementation specific OID) */
/* 81(first byte of non zero Realtek unique identifier) */
/* 80 (second byte of non zero Realtek unique identifier) */
/* XX (the custom OID number - providing 255 possible custom oids) */
#define OID_RT_PRO_RESET_DUT 0xFF818000
#define OID_RT_PRO_SET_DATA_RATE 0xFF818001
#define OID_RT_PRO_START_TEST 0xFF818002
#define OID_RT_PRO_STOP_TEST 0xFF818003
#define OID_RT_PRO_SET_PREAMBLE 0xFF818004
#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005
#define OID_RT_PRO_SET_FILTER_BB 0xFF818006
#define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB 0xFF818007
#define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL 0xFF818008
#define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL 0xFF818009
#define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL 0xFF81800A
#define OID_RT_PRO_SET_TX_ANTENNA_BB 0xFF81800D
#define OID_RT_PRO_SET_ANTENNA_BB 0xFF81800E
#define OID_RT_PRO_SET_CR_SCRAMBLER 0xFF81800F
#define OID_RT_PRO_SET_CR_NEW_FILTER 0xFF818010
#define OID_RT_PRO_SET_TX_POWER_CONTROL 0xFF818011
#define OID_RT_PRO_SET_CR_TX_CONFIG 0xFF818012
#define OID_RT_PRO_GET_TX_POWER_CONTROL 0xFF818013
#define OID_RT_PRO_GET_CR_SIGNAL_QUALITY 0xFF818014
#define OID_RT_PRO_SET_CR_SETPOINT 0xFF818015
#define OID_RT_PRO_SET_INTEGRATOR 0xFF818016
#define OID_RT_PRO_SET_SIGNAL_QUALITY 0xFF818017
#define OID_RT_PRO_GET_INTEGRATOR 0xFF818018
#define OID_RT_PRO_GET_SIGNAL_QUALITY 0xFF818019
#define OID_RT_PRO_QUERY_EEPROM_TYPE 0xFF81801A
#define OID_RT_PRO_WRITE_MAC_ADDRESS 0xFF81801B
#define OID_RT_PRO_READ_MAC_ADDRESS 0xFF81801C
#define OID_RT_PRO_WRITE_CIS_DATA 0xFF81801D
#define OID_RT_PRO_READ_CIS_DATA 0xFF81801E
#define OID_RT_PRO_WRITE_POWER_CONTROL 0xFF81801F
#define OID_RT_PRO_READ_POWER_CONTROL 0xFF818020
#define OID_RT_PRO_WRITE_EEPROM 0xFF818021
#define OID_RT_PRO_READ_EEPROM 0xFF818022
#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023
#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024
#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025
#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026
#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027
#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028
#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029
#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A
#define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C
/* added by Owen on 04/08/03 for Cameo's request */
#define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D
#define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E
#define OID_RT_PRO_SET_MODULATION 0xFF81802F
/* */
#define OID_RT_DRIVER_OPTION 0xFF818080
#define OID_RT_RF_OFF 0xFF818081
#define OID_RT_AUTH_STATUS 0xFF818082
/* */
#define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B
#define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C
#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B
#define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043
/* */
/* by Owen for RTL8185 Phy Status Report Utility */
#define OID_RT_UTILITYfalse_ALARM_COUNTERS 0xFF818580
#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581
#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582
#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583
#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584
#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585
#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586
/* by Owen on 03/09/19-03/09/22 for RTL8185 */
#define OID_RT_WIRELESS_MODE 0xFF818500
#define OID_RT_SUPPORTED_RATES 0xFF818501
#define OID_RT_DESIRED_RATES 0xFF818502
#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503
/* */
#define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002
#define OID_RT_SET_KEY_LENGTH 0xFF030003
#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004
#define OID_RT_SET_CHANNEL 0xFF010182
#define OID_RT_SET_SNIFFER_MODE 0xFF010183
#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185
#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186
#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187
#define OID_RT_GET_TX_RETRY 0xFF010188
#define OID_RT_GET_RX_RETRY 0xFF010189
#define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A/* S */
#define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B/* S */
#define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190
#define OID_RT_GET_TX_BEACON_OK 0xFF010191
#define OID_RT_GET_TX_BEACON_ERR 0xFF010192
#define OID_RT_GET_RX_ICV_ERR 0xFF010193
#define OID_RT_SET_ENCRYPTION_ALGORITHM 0xFF010194
#define OID_RT_SET_NO_AUTO_RESCAN 0xFF010195
#define OID_RT_GET_PREAMBLE_MODE 0xFF010196
#define OID_RT_GET_DRIVER_UP_DELTA_TIME 0xFF010197
#define OID_RT_GET_AP_IP 0xFF010198
#define OID_RT_GET_CHANNELPLAN 0xFF010199
#define OID_RT_SET_PREAMBLE_MODE 0xFF01019A
#define OID_RT_SET_BCN_INTVL 0xFF01019B
#define OID_RT_GET_RF_VENDER 0xFF01019C
#define OID_RT_DEDICATE_PROBE 0xFF01019D
#define OID_RT_PRO_RX_FILTER_PATTERN 0xFF01019E
#define OID_RT_GET_DCST_CURRENT_THRESHOLD 0xFF01019F
#define OID_RT_GET_CCA_ERR 0xFF0101A0
#define OID_RT_GET_CCA_UPGRADE_THRESHOLD 0xFF0101A1
#define OID_RT_GET_CCA_FALLBACK_THRESHOLD 0xFF0101A2
#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3
#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4
/* by Owen on 03/31/03 for Cameo's request */
#define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5
/* */
#define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5
#define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6
#define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7
#define OID_RT_GET_TOTAL_RX_BYTES 0xFF0101A8
#define OID_RT_CURRENT_TX_POWER_LEVEL 0xFF0101A9
#define OID_RT_GET_ENC_KEY_MISMATCH_COUNT 0xFF0101AA
#define OID_RT_GET_ENC_KEY_MATCH_COUNT 0xFF0101AB
#define OID_RT_GET_CHANNEL 0xFF0101AC
#define OID_RT_SET_CHANNELPLAN 0xFF0101AD
#define OID_RT_GET_HARDWARE_RADIO_OFF 0xFF0101AE
#define OID_RT_CHANNELPLAN_BY_COUNTRY 0xFF0101AF
#define OID_RT_SCAN_AVAILABLE_BSSID 0xFF0101B0
#define OID_RT_GET_HARDWARE_VERSION 0xFF0101B1
#define OID_RT_GET_IS_ROAMING 0xFF0101B2
#define OID_RT_GET_IS_PRIVACY 0xFF0101B3
#define OID_RT_GET_KEY_MISMATCH 0xFF0101B4
#define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH 0xFF0101B5
#define OID_RT_SET_RSSI_ROAM_SIGNAL_TH 0xFF0101B6
#define OID_RT_RESET_LOG 0xFF0101B7
#define OID_RT_GET_LOG 0xFF0101B8
#define OID_RT_SET_INDICATE_HIDDEN_AP 0xFF0101B9
#define OID_RT_GET_HEADER_FAIL 0xFF0101BA
#define OID_RT_SUPPORTED_WIRELESS_MODE 0xFF0101BB
#define OID_RT_GET_CHANNEL_LIST 0xFF0101BC
#define OID_RT_GET_SCAN_IN_PROGRESS 0xFF0101BD
#define OID_RT_GET_TX_INFO 0xFF0101BE
#define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF
#define OID_RT_RF_READ_WRITE 0xFF0101C0
/* For Netgear request. 2005.01.13, by rcnjko. */
#define OID_RT_FORCED_DATA_RATE 0xFF0101C1
#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2
/* For Netgear request. 2005.02.17, by rcnjko. */
#define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3
/* For AZ project. 2005.06.27, by rcnjko. */
#define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4
/* Vincent 8185MP */
#define OID_RT_PRO_RX_FILTER 0xFF0111C0
/* Andy TEST */
/* define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1 */
/* define OID_RT_PRO_READ_REGISTRY 0xFF0111C2 */
#define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1
#define OID_CE_USB_READ_REGISTRY 0xFF0111C2
#define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3
#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4
#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5
#define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6
#define OID_RT_PRO_SET_RX_CHARGE_PUMP 0xFF0111C7
#define OID_RT_PRO_RF_WRITE_REGISTRY 0xFF0111C8
#define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9
#define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA
/* AP OID */
#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300
#define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301
#define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302
#define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303
#define OID_RT_AP_SUPPORTED 0xFF010304 /* Determine if driver supports AP mode. 2004.08.27, by rcnjko. */
#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 /* Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. */
/* 8187MP. 2004.09.06, by rcnjko. */
#define OID_RT_PRO8187_WI_POLL 0xFF818780
#define OID_RT_PRO_WRITE_BB_REG 0xFF818781
#define OID_RT_PRO_READ_BB_REG 0xFF818782
#define OID_RT_PRO_WRITE_RF_REG 0xFF818783
#define OID_RT_PRO_READ_RF_REG 0xFF818784
/* Meeting House. added by Annie, 2005-07-20. */
#define OID_RT_MH_VENDER_ID 0xFFEDC100
/* 8711 MP OID added 20051230. */
#define OID_RT_PRO8711_JOIN_BSS 0xFF871100/* S */
#define OID_RT_PRO_READ_REGISTER 0xFF871101 /* Q */
#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 /* S */
#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 /* Q */
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 /* S */
#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 /* S */
#define OID_RT_PRO_READ16_EEPROM 0xFF871106 /* Q */
#define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 /* S */
#define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 /* S */
#define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 /* Q */
#define OID_RT_PRO8711_WI_POLL 0xFF87110A /* Q */
#define OID_RT_PRO8711_PKT_LOSS 0xFF87110B /* Q */
#define OID_RT_RD_ATTRIB_MEM 0xFF87110C/* Q */
#define OID_RT_WR_ATTRIB_MEM 0xFF87110D/* S */
/* Method 2 for H2C/C2H */
#define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 /* S */
#define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 /* Q */
#define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 /* S */
#define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 /* Q */
#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114/* Q */
#define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 /* Q, S */
#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 /* S */
#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 /* Q,S */
#define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 /* Q */
#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 /* Q */
#define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A /* S */
#define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B /* Q */
#define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C /* S */
#define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D /* Q */
#define OID_RT_PRO_SET_RF_INTFS 0xFF87111E /* S */
#define OID_RT_POLL_RX_STATUS 0xFF87111F /* Q */
#define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 /* Q,S */
#define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121/* S */
#define OID_RT_PRO_SET_BASIC_RATE 0xFF871122/* S */
#define OID_RT_PRO_READ_TSSI 0xFF871123/* S */
#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124/* S */
#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 /* Q */
#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 /* S */
/* Method 2 , using workitem */
#define OID_RT_SET_READ_REG 0xFF871181 /* S */
#define OID_RT_SET_WRITE_REG 0xFF871182 /* S */
#define OID_RT_SET_BURST_READ_REG 0xFF871183 /* S */
#define OID_RT_SET_BURST_WRITE_REG 0xFF871184 /* S */
#define OID_RT_SET_WRITE_TXCMD 0xFF871185 /* S */
#define OID_RT_SET_READ16_EEPROM 0xFF871186 /* S */
#define OID_RT_SET_WRITE16_EEPROM 0xFF871187 /* S */
#define OID_RT_QRY_POLL_WKITEM 0xFF871188 /* Q */
/* For SDIO INTERFACE only */
#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 /* Q, S */
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
/* For USB INTERFACE only */
#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 /* Q, S */
#define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 /* S */
#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 /* S */
#define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 /* Q */
#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 /* Q */
#define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB /* S */
#define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC /* S */
#define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE
#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 /* Q, S */
#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 /* S */
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 /* S */
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 /* Q */
#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 /* Q, S */
#define OID_RT_PRO_READ_EFUSE 0xFF871205 /* Q */
#define OID_RT_PRO_WRITE_EFUSE 0xFF871206 /* S */
#define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 /* Q, S */
#define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 /* Q */
#define OID_RT_SET_BANDWIDTH 0xFF871209 /* S */
#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A /* S */
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B /* S */
#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C /* Q */
#define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D /* S */
#define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E /* S */
#define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F /* S */
#define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 /* Q */
#define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 /* S */
#define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 /* Q */
#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 /* Q */
#define OID_RT_SET_POWER_DOWN 0xFF871214 /* S */
#define OID_RT_GET_POWER_MODE 0xFF871215 /* Q */
#define OID_RT_PRO_EFUSE 0xFF871216 /* Q, S */
#define OID_RT_PRO_EFUSE_MAP 0xFF871217 /* Q, S */
#endif /* ifndef __CUSTOM_OID_H */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
#include <Hal8723APhyCfg.h>
/* */
/* Definition */
/* */
/* */
/* */
/* CCK Rates, TxHT = 0 */
#define DESC92C_RATE1M 0x00
#define DESC92C_RATE2M 0x01
#define DESC92C_RATE5_5M 0x02
#define DESC92C_RATE11M 0x03
/* OFDM Rates, TxHT = 0 */
#define DESC92C_RATE6M 0x04
#define DESC92C_RATE9M 0x05
#define DESC92C_RATE12M 0x06
#define DESC92C_RATE18M 0x07
#define DESC92C_RATE24M 0x08
#define DESC92C_RATE36M 0x09
#define DESC92C_RATE48M 0x0a
#define DESC92C_RATE54M 0x0b
/* MCS Rates, TxHT = 1 */
#define DESC92C_RATEMCS0 0x0c
#define DESC92C_RATEMCS1 0x0d
#define DESC92C_RATEMCS2 0x0e
#define DESC92C_RATEMCS3 0x0f
#define DESC92C_RATEMCS4 0x10
#define DESC92C_RATEMCS5 0x11
#define DESC92C_RATEMCS6 0x12
#define DESC92C_RATEMCS7 0x13
#define DESC92C_RATEMCS8 0x14
#define DESC92C_RATEMCS9 0x15
#define DESC92C_RATEMCS10 0x16
#define DESC92C_RATEMCS11 0x17
#define DESC92C_RATEMCS12 0x18
#define DESC92C_RATEMCS13 0x19
#define DESC92C_RATEMCS14 0x1a
#define DESC92C_RATEMCS15 0x1b
#define DESC92C_RATEMCS15_SG 0x1c
#define DESC92C_RATEMCS32 0x20
/* */
/* structure and define */
/* */
struct phy_rx_agc_info {
#ifdef __LITTLE_ENDIAN
u8 gain:7,trsw:1;
#else
u8 trsw:1,gain:7;
#endif
};
struct phy_status_rpt {
struct phy_rx_agc_info path_agc[RF_PATH_MAX];
u8 ch_corr[RF_PATH_MAX];
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_rpt_b_ofdm_cfosho_b;
u8 rsvd_1;/* ch_corr_msb; */
u8 noise_power_db_msb;
u8 path_cfotail[RF_PATH_MAX];
u8 pcts_mask[RF_PATH_MAX];
s8 stream_rxevm[RF_PATH_MAX];
u8 path_rxsnr[RF_PATH_MAX];
u8 noise_power_db_lsb;
u8 rsvd_2[3];
u8 stream_csi[RF_PATH_MAX];
u8 stream_target_csi[RF_PATH_MAX];
s8 sig_evm;
u8 rsvd_3;
#ifdef __LITTLE_ENDIAN
u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
u8 sgi_en:1;
u8 rxsc:2;
u8 idle_long:1;
u8 r_ant_train_en:1;
u8 ant_sel_b:1;
u8 ant_sel:1;
#else /* _BIG_ENDIAN_ */
u8 ant_sel:1;
u8 ant_sel_b:1;
u8 r_ant_train_en:1;
u8 idle_long:1;
u8 rxsc:2;
u8 sgi_en:1;
u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
#endif
};
struct phy_status_rpt_8195 {
struct phy_rx_agc_info path_agc[2];
u8 ch_num[2];
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_bb_pwr_ofdm_cfosho_b;
u8 cck_rx_path; /* CCK_RX_PATH [3:0] (with regA07[3:0] definition) */
u8 rsvd_1;
u8 path_cfotail[2];
u8 pcts_mask[2];
s8 stream_rxevm[2];
u8 path_rxsnr[2];
u8 rsvd_2[2];
u8 stream_snr[2];
u8 stream_csi[2];
u8 rsvd_3[2];
s8 sig_evm;
u8 rsvd_4;
#ifdef __LITTLE_ENDIAN
u8 antidx_anta:3;
u8 antidx_antb:3;
u8 rsvd_5:2;
#else /* _BIG_ENDIAN_ */
u8 rsvd_5:2;
u8 antidx_antb:3;
u8 antidx_anta:3;
#endif
};
void odm_Init_RSSIForDM23a(struct dm_odm_t *pDM_Odm);
void
ODM_PhyStatusQuery23a(
struct dm_odm_t *pDM_Odm,
struct odm_phy_info *pPhyInfo,
u8 * pPhyStatus,
struct odm_packet_info *pPktinfo
);
void ODM_MacStatusQuery23a(struct dm_odm_t *pDM_Odm,
u8 *pMacStatus,
u8 MacID,
bool bPacketMatchBSSID,
bool bPacketToSelf,
bool bPacketBeacon
);
enum hal_status ODM_ConfigRFWithHeaderFile23a(struct dm_odm_t *pDM_Odm,
enum RF_RADIO_PATH Content,
enum RF_RADIO_PATH eRFPath
);
enum hal_status ODM_ConfigBBWithHeaderFile23a(struct dm_odm_t *pDM_Odm,
enum odm_bb_config_type ConfigType
);
enum hal_status ODM_ConfigMACWithHeaderFile23a(struct dm_odm_t *pDM_Odm);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8723A
#define __INC_ODM_REGCONFIG_H_8723A
void odm_ConfigRFReg_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Data,
enum RF_RADIO_PATH RF_PATH, u32 RegAddr);
void odm_ConfigRF_RadioA_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Data);
void odm_ConfigRF_RadioB_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Data);
void odm_ConfigMAC_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u8 Data);
void odm_ConfigBB_AGC_8723A(struct dm_odm_t *pDM_Odm, u32 Addr,
u32 Bitmask, u32 Data);
void odm_ConfigBB_PHY_REG_PG_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data);
void odm_ConfigBB_PHY_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data);
#endif /* end of SUPPORT */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11AC_H__
#define __ODM_REGDEFINE11AC_H__
/* 2 RF REG LIST */
/* 2 BB REG LIST */
/* PAGE 8 */
/* PAGE 9 */
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
/* PAGE A */
#define ODM_REG_CCK_CCA_11AC 0xA0A
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
#define ODM_REG_CCK_FA_11AC 0xA5C
/* PAGE C */
#define ODM_REG_IGI_A_11AC 0xC50
/* PAGE E */
#define ODM_REG_IGI_B_11AC 0xE50
/* PAGE F */
#define ODM_REG_OFDM_FA_11AC 0xF48
/* 2 MAC REG LIST */
/* DIG Related */
#define ODM_BIT_IGI_11AC 0xFFFFFFFF
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__
/* 2 RF REG LIST */
#define ODM_REG_RF_MODE_11N 0x00
#define ODM_REG_RF_0B_11N 0x0B
#define ODM_REG_CHNBW_11N 0x18
#define ODM_REG_T_METER_11N 0x24
#define ODM_REG_RF_25_11N 0x25
#define ODM_REG_RF_26_11N 0x26
#define ODM_REG_RF_27_11N 0x27
#define ODM_REG_RF_2B_11N 0x2B
#define ODM_REG_RF_2C_11N 0x2C
#define ODM_REG_RXRF_A3_11N 0x3C
#define ODM_REG_T_METER_92D_11N 0x42
#define ODM_REG_T_METER_88E_11N 0x42
/* 2 BB REG LIST */
/* PAGE 8 */
#define ODM_REG_BB_CTRL_11N 0x800
#define ODM_REG_RF_PIN_11N 0x804
#define ODM_REG_PSD_CTRL_11N 0x808
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
#define ODM_REG_BB_PWR_SAV5_11N 0x818
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
#define ODM_REG_RX_DEFUALT_A_11N 0x858
#define ODM_REG_RX_DEFUALT_B_11N 0x85A
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
#define ODM_REG_ANTSEL_CTRL_11N 0x860
#define ODM_REG_RX_ANT_CTRL_11N 0x864
#define ODM_REG_PIN_CTRL_11N 0x870
#define ODM_REG_BB_PWR_SAV1_11N 0x874
#define ODM_REG_ANTSEL_PATH_11N 0x878
#define ODM_REG_BB_3WIRE_11N 0x88C
#define ODM_REG_SC_CNT_11N 0x8C4
#define ODM_REG_PSD_DATA_11N 0x8B4
/* PAGE 9 */
#define ODM_REG_ANT_MAPPING1_11N 0x914
#define ODM_REG_ANT_MAPPING2_11N 0x918
/* PAGE A */
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
#define ODM_REG_CCK_FA_RST_11N 0xA2C
#define ODM_REG_CCK_FA_MSB_11N 0xA58
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
/* PAGE B */
#define ODM_REG_LNA_SWITCH_11N 0xB2C
#define ODM_REG_PATH_SWITCH_11N 0xB30
#define ODM_REG_RSSI_CTRL_11N 0xB38
#define ODM_REG_CONFIG_ANTA_11N 0xB68
#define ODM_REG_RSSI_BT_11N 0xB9C
/* PAGE C */
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_RX_PATH_11N 0xC04
#define ODM_REG_TRMUX_11N 0xC08
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define ODM_REG_IGI_A_11N 0xC50
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
#define ODM_REG_IGI_B_11N 0xC58
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
#define ODM_REG_RX_OFF_11N 0xC7C
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
/* PAGE D */
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
/* PAGE E */
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define ODM_REG_FPGA0_IQK_11N 0xE28
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
#define ODM_REG_TXIQK_PI_A_11N 0xE38
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
#define ODM_REG_TXIQK_11N 0xE40
#define ODM_REG_RXIQK_11N 0xE44
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
#define ODM_REG_BLUETOOTH_11N 0xE6C
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
#define ODM_REG_TX_CCK_RFON_11N 0xE74
#define ODM_REG_TX_CCK_BBON_11N 0xE78
#define ODM_REG_OFDM_RFON_11N 0xE7C
#define ODM_REG_OFDM_BBON_11N 0xE80
#define ODM_REG_TX2RX_11N 0xE84
#define ODM_REG_TX2TX_11N 0xE88
#define ODM_REG_RX_CCK_11N 0xE8C
#define ODM_REG_RX_OFDM_11N 0xED0
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
#define ODM_REG_RX2RX_11N 0xED8
#define ODM_REG_STANDBY_11N 0xEDC
#define ODM_REG_SLEEP_11N 0xEE0
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
/* 2 MAC REG LIST */
#define ODM_REG_BB_RST_11N 0x02
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_EARLY_MODE_11N 0x4D0
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
#define ODM_REG_EDCA_VO_11N 0x500
#define ODM_REG_EDCA_VI_11N 0x504
#define ODM_REG_EDCA_BE_11N 0x508
#define ODM_REG_EDCA_BK_11N 0x50C
#define ODM_REG_TXPAUSE_11N 0x522
#define ODM_REG_RESP_TX_11N 0x6D8
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
/* DIG Related */
#define ODM_BIT_IGI_11N 0x0000007F
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
/* */
/* Define the debug levels */
/* */
/* 1. DBG_TRACE and DBG_LOUD are used for normal cases. */
/* So that, they can help SW engineer to develope or trace states changed */
/* and also help HW enginner to trace every operation to and from HW, */
/* e.g IO, Tx, Rx. */
/* */
/* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, */
/* which help us to debug SW or HW. */
/* */
/* */
/* */
/* Never used in a call to ODM_RT_TRACE()! */
/* */
#define ODM_DBG_OFF 1
/* */
/* Fatal bug. */
/* For example, Tx/Rx/IO locked up, OS hangs, memory access violation, */
/* resource allocation failed, unexpected HW behavior, HW BUG and so on. */
/* */
#define ODM_DBG_SERIOUS 2
/* */
/* Abnormal, rare, or unexpeted cases. */
/* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. */
/* */
#define ODM_DBG_WARNING 3
/* */
/* Normal case with useful information about current SW or HW state. */
/* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, */
/* SW protocol state change, dynamic mechanism state change and so on. */
/* */
#define ODM_DBG_LOUD 4
/* */
/* Normal case with detail execution flow or information. */
/* */
#define ODM_DBG_TRACE 5
/* */
/* Define the tracing components */
/* */
/* */
/* BB Functions */
#define ODM_COMP_DIG BIT0
#define ODM_COMP_RA_MASK BIT1
#define ODM_COMP_DYNAMIC_TXPWR BIT2
#define ODM_COMP_FA_CNT BIT3
#define ODM_COMP_RSSI_MONITOR BIT4
#define ODM_COMP_CCK_PD BIT5
#define ODM_COMP_ANT_DIV BIT6
#define ODM_COMP_PWR_SAVE BIT7
#define ODM_COMP_PWR_TRAIN BIT8
#define ODM_COMP_RATE_ADAPTIVE BIT9
#define ODM_COMP_PATH_DIV BIT10
#define ODM_COMP_PSD BIT11
#define ODM_COMP_DYNAMIC_PRICCA BIT12
#define ODM_COMP_RXHP BIT13
/* MAC Functions */
#define ODM_COMP_EDCA_TURBO BIT16
#define ODM_COMP_EARLY_MODE BIT17
/* RF Functions */
#define ODM_COMP_TX_PWR_TRACK BIT24
#define ODM_COMP_RX_GAIN_TRACK BIT25
#define ODM_COMP_CALIBRATION BIT26
/* Common Functions */
#define ODM_COMP_COMMON BIT30
#define ODM_COMP_INIT BIT31
/*------------------------Export Macro Definition---------------------------*/
#define DbgPrint printk
#define RT_PRINTK(fmt, args...) DbgPrint("%s(): " fmt, __func__, ## args);
#ifndef ASSERT
#define ASSERT(expr)
#endif
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
DbgPrint("[ODM-8723A] "); \
RT_PRINTK fmt; \
}
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \
if(!(expr)) { \
DbgPrint("Assertion failed! %s at ......\n", #expr); \
DbgPrint(" ......%s,%s,line=%d\n", __FILE__, __func__, __LINE__);\
RT_PRINTK fmt; \
ASSERT(false); \
}
#define ODM_dbg_enter() { DbgPrint("==> %s\n", __func__); }
#define ODM_dbg_exit() { DbgPrint("<== %s\n", __func__); }
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __func__, str); }
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel){ \
int __i; \
u8 * __ptr = (u8 *)ptr; \
DbgPrint("[ODM] "); \
DbgPrint(title_str); \
DbgPrint(" "); \
for (__i=0; __i < 6; __i++) \
DbgPrint("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \
DbgPrint("\n"); \
}
void ODM_InitDebugSetting23a(struct dm_odm_t *pDM_Odm);
#endif /* __ODM_DBG_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __ODM_INTERFACE_H__
#define __ODM_INTERFACE_H__
/* */
/* =========== Constant/Structure/Enum/... Define */
/* */
/* */
/* =========== Macro Define */
/* */
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
/* _cat: implemented by Token-Pasting Operator. */
/*===================================
#define ODM_REG_DIG_11N 0xC50
#define ODM_REG_DIG_11AC 0xDDD
ODM_REG(DIG,_pDM_Odm)
=====================================*/
#define _reg_11N(_name) ODM_REG_##_name##_11N
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
_func##_11AC(_name) \
)
/* _name: name of register or bit. */
/* Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" */
/* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. */
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
/* */
/* 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. */
/* Suggest HW team to use thread instead of workitem. Windows also support the feature. */
/* */
typedef void (*RT_WORKITEM_CALL_BACK)(struct work_struct *pContext);
/* */
/* =========== Extern Variable ??? It should be forbidden. */
/* */
/* */
/* =========== EXtern Function Prototype */
/* */
u8 ODM_Read1Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr);
u16 ODM_Read2Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr);
u32 ODM_Read4Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr);
void ODM_Write1Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u8 Data);
void ODM_Write2Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u16 Data);
void ODM_Write4Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 Data);
void ODM_SetMACReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data);
u32 ODM_GetMACReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask);
void ODM_SetBBReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data);
u32 ODM_GetBBReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask);
void ODM_SetRFReg(struct dm_odm_t *pDM_Odm, enum RF_RADIO_PATH eRFPath,
u32 RegAddr, u32 BitMask, u32 Data);
u32 ODM_GetRFReg(struct dm_odm_t *pDM_Odm, enum RF_RADIO_PATH eRFPath,
u32 RegAddr, u32 BitMask);
/* Memory Relative Function. */
void ODM_AllocateMemory(struct dm_odm_t *pDM_Odm, void **pPtr, u32 length);
void ODM_FreeMemory(struct dm_odm_t *pDM_Odm, void *pPtr, u32 length);
s32 ODM_CompareMemory(struct dm_odm_t *pDM_Odm, void *pBuf1, void *pBuf2, u32 length);
/* ODM MISC-spin lock relative API. */
void ODM_AcquireSpinLock(struct dm_odm_t *pDM_Odm, enum rt_spinlock_type type);
void ODM_ReleaseSpinLock(struct dm_odm_t *pDM_Odm, enum rt_spinlock_type type);
/* ODM MISC-workitem relative API. */
void ODM_InitializeWorkItem(struct dm_odm_t *pDM_Odm, void *pRtWorkItem,
RT_WORKITEM_CALL_BACK RtWorkItemCallback, void *pContext, const char *szID);
/* ODM Timer relative API. */
void ODM_SetTimer(struct dm_odm_t *pDM_Odm, struct timer_list *pTimer, u32 msDelay);
void ODM_ReleaseTimer(struct dm_odm_t *pDM_Odm, struct timer_list *pTimer);
/* ODM FW relative API. */
u32 ODM_FillH2CCmd(u8 *pH2CBuffer, u32 H2CBufferLen, u32 CmdNum,
u32 *pElementID, u32 *pCmdLen, u8 **pCmbBuffer,
u8 *CmdStartSeq);
#endif /* __ODM_INTERFACE_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __ODM_PRECOMP_H__
#define __ODM_PRECOMP_H__
#include "odm_types.h"
#define TEST_FALG___ 1
/* 2 Config Flags and Structs - defined by each ODM Type */
#include <osdep_service.h>
#include <drv_types.h>
#include <hal_intf.h>
/* 2 Hardware Parameter Files */
#include "Hal8723UHWImg_CE.h"
/* 2 OutSrc Header Files */
#include "odm.h"
#include "odm_HWConfig.h"
#include "odm_debug.h"
#include "odm_RegDefine11AC.h"
#include "odm_RegDefine11N.h"
#include "HalDMOutSrc8723A.h" /* for IQK,LCK,Power-tracking */
#include "rtl8723a_hal.h"
#include "odm_interface.h"
#include "odm_reg.h"
#include "HalHWImg8723A_MAC.h"
#include "HalHWImg8723A_RF.h"
#include "HalHWImg8723A_BB.h"
#include "HalHWImg8723A_FW.h"
#include "odm_RegConfig8723A.h"
#endif /* __ODM_PRECOMP_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/* */
/* File Name: odm_reg.h */
/* */
/* Description: */
/* */
/* This file is for general register definition. */
/* */
/* */
/* */
#ifndef __HAL_ODM_REG_H__
#define __HAL_ODM_REG_H__
/* */
/* Register Definition */
/* */
/* MAC REG */
#define ODM_BB_RESET 0x002
#define ODM_DUMMY 0x4fe
#define ODM_EDCA_VO_PARAM 0x500
#define ODM_EDCA_VI_PARAM 0x504
#define ODM_EDCA_BE_PARAM 0x508
#define ODM_EDCA_BK_PARAM 0x50C
#define ODM_TXPAUSE 0x522
/* BB REG */
#define ODM_FPGA_PHY0_PAGE8 0x800
#define ODM_PSD_SETTING 0x808
#define ODM_AFE_SETTING 0x818
#define ODM_TXAGC_B_6_18 0x830
#define ODM_TXAGC_B_24_54 0x834
#define ODM_TXAGC_B_MCS32_5 0x838
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
#define ODM_TXAGC_B_MCS4_MCS7 0x848
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
#define ODM_ANALOG_REGISTER 0x85c
#define ODM_RF_INTERFACE_OUTPUT 0x860
#define ODM_TXAGC_B_MCS12_MCS15 0x868
#define ODM_TXAGC_B_11_A_2_11 0x86c
#define ODM_AD_DA_LSB_MASK 0x874
#define ODM_ENABLE_3_WIRE 0x88c
#define ODM_PSD_REPORT 0x8b4
#define ODM_R_ANT_SELECT 0x90c
#define ODM_CCK_ANT_SELECT 0xa07
#define ODM_CCK_PD_THRESH 0xa0a
#define ODM_CCK_RF_REG1 0xa11
#define ODM_CCK_MATCH_FILTER 0xa20
#define ODM_CCK_RAKE_MAC 0xa2e
#define ODM_CCK_CNT_RESET 0xa2d
#define ODM_CCK_TX_DIVERSITY 0xa2f
#define ODM_CCK_FA_CNT_MSB 0xa5b
#define ODM_CCK_FA_CNT_LSB 0xa5c
#define ODM_CCK_NEW_FUNCTION 0xa75
#define ODM_OFDM_PHY0_PAGE_C 0xc00
#define ODM_OFDM_RX_ANT 0xc04
#define ODM_R_A_RXIQI 0xc14
#define ODM_R_A_AGC_CORE1 0xc50
#define ODM_R_A_AGC_CORE2 0xc54
#define ODM_R_B_AGC_CORE1 0xc58
#define ODM_R_AGC_PAR 0xc70
#define ODM_R_HTSTF_AGC_PAR 0xc7c
#define ODM_TX_PWR_TRAINING_A 0xc90
#define ODM_TX_PWR_TRAINING_B 0xc98
#define ODM_OFDM_FA_CNT1 0xcf0
#define ODM_OFDM_PHY0_PAGE_D 0xd00
#define ODM_OFDM_FA_CNT2 0xda0
#define ODM_OFDM_FA_CNT3 0xda4
#define ODM_OFDM_FA_CNT4 0xda8
#define ODM_TXAGC_A_6_18 0xe00
#define ODM_TXAGC_A_24_54 0xe04
#define ODM_TXAGC_A_1_MCS32 0xe08
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
/* RF REG */
#define ODM_GAIN_SETTING 0x00
#define ODM_CHANNEL 0x18
/* Ant Detect Reg */
#define ODM_DPDT 0x300
/* PSD Init */
#define ODM_PSDREG 0x808
/* 92D Path Div */
#define PATHDIV_REG 0xB30
#define PATHDIV_TRI 0xBA0
/* */
/* Bitmap Definition */
/* */
#define BIT_FA_RESET BIT0
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __ODM_TYPES_H__
#define __ODM_TYPES_H__
/* Define Different SW team support */
enum hal_status {
HAL_STATUS_SUCCESS,
HAL_STATUS_FAILURE,
};
enum rt_spinlock_type {
RT_TEMP =1,
};
#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
#endif /* __ODM_TYPES_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __OSDEP_INTF_H_
#define __OSDEP_INTF_H_
#include <osdep_service.h>
#include <drv_types.h>
int rtw_hw_suspend23a(struct rtw_adapter *padapter);
int rtw_hw_resume23a(struct rtw_adapter *padapter);
u8 rtw_init_drv_sw23a(struct rtw_adapter *padapter);
u8 rtw_free_drv_sw23a(struct rtw_adapter *padapter);
u8 rtw_reset_drv_sw23a(struct rtw_adapter *padapter);
u32 rtw_start_drv_threads23a(struct rtw_adapter *padapter);
void rtw_stop_drv_threads23a (struct rtw_adapter *padapter);
void rtw_cancel_all_timer23a(struct rtw_adapter *padapter);
int rtw_init_netdev23a_name23a(struct net_device *pnetdev, const char *ifname);
struct net_device *rtw_init_netdev23a(struct rtw_adapter *padapter);
u16 rtw_recv_select_queue23a(struct sk_buff *skb);
void rtw_ips_dev_unload23a(struct rtw_adapter *padapter);
int rtw_ips_pwr_up23a(struct rtw_adapter *padapter);
void rtw_ips_pwr_down23a(struct rtw_adapter *padapter);
int rtw_drv_register_netdev(struct rtw_adapter *padapter);
void rtw_ndev_destructor(struct net_device *ndev);
#endif /* _OSDEP_INTF_H_ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __OSDEP_SERVICE_H_
#define __OSDEP_SERVICE_H_
#define _FAIL 0
#define _SUCCESS 1
#define RTW_RX_HANDLED 2
#include <linux/version.h>
#include <linux/spinlock.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kref.h>
#include <linux/netdevice.h>
#include <linux/skbuff.h>
#include <linux/circ_buf.h>
#include <asm/uaccess.h>
#include <asm/byteorder.h>
#include <asm/atomic.h>
#include <asm/io.h>
#include <linux/semaphore.h>
#include <linux/sem.h>
#include <linux/sched.h>
#include <linux/etherdevice.h>
#include <linux/wireless.h>
#include <net/iw_handler.h>
#include <linux/if_arp.h>
#include <linux/rtnetlink.h>
#include <linux/delay.h>
#include <linux/proc_fs.h> /* Necessary because we use the proc fs */
#include <linux/interrupt.h> /* for struct tasklet_struct */
#include <linux/ip.h>
#include <linux/kthread.h>
/* #include <linux/ieee80211.h> */
#include <net/ieee80211_radiotap.h>
#include <net/cfg80211.h>
#include <linux/usb.h>
#include <linux/usb/ch9.h>
struct rtw_adapter;
struct c2h_evt_hdr;
typedef s32 (*c2h_id_filter)(u8 id);
struct rtw_queue {
struct list_head queue;
spinlock_t lock;
};
static inline struct list_head *get_list_head(struct rtw_queue *queue)
{
return (&queue->queue);
}
static inline int rtw_netif_queue_stopped(struct net_device *pnetdev)
{
return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) &&
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) &&
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) &&
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)) );
}
#ifndef BIT
#define BIT(x) ( 1 << (x))
#endif
static inline u32 CHKBIT(u32 x)
{
WARN_ON(x >= 32);
if (x >= 32)
return 0;
return BIT(x);
}
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define BIT32 0x0100000000
#define BIT33 0x0200000000
#define BIT34 0x0400000000
#define BIT35 0x0800000000
#define BIT36 0x1000000000
int RTW_STATUS_CODE23a(int error_code);
u8* _rtw_vmalloc(u32 sz);
u8* _rtw_zvmalloc(u32 sz);
void _rtw_vmfree(u8 *pbuf, u32 sz);
#define rtw_vmalloc(sz) _rtw_vmalloc((sz))
#define rtw_zvmalloc(sz) _rtw_zvmalloc((sz))
#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz))
extern unsigned char REALTEK_96B_IE23A[];
extern unsigned char MCS_rate_2R23A[16];
extern unsigned char RTW_WPA_OUI23A[];
extern unsigned char WPA_TKIP_CIPHER23A[4];
extern unsigned char RSN_TKIP_CIPHER23A[4];
extern unsigned char MCS_rate_2R23A[16];
extern unsigned char MCS_rate_1R23A[16];
void _rtw_init_queue23a(struct rtw_queue *pqueue);
u32 _rtw_queue_empty23a(struct rtw_queue *pqueue);
static inline u32 bitshift(u32 bitmask)
{
u32 i;
for (i = 0; i <= 31; i++)
if (((bitmask>>i) & 0x1) == 1) break;
return i;
}
void rtw_suspend_lock_init(void);
void rtw_suspend_lock_uninit(void);
void rtw_lock_suspend(void);
void rtw_unlock_suspend(void);
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ndev->name
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) adapter->pnetdev->name
#define FUNC_NDEV_FMT "%s(%s)"
#define FUNC_NDEV_ARG(ndev) __func__, ndev->name
#define FUNC_ADPT_FMT "%s(%s)"
#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name
#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)),(sig), 1)
u64 rtw_modular6423a(u64 x, u64 y);
u64 rtw_division6423a(u64 x, u64 y);
/* Macros for handling unaligned memory accesses */
#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
((u32) (a)[2]))
struct rtw_cbuf {
u32 write;
u32 read;
u32 size;
void *bufs[0];
};
bool rtw_cbuf_full23a(struct rtw_cbuf *cbuf);
bool rtw_cbuf_empty23a(struct rtw_cbuf *cbuf);
bool rtw_cbuf_push23a(struct rtw_cbuf *cbuf, void *buf);
void *rtw_cbuf_pop23a(struct rtw_cbuf *cbuf);
struct rtw_cbuf *rtw_cbuf_alloc23a(u32 size);
void rtw_cbuf_free(struct rtw_cbuf *cbuf);
int rtw_change_ifname(struct rtw_adapter *padapter, const char *ifname);
s32 c2h_evt_hdl(struct rtw_adapter *adapter, struct c2h_evt_hdr *c2h_evt, c2h_id_filter filter);
void indicate_wx_scan_complete_event(struct rtw_adapter *padapter);
u8 rtw_do_join23a(struct rtw_adapter *padapter);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RECV_OSDEP_H_
#define __RECV_OSDEP_H_
#include <osdep_service.h>
#include <drv_types.h>
int _rtw_init_recv_priv23a(struct recv_priv *precvpriv, struct rtw_adapter *padapter);
void _rtw_free_recv_priv23a (struct recv_priv *precvpriv);
int rtw_recv_entry23a(struct recv_frame *precv_frame);
int rtw_recv_indicatepkt23a(struct rtw_adapter *adapter, struct recv_frame *precv_frame);
void rtw_recv_returnpacket(struct net_device *cnxt, struct sk_buff *preturnedpkt);
void rtw_hostapd_mlme_rx23a(struct rtw_adapter *padapter, struct recv_frame *precv_frame);
void rtw_handle_tkip_mic_err23a(struct rtw_adapter *padapter, u8 bgroup);
int rtw_init_recv_priv(struct recv_priv *precvpriv, struct rtw_adapter *padapter);
void rtw_free_recv_priv (struct recv_priv *precvpriv);
int rtw_os_recv_resource_init(struct recv_priv *precvpriv, struct rtw_adapter *padapter);
int rtw_os_recv_resource_alloc23a(struct rtw_adapter *padapter, struct recv_frame *precvframe);
void rtw_os_recv_resource_free(struct recv_priv *precvpriv);
int rtw_os_recvbuf_resource_alloc23a(struct rtw_adapter *padapter, struct recv_buf *precvbuf);
int rtw_os_recvbuf_resource_free23a(struct rtw_adapter *padapter, struct recv_buf *precvbuf);
void rtw_os_read_port23a(struct rtw_adapter *padapter, struct recv_buf *precvbuf);
void rtw_init_recv_timer23a(struct recv_reorder_ctrl *preorder_ctrl);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTL8723A_CMD_H__
#define __RTL8723A_CMD_H__
#define H2C_BT_FW_PATCH_LEN 3
#define H2C_BT_PWR_FORCE_LEN 3
enum cmd_msg_element_id
{
NONE_CMDMSG_EID,
AP_OFFLOAD_EID = 0,
SET_PWRMODE_EID = 1,
JOINBSS_RPT_EID = 2,
RSVD_PAGE_EID = 3,
RSSI_4_EID = 4,
RSSI_SETTING_EID = 5,
MACID_CONFIG_EID = 6,
MACID_PS_MODE_EID = 7,
P2P_PS_OFFLOAD_EID = 8,
SELECTIVE_SUSPEND_ROF_CMD = 9,
BT_QUEUE_PKT_EID = 17,
BT_ANT_TDMA_EID = 20,
BT_2ANT_HID_EID = 21,
P2P_PS_CTW_CMD_EID = 32,
FORCE_BT_TX_PWR_EID = 33,
SET_TDMA_WLAN_ACT_TIME_EID = 34,
SET_BT_TX_RETRY_INDEX_EID = 35,
HID_PROFILE_ENABLE_EID = 36,
BT_IGNORE_WLAN_ACT_EID = 37,
BT_PTA_MANAGER_UPDATE_ENABLE_EID = 38,
DAC_SWING_VALUE_EID = 41,
TRADITIONAL_TDMA_EN_EID = 51,
H2C_BT_FW_PATCH = 54,
B_TYPE_TDMA_EID = 58,
SCAN_EN_EID = 59,
LOWPWR_LPS_EID = 71,
H2C_RESET_TSF = 75,
MAX_CMDMSG_EID
};
struct cmd_msg_parm {
u8 eid; /* element id */
u8 sz; /* sz */
u8 buf[6];
};
struct setpwrmode_parm {
u8 Mode;
u8 SmartPS;
u8 AwakeInterval; /* unit: beacon interval */
u8 bAllQueueUAPSD;
#define SETPM_LOWRXBCN BIT(0)
#define SETPM_AUTOANTSWITCH BIT(1)
#define SETPM_PSALLOWBTHIGHPRI BIT(2)
u8 BcnAntMode;
} __packed;
struct H2C_SS_RFOFF_PARAM{
u8 ROFOn; /* 1: on, 0:off */
u16 gpio_period; /* unit: 1024 us */
}__attribute__ ((packed));
struct joinbssrpt_parm {
u8 OpMode; /* enum rt_media_status */
};
struct rsvdpage_loc {
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocNullData;
u8 LocQosNull;
u8 LocBTQosNull;
};
struct P2P_PS_Offload_t {
u8 Offload_En:1;
u8 role:1; /* 1: Owner, 0: Client */
u8 CTWindow_En:1;
u8 NoA0_En:1;
u8 NoA1_En:1;
u8 AllStaSleep:1; /* Only valid in Owner */
u8 discovery:1;
u8 rsvd:1;
};
struct P2P_PS_CTWPeriod_t {
u8 CTWPeriod; /* TU */
};
#define B_TDMA_EN BIT(0)
#define B_TDMA_FIXANTINBT BIT(1)
#define B_TDMA_TXPSPOLL BIT(2)
#define B_TDMA_VAL870 BIT(3)
#define B_TDMA_AUTOWAKEUP BIT(4)
#define B_TDMA_NOPS BIT(5)
#define B_TDMA_WLANHIGHPRI BIT(6)
struct b_type_tdma_parm {
u8 option;
u8 TBTTOnPeriod;
u8 MedPeriod;
u8 rsvd30;
} __packed;
struct scan_en_parm {
u8 En;
} __packed;
/* BT_PWR */
#define SET_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
/* BT_FW_PATCH */
#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 0, 8, __Value) /* SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) */
#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 8, 16, __Value) /* SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value) */
struct lowpwr_lps_parm{
u8 bcn_count:4;
u8 tb_bcn_threshold:3;
u8 enable:1;
u8 bcn_interval;
u8 drop_threshold;
u8 max_early_period;
u8 max_bcn_timeout_period;
} __packed;
/* host message to firmware cmd */
void rtl8723a_set_FwPwrMode_cmd(struct rtw_adapter * padapter, u8 Mode);
void rtl8723a_set_FwJoinBssReport_cmd(struct rtw_adapter * padapter, u8 mstatus);
#ifdef CONFIG_8723AU_BT_COEXIST
void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(struct rtw_adapter * padapter);
#endif
u8 rtl8723a_set_rssi_cmd(struct rtw_adapter * padapter, u8 *param);
u8 rtl8723a_set_raid_cmd(struct rtw_adapter * padapter, u32 mask, u8 arg);
void rtl8723a_add_rateatid(struct rtw_adapter * padapter, u32 bitmap, u8 arg, u8 rssi_level);
#ifdef CONFIG_8723AU_P2P
void rtl8723a_set_p2p_ps_offload_cmd(struct rtw_adapter * padapter, u8 p2p_ps_state);
#endif /* CONFIG_8723AU_P2P */
void CheckFwRsvdPageContent23a(struct rtw_adapter *padapter);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTL8723A_DM_H__
#define __RTL8723A_DM_H__
/* */
/* Description: */
/* */
/* This file is for 8723A dynamic mechanism only */
/* */
/* */
/* */
#define DYNAMIC_FUNC_BT BIT(0)
enum{
UP_LINK,
DOWN_LINK,
};
/* */
/* structure and define */
/* */
/* duplicate code,will move to ODM ######### */
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
/* duplicate code,will move to ODM ######### */
struct dm_priv
{
u8 DM_Type;
u8 DMFlag;
u8 InitDMFlag;
u32 InitODMFlag;
/* Upper and Lower Signal threshold for Rate Adaptive*/
int UndecoratedSmoothedPWDB;
int UndecoratedSmoothedCCK;
int EntryMinUndecoratedSmoothedPWDB;
int EntryMaxUndecoratedSmoothedPWDB;
int MinUndecoratedPWDBForDM;
int LastMinUndecoratedPWDBForDM;
s32 UndecoratedSmoothedBeacon;
#ifdef CONFIG_8723AU_BT_COEXIST
s32 BT_EntryMinUndecoratedSmoothedPWDB;
s32 BT_EntryMaxUndecoratedSmoothedPWDB;
#endif
/* for High Power */
u8 bDynamicTxPowerEnable;
u8 LastDTPLvl;
u8 DynamicTxHighPowerLvl;/* Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 */
/* for tx power tracking */
u8 bTXPowerTracking;
u8 TXPowercount;
u8 bTXPowerTrackingInit;
u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
u8 TM_Trigger;
u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
u8 ThermalValue;
u8 ThermalValue_LCK;
u8 ThermalValue_IQK;
u8 ThermalValue_DPK;
u8 bRfPiEnable;
/* for APK */
u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 bAPKdone;
u8 bAPKThermalMeterIgnore;
u8 bDPdone;
u8 bDPPathAOK;
u8 bDPPathBOK;
/* for IQK */
u32 RegC04;
u32 Reg874;
u32 RegC08;
u32 RegB68;
u32 RegB6C;
u32 Reg870;
u32 Reg860;
u32 Reg864;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u8 PowerIndex_backup[6];
u8 bCCKinCH14;
u8 CCK_index;
u8 OFDM_index[2];
u8 bDoneTxpower;
u8 CCK_index_HP;
u8 OFDM_index_HP[2];
u8 ThermalValue_HP[HP_THERMAL_NUM];
u8 ThermalValue_HP_index;
/* for TxPwrTracking */
s32 RegE94;
s32 RegE9C;
s32 RegEB4;
s32 RegEBC;
u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
u32 prv_traffic_idx; /* edca turbo */
s32 OFDM_Pkt_Cnt;
u8 RSSI_Select;
/* u8 DIG_Dynamic_MIN ; */
/* duplicate code,will move to ODM ######### */
/* Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas */
u8 INIDATA_RATE[32];
};
/* */
/* function prototype */
/* */
void rtl8723a_init_dm_priv(struct rtw_adapter *padapter);
void rtl8723a_deinit_dm_priv(struct rtw_adapter *padapter);
void rtl8723a_InitHalDm(struct rtw_adapter *padapter);
void rtl8723a_HalDmWatchDog(struct rtw_adapter *padapter);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTL8723A_HAL_H__
#define __RTL8723A_HAL_H__
#include "rtl8723a_spec.h"
#include "rtl8723a_pg.h"
#include "Hal8723APhyReg.h"
#include "Hal8723APhyCfg.h"
#include "rtl8723a_rf.h"
#ifdef CONFIG_8723AU_BT_COEXIST
#include "rtl8723a_bt-coexist.h"
#endif
#include "rtl8723a_dm.h"
#include "rtl8723a_recv.h"
#include "rtl8723a_xmit.h"
#include "rtl8723a_cmd.h"
#include "rtl8723a_sreset.h"
#include "rtw_efuse.h"
#include "odm_precomp.h"
/* 2TODO: We should define 8192S firmware related macro settings here!! */
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
/* TODO: The following need to check!! */
#define RTL8723_FW_UMC_IMG "rtl8192CU\\rtl8723fw.bin"
#define RTL8723_FW_UMC_B_IMG "rtl8192CU\\rtl8723fw_B.bin"
#define RTL8723_PHY_REG "rtl8723S\\PHY_REG_1T.txt"
#define RTL8723_PHY_RADIO_A "rtl8723S\\radio_a_1T.txt"
#define RTL8723_PHY_RADIO_B "rtl8723S\\radio_b_1T.txt"
#define RTL8723_AGC_TAB "rtl8723S\\AGC_TAB_1T.txt"
#define RTL8723_PHY_MACREG "rtl8723S\\MAC_REG.txt"
#define RTL8723_PHY_REG_PG "rtl8723S\\PHY_REG_PG.txt"
#define RTL8723_PHY_REG_MP "rtl8723S\\PHY_REG_MP.txt"
/* */
/* RTL8723S From header */
/* */
/* Fw Array */
#define Rtl8723_FwImageArray Rtl8723UFwImgArray
#define Rtl8723_FwUMCBCutImageArrayWithBT Rtl8723UFwUMCBCutImgArrayWithBT
#define Rtl8723_FwUMCBCutImageArrayWithoutBT Rtl8723UFwUMCBCutImgArrayWithoutBT
#define Rtl8723_ImgArrayLength Rtl8723UImgArrayLength
#define Rtl8723_UMCBCutImgArrayWithBTLength Rtl8723UUMCBCutImgArrayWithBTLength
#define Rtl8723_UMCBCutImgArrayWithoutBTLength Rtl8723UUMCBCutImgArrayWithoutBTLength
#define Rtl8723_PHY_REG_Array_PG Rtl8723UPHY_REG_Array_PG
#define Rtl8723_PHY_REG_Array_PGLength Rtl8723UPHY_REG_Array_PGLength
#define Rtl8723_FwUMCBCutMPImageArray Rtl8723SFwUMCBCutMPImgAr
#define Rtl8723_UMCBCutMPImgArrayLength Rtl8723SUMCBCutMPImgArrayLength
#define DRVINFO_SZ 4 /* unit is 8bytes */
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
#define FW_8723A_SIZE 0x8000
#define FW_8723A_START_ADDRESS 0x1000
#define FW_8723A_END_ADDRESS 0x1FFF /* 0x5FFF */
#define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */
#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
/* */
/* This structure must be cared byte-ordering */
/* */
/* Added by tynli. 2009.12.04. */
struct rt_8723a_firmware_hdr {
/* 8-byte alinment required */
/* LONG WORD 0 ---- */
u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
u8 Category; /* AP/NIC and USB/PCI */
u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
u16 Version; /* FW Version */
u8 Subversion; /* FW Subversion, default 0x00 */
u16 Rsvd1;
/* LONG WORD 1 ---- */
u8 Month; /* Release time Month field */
u8 Date; /* Release time Date field */
u8 Hour; /* Release time Hour field */
u8 Minute; /* Release time Minute field */
u16 RamCodeSize; /* The size of RAM code */
u16 Rsvd2;
/* LONG WORD 2 ---- */
u32 SvnIdx; /* The SVN entry index */
u32 Rsvd3;
/* LONG WORD 3 ---- */
u32 Rsvd4;
u32 Rsvd5;
};
#define DRIVER_EARLY_INT_TIME 0x05
#define BCN_DMA_ATIME_INT_TIME 0x02
/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
#define MAX_TX_QUEUE 9
#define TX_SELE_HQ BIT(0) /* High Queue */
#define TX_SELE_LQ BIT(1) /* Low Queue */
#define TX_SELE_NQ BIT(2) /* Normal Queue */
/* Note: We will divide number of page equally for each queue other than public queue! */
#define TX_TOTAL_PAGE_NUMBER 0xF8
#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
/* For Normal Chip Setting */
/* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
#define NORMAL_PAGE_NUM_PUBQ 0xE7
#define NORMAL_PAGE_NUM_HPQ 0x0C
#define NORMAL_PAGE_NUM_LPQ 0x02
#define NORMAL_PAGE_NUM_NPQ 0x02
/* For Test Chip Setting */
/* (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
#define TEST_PAGE_NUM_PUBQ 0x7E
/* For Test Chip Setting */
#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
#define WMM_TEST_PAGE_NUM_HPQ 0x29
#define WMM_TEST_PAGE_NUM_LPQ 0x29
/* Note: For Normal Chip Setting, modify later */
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
#define WMM_NORMAL_PAGE_NUM_HPQ 0x29
#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C
/* */
/* Chip specific */
/* */
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
#define CHIP_BONDING_92C_1T2R 0x1
#define CHIP_BONDING_88C_USB_MCARD 0x2
#define CHIP_BONDING_88C_USB_HP 0x1
#include "HalVerDef.h"
#include "hal_com.h"
/* */
/* Channel Plan */
/* */
enum ChannelPlan
{
CHPL_FCC = 0,
CHPL_IC = 1,
CHPL_ETSI = 2,
CHPL_SPAIN = 3,
CHPL_FRANCE = 4,
CHPL_MKK = 5,
CHPL_MKK1 = 6,
CHPL_ISRAEL = 7,
CHPL_TELEC = 8,
CHPL_GLOBAL = 9,
CHPL_WORLD = 10,
};
#define EFUSE_REAL_CONTENT_LEN 512
#define EFUSE_MAP_LEN 128
#define EFUSE_MAX_SECTION 16
#define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
/* */
/* <Roger_Notes> */
/* To prevent out of boundary programming case, */
/* leave 1byte and program full section */
/* 9bytes + 1byt + 5bytes and pre 1byte. */
/* For worst case: */
/* | 1byte|----8bytes----|1byte|--5bytes--| */
/* | | Reserved(14bytes) | */
/* */
/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
#define EFUSE_OOB_PROTECT_BYTES 15
#define EFUSE_REAL_CONTENT_LEN_8723A 512
#define EFUSE_MAP_LEN_8723A 256
#define EFUSE_MAX_SECTION_8723A 32
/* */
/* EFUSE for BT definition */
/* */
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512
#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */
#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */
#define EFUSE_PROTECT_BYTES_BANK 16
/* */
/* <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */
/* */
enum RT_MULTI_FUNC {
RT_MULTI_FUNC_NONE = 0x00,
RT_MULTI_FUNC_WIFI = 0x01,
RT_MULTI_FUNC_BT = 0x02,
RT_MULTI_FUNC_GPS = 0x04,
};
/* */
/* <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */
/* */
enum RT_POLARITY_CTL {
RT_POLARITY_LOW_ACT = 0,
RT_POLARITY_HIGH_ACT = 1,
};
/* For RTL8723 regulator mode. by tynli. 2011.01.14. */
enum RT_REGULATOR_MODE {
RT_SWITCHING_REGULATOR = 0,
RT_LDO_REGULATOR = 1,
};
/* Description: Determine the types of C2H events that are the same in driver and Fw. */
/* Fisrt constructed by tynli. 2009.10.09. */
enum {
C2H_DBG = 0,
C2H_TSF = 1,
C2H_AP_RPT_RSP = 2,
C2H_CCX_TX_RPT = 3, /* The FW notify the report of the specific tx packet. */
C2H_BT_RSSI = 4,
C2H_BT_OP_MODE = 5,
C2H_EXT_RA_RPT = 6,
C2H_HW_INFO_EXCH = 10,
C2H_C2H_H2C_TEST = 11,
C2H_BT_INFO = 12,
C2H_BT_MP_INFO = 15,
MAX_C2HEVENT
};
struct hal_data_8723a {
struct hal_version VersionID;
enum rt_customer_id CustomerID;
u16 FirmwareVersion;
u16 FirmwareVersionRev;
u16 FirmwareSubVersion;
u16 FirmwareSignature;
/* current WIFI_PHY values */
u32 ReceiveConfig;
enum WIRELESS_MODE CurrentWirelessMode;
enum ht_channel_width CurrentChannelBW;
u8 CurrentChannel;
u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */
u16 BasicRateSet;
/* rf_ctrl */
u8 rf_chip;
u8 rf_type;
u8 NumTotalRFPath;
u8 BoardType;
u8 CrystalCap;
/* */
/* EEPROM setting. */
/* */
u8 EEPROMVersion;
u16 EEPROMVID;
u16 EEPROMPID;
u16 EEPROMSVID;
u16 EEPROMSDID;
u8 EEPROMCustomerID;
u8 EEPROMSubCustomerID;
u8 EEPROMRegulatory;
u8 EEPROMThermalMeter;
u8 EEPROMBluetoothCoexist;
u8 EEPROMBluetoothType;
u8 EEPROMBluetoothAntNum;
u8 EEPROMBluetoothAntIsolation;
u8 EEPROMBluetoothRadioShared;
u8 bTXPowerDataReadFromEEPORM;
u8 bAPKThermalMeterIgnore;
u8 bIQKInitialized;
u8 bAntennaDetected;
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */
u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */
/* For power group */
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */
/* Read/write are allow for following hardware information variables */
u8 framesync;
u32 framesyncC34;
u8 framesyncMonitor;
u8 DefaultInitialGain[4];
u8 pwrGroupCnt;
u32 MCSTxPowerLevelOriginalOffset[7][16];
u32 CCKTxPowerLevelOriginalOffset;
u32 AntennaTxPath; /* Antenna path Tx */
u32 AntennaRxPath; /* Antenna path Rx */
u8 ExternalPA;
u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
u8 b1x1RecvCombine; /* for 1T1R receive combining */
/* For EDCA Turbo mode */
u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
/* vivi, for tx power tracking, 20080407 */
/* u16 TSSI_13dBm; */
/* u32 Pwr_Track; */
/* The current Tx Power Level */
u8 CurrentCckTxPwrIdx;
u8 CurrentOfdm24GTxPwrIdx;
struct bb_reg_define PHYRegDef[4]; /* Radio A/B/C/D */
bool bRFPathRxEnable[4]; /* We support 4 RF path now. */
u32 RfRegChnlVal[2];
u8 bCckHighPower;
/* RDG enable */
bool bRDGEnable;
/* for host message to fw */
u8 LastHMEBoxNum;
u8 fw_ractrl;
u8 RegTxPause;
/* Beacon function related global variable. */
u32 RegBcnCtrlVal;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
struct dm_priv dmpriv;
struct dm_odm_t odmpriv;
struct sreset_priv srestpriv;
#ifdef CONFIG_8723AU_BT_COEXIST
u8 bBTMode;
/* BT only. */
struct bt_30info BtInfo;
/* For bluetooth co-existance */
struct bt_coexist_str bt_coexist;
#endif
u8 bDumpRxPkt;/* for debug */
u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */
/* 2010/08/09 MH Add CU power down mode. */
u8 pwrdown;
/* Add for dual MAC 0--Mac0 1--Mac1 */
u32 interfaceIndex;
u8 OutEpQueueSel;
u8 OutEpNumber;
/* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
bool UsbRxHighSpeedMode;
/* 2010/11/22 MH Add for slim combo debug mode selective. */
/* This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. */
bool SlimComboDbg;
/* */
/* Add For EEPROM Efuse switch and Efuse Shadow map Setting */
/* */
u8 EepromOrEfuse;
u16 EfuseUsedBytes;
u16 BTEfuseUsedBytes;
/* Interrupt relatd register information. */
u32 SysIntrStatus;
u32 SysIntrMask;
/* */
/* 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an */
/* independent file in the future. */
/* */
/* 8723-----------------------------------------*/
enum RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */
enum RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */
enum RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */
/* 8723-----------------------------------------
* 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an */
/* independent file in the future. */
bool bMACFuncEnable;
#ifdef CONFIG_8723AU_P2P
struct P2P_PS_Offload_t p2p_ps_offload;
#endif
/* */
/* For USB Interface HAL related */
/* */
u32 UsbBulkOutSize;
/* Interrupt related register information. */
u32 IntArray[2];
u32 IntrMask[2];
/* */
/* For SDIO Interface HAL related */
/* */
/* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
u8 bMacPwrCtrlOn;
};
#define GET_HAL_DATA(__pAdapter) ((struct hal_data_8723a *)((__pAdapter)->HalData))
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
struct rxreport_8723a {
u32 pktlen:14;
u32 crc32:1;
u32 icverr:1;
u32 drvinfosize:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 physt:1;
u32 swdec:1;
u32 ls:1;
u32 fs:1;
u32 eor:1;
u32 own:1;
u32 macid:5;
u32 tid:4;
u32 hwrsvd:4;
u32 amsdu:1;
u32 paggr:1;
u32 faggr:1;
u32 a1fit:4;
u32 a2fit:4;
u32 pam:1;
u32 pwr:1;
u32 md:1;
u32 mf:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
u32 seq:12;
u32 frag:4;
u32 nextpktlen:14;
u32 nextind:1;
u32 rsvd0831:1;
u32 rxmcs:6;
u32 rxht:1;
u32 gf:1;
u32 splcp:1;
u32 bw:1;
u32 htc:1;
u32 eosp:1;
u32 bssidfit:2;
u32 rsvd1214:16;
u32 unicastwake:1;
u32 magicwake:1;
u32 pattern0match:1;
u32 pattern1match:1;
u32 pattern2match:1;
u32 pattern3match:1;
u32 pattern4match:1;
u32 pattern5match:1;
u32 pattern6match:1;
u32 pattern7match:1;
u32 pattern8match:1;
u32 pattern9match:1;
u32 patternamatch:1;
u32 patternbmatch:1;
u32 patterncmatch:1;
u32 rsvd1613:19;
u32 tsfl;
u32 bassn:12;
u32 bavld:1;
u32 rsvd2413:19;
};
/* rtl8723a_hal_init.c */
s32 rtl8723a_FirmwareDownload(struct rtw_adapter *padapter);
void rtl8723a_FirmwareSelfReset(struct rtw_adapter *padapter);
void rtl8723a_InitializeFirmwareVars(struct rtw_adapter *padapter);
void rtl8723a_InitAntenna_Selection(struct rtw_adapter *padapter);
void rtl8723a_DeinitAntenna_Selection(struct rtw_adapter *padapter);
void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter);
void rtl8723a_init_default_value(struct rtw_adapter *padapter);
s32 InitLLTTable23a(struct rtw_adapter *padapter, u32 boundary);
s32 CardDisableHWSM(struct rtw_adapter *padapter, u8 resetMCU);
s32 CardDisableWithoutHWSM(struct rtw_adapter *padapter);
/* EFuse */
u8 GetEEPROMSize8723A(struct rtw_adapter *padapter);
void Hal_InitPGData(struct rtw_adapter *padapter, u8 *PROMContent);
void Hal_EfuseParseIDCode(struct rtw_adapter *padapter, u8 *hwinfo);
void Hal_EfuseParsetxpowerinfo_8723A(struct rtw_adapter *padapter, u8 *PROMContent, bool AutoLoadFail);
void Hal_EfuseParseBTCoexistInfo_8723A(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
void Hal_EfuseParseEEPROMVer(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
void rtl8723a_EfuseParseChnlPlan(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
void Hal_EfuseParseCustomerID(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
void Hal_EfuseParseAntennaDiversity(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
void Hal_EfuseParseRateIndicationOption(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
void Hal_EfuseParseXtal_8723A(struct rtw_adapter *pAdapter, u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8723A(struct rtw_adapter *padapter, u8 *hwinfo, u8 AutoLoadFail);
void Hal_InitChannelPlan23a(struct rtw_adapter *padapter);
void rtl8723a_set_hal_ops(struct hal_ops *pHalFunc);
void SetHwReg8723A(struct rtw_adapter *padapter, u8 variable, u8 *val);
void GetHwReg8723A(struct rtw_adapter *padapter, u8 variable, u8 *val);
#ifdef CONFIG_8723AU_BT_COEXIST
void rtl8723a_SingleDualAntennaDetection(struct rtw_adapter *padapter);
#endif
/* register */
void SetBcnCtrlReg23a(struct rtw_adapter *padapter, u8 SetBits, u8 ClearBits);
void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter);
void rtl8723a_clone_haldata(struct rtw_adapter *dst_adapter, struct rtw_adapter *src_adapter);
void rtl8723a_start_thread(struct rtw_adapter *padapter);
void rtl8723a_stop_thread(struct rtw_adapter *padapter);
s32 c2h_id_filter_ccx_8723a(u8 id);
#endif

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drivers/staging/rtl8723au/include/rtl8723a_led.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTL8723A_LED_H__
#define __RTL8723A_LED_H__
#include <osdep_service.h>
#include <drv_types.h>
/* */
/* Interface to manipulate LED objects. */
/* */
void rtl8723au_InitSwLeds(struct rtw_adapter *padapter);
void rtl8723au_DeInitSwLeds(struct rtw_adapter *padapter);
void SwLedOn23a(struct rtw_adapter *padapter, struct led_8723a * pLed);
void SwLedOff23a(struct rtw_adapter *padapter, struct led_8723a * pLed);
#endif

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drivers/staging/rtl8723au/include/rtl8723a_pg.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTL8723A_PG_H__
#define __RTL8723A_PG_H__
/* EEPROM/Efuse PG Offset for 8723E/8723U/8723S */
#define EEPROM_CCK_TX_PWR_INX_8723A 0x10
#define EEPROM_HT40_1S_TX_PWR_INX_8723A 0x16
#define EEPROM_HT20_TX_PWR_INX_DIFF_8723A 0x1C
#define EEPROM_OFDM_TX_PWR_INX_DIFF_8723A 0x1F
#define EEPROM_HT40_MAX_PWR_OFFSET_8723A 0x22
#define EEPROM_HT20_MAX_PWR_OFFSET_8723A 0x25
#define EEPROM_ChannelPlan_8723A 0x28
#define EEPROM_TSSI_A_8723A 0x29
#define EEPROM_THERMAL_METER_8723A 0x2A
#define RF_OPTION1_8723A 0x2B
#define RF_OPTION2_8723A 0x2C
#define RF_OPTION3_8723A 0x2D
#define RF_OPTION4_8723A 0x2E
#define EEPROM_VERSION_8723A 0x30
#define EEPROM_CustomID_8723A 0x31
#define EEPROM_SubCustomID_8723A 0x32
#define EEPROM_XTAL_K_8723A 0x33
#define EEPROM_Chipset_8723A 0x34
/* RTL8723AE */
#define EEPROM_VID_8723AE 0x49
#define EEPROM_DID_8723AE 0x4B
#define EEPROM_SVID_8723AE 0x4D
#define EEPROM_SMID_8723AE 0x4F
#define EEPROM_MAC_ADDR_8723AE 0x67
/* RTL8723AU */
#define EEPROM_MAC_ADDR_8723AU 0xC6
#define EEPROM_VID_8723AU 0xB7
#define EEPROM_PID_8723AU 0xB9
/* RTL8723AS */
#define EEPROM_MAC_ADDR_8723AS 0xAA
/* EEPROM/Efuse Value Type */
#define EETYPE_TX_PWR 0x0
/* EEPROM/Efuse Default Value */
#define EEPROM_Default_CrystalCap_8723A 0x20
/* EEPROM/EFUSE data structure definition. */
#define MAX_CHNL_GROUP 3+9
struct txpowerinfo {
u8 CCKIndex[RF_PATH_MAX][MAX_CHNL_GROUP];
u8 HT40_1SIndex[RF_PATH_MAX][MAX_CHNL_GROUP];
u8 HT40_2SIndexDiff[RF_PATH_MAX][MAX_CHNL_GROUP];
u8 HT20IndexDiff[RF_PATH_MAX][MAX_CHNL_GROUP];
u8 OFDMIndexDiff[RF_PATH_MAX][MAX_CHNL_GROUP];
u8 HT40MaxOffset[RF_PATH_MAX][MAX_CHNL_GROUP];
u8 HT20MaxOffset[RF_PATH_MAX][MAX_CHNL_GROUP];
u8 TSSI_A[3];
u8 TSSI_B[3];
u8 TSSI_A_5G[3]; /* 5GL/5GM/5GH */
u8 TSSI_B_5G[3];
};
enum bt_ant_num {
Ant_x2 = 0,
Ant_x1 = 1
};
enum bt_cotype {
BT_2Wire = 0,
BT_ISSC_3Wire = 1,
BT_Accel = 2,
BT_CSR_BC4 = 3,
BT_CSR_BC8 = 4,
BT_RTL8756 = 5,
BT_RTL8723A = 6
};
enum bt_radioshared {
BT_Radio_Shared = 0,
BT_Radio_Individual = 1,
};
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTL8723A_RECV_H__
#define __RTL8723A_RECV_H__
#include <osdep_service.h>
#include <drv_types.h>
#define NR_RECVBUFF (4)
#define NR_PREALLOC_RECV_SKB (8)
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#define RECV_BULK_IN_ADDR 0x80
#define RECV_INT_IN_ADDR 0x81
#define PHY_RSSI_SLID_WIN_MAX 100
#define PHY_LINKQUALITY_SLID_WIN_MAX 20
struct phy_stat
{
unsigned int phydw0;
unsigned int phydw1;
unsigned int phydw2;
unsigned int phydw3;
unsigned int phydw4;
unsigned int phydw5;
unsigned int phydw6;
unsigned int phydw7;
};
/* Rx smooth factor */
#define Rx_Smooth_Factor (20)
struct interrupt_msg_format {
unsigned int C2H_MSG0;
unsigned int C2H_MSG1;
unsigned int C2H_MSG2;
unsigned int C2H_MSG3;
unsigned int HISR; /* from HISR Reg0x124, read to clear */
unsigned int HISRE;/* from HISRE Reg0x12c, read to clear */
unsigned int MSG_EX;
};
void rtl8723au_init_recvbuf(struct rtw_adapter *padapter, struct recv_buf *precvbuf);
int rtl8723au_init_recv_priv(struct rtw_adapter * padapter);
void rtl8723au_free_recv_priv(struct rtw_adapter * padapter);
void rtl8723a_process_phy_info(struct rtw_adapter *padapter, void *prframe);
void update_recvframe_attrib(struct recv_frame *precvframe, struct recv_stat *prxstat);
void update_recvframe_phyinfo(struct recv_frame *precvframe, struct phy_stat *pphy_info);
#endif

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drivers/staging/rtl8723au/include/rtl8723a_rf.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTL8723A_RF_H__
#define __RTL8723A_RF_H__
/*--------------------------Define Parameters-------------------------------*/
/* */
/* For RF 6052 Series */
/* */
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
/* */
/* RF RL6052 Series API */
/* */
void rtl8723a_phy_rf6052set_bw(struct rtw_adapter *Adapter,
enum ht_channel_width Bandwidth);
void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter,
u8* pPowerlevel);
void rtl8723a_PHY_RF6052SetOFDMTxPower(struct rtw_adapter *Adapter,
u8* pPowerLevel, u8 Channel);
/*--------------------------Exported Function prototype---------------------*/
int PHY_RF6052_Config8723A(struct rtw_adapter *Adapter);
#endif

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drivers/staging/rtl8723au/include/rtl8723a_spec.h Normal file
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drivers/staging/rtl8723au/include/rtl8723a_sreset.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _RTL8723A_SRESET_H_
#define _RTL8723A_SRESET_H_
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_sreset.h>
void rtl8723a_sreset_xmit_status_check(struct rtw_adapter *padapter);
void rtl8723a_sreset_linked_status_check(struct rtw_adapter *padapter);
#endif

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drivers/staging/rtl8723au/include/rtl8723a_xmit.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTL8723A_XMIT_H__
#define __RTL8723A_XMIT_H__
/* */
/* Queue Select Value in TxDesc */
/* */
#define QSLT_BK 0x2/* 0x01 */
#define QSLT_BE 0x0
#define QSLT_VI 0x5/* 0x4 */
#define QSLT_VO 0x7/* 0x6 */
#define QSLT_BEACON 0x10
#define QSLT_HIGH 0x11
#define QSLT_MGNT 0x12
#define QSLT_CMD 0x13
/* */
/* defined for TX DESC Operation */
/* */
#define MAX_TID (15)
/* OFFSET 0 */
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
/* OFFSET 4 */
#define PKT_OFFSET_SZ 0
#define BK BIT(6)
#define QSEL_SHT 8
#define Rate_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define PKT_OFFSET_SHT 26
#define HWPC BIT(31)
/* OFFSET 8 */
#define AGG_EN BIT(29)
/* OFFSET 12 */
#define SEQ_SHT 16
/* OFFSET 16 */
#define QoS BIT(6)
#define HW_SEQ_EN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define DATA_SHORT BIT(24)
#define DATA_BW BIT(25)
/* OFFSET 20 */
#define SGI BIT(6)
struct txdesc_8723a {
u32 pktlen:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 ls:1;
u32 fs:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 own:1;
u32 macid:5;
u32 agg_en:1;
u32 bk:1;
u32 rd_en:1;
u32 qsel:5;
u32 rd_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rate_id:4;
u32 navusehdr:1;
u32 en_desc_id:1;
u32 sectype:2;
u32 rsvd0424:2;
u32 pkt_offset:5; /* unit: 8 bytes */
u32 rsvd0431:1;
u32 rts_rc:6;
u32 data_rc:6;
u32 rsvd0812:2;
u32 bar_rty_th:2;
u32 rsvd0816:1;
u32 morefrag:1;
u32 raw:1;
u32 ccx:1;
u32 ampdu_density:3;
u32 bt_null:1;
u32 ant_sel_a:1;
u32 ant_sel_b:1;
u32 tx_ant_cck:2;
u32 tx_antl:2;
u32 tx_ant_ht:2;
u32 nextheadpage:8;
u32 tailpage:8;
u32 seq:12;
u32 cpu_handle:1;
u32 tag1:1;
u32 trigger_int:1;
u32 hwseq_en:1;
u32 rtsrate:5;
u32 ap_dcfe:1;
u32 hwseq_sel:2;
u32 userate:1;
u32 disrtsfb:1;
u32 disdatafb:1;
u32 cts2self:1;
u32 rtsen:1;
u32 hw_rts_en:1;
u32 port_id:1;
u32 rsvd1615:3;
u32 wait_dcts:1;
u32 cts2ap_en:1;
u32 data_sc:2;
u32 data_stbc:2;
u32 data_short:1;
u32 data_bw:1;
u32 rts_short:1;
u32 rts_bw:1;
u32 rts_sc:2;
u32 vcs_stbc:2;
u32 datarate:6;
u32 sgi:1;
u32 try_rate:1;
u32 data_ratefb_lmt:5;
u32 rts_ratefb_lmt:4;
u32 rty_lmt_en:1;
u32 data_rt_lmt:6;
u32 usb_txagg_num:8;
u32 txagg_a:5;
u32 txagg_b:5;
u32 use_max_len:1;
u32 max_agg_num:5;
u32 mcsg1_max_len:4;
u32 mcsg2_max_len:4;
u32 mcsg3_max_len:4;
u32 mcs7_sgi_max_len:4;
u32 checksum:16; /* TxBuffSize(PCIe)/CheckSum(USB) */
u32 mcsg4_max_len:4;
u32 mcsg5_max_len:4;
u32 mcsg6_max_len:4;
u32 mcs15_sgi_max_len:4;
};
#define txdesc_set_ccx_sw_8723a(txdesc, value) \
do { \
((struct txdesc_8723a *)(txdesc))->mcsg4_max_len = (((value)>>8) & 0x0f); \
((struct txdesc_8723a *)(txdesc))->mcs15_sgi_max_len= (((value)>>4) & 0x0f); \
((struct txdesc_8723a *)(txdesc))->mcsg6_max_len = ((value) & 0x0f); \
} while (0)
struct txrpt_ccx_8723a {
/* offset 0 */
u8 tag1:1;
u8 rsvd:4;
u8 int_bt:1;
u8 int_tri:1;
u8 int_ccx:1;
/* offset 1 */
u8 mac_id:5;
u8 pkt_drop:1;
u8 pkt_ok:1;
u8 bmc:1;
/* offset 2 */
u8 retry_cnt:6;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 3 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 5 */
u8 final_data_rate;
/* offset 6 */
u8 sw1:4;
u8 qsel:4;
/* offset 7 */
u8 sw0;
};
#define txrpt_ccx_sw_8723a(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
#define txrpt_ccx_qtime_8723a(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
void dump_txrpt_ccx_8723a(void *buf);
void handle_txrpt_ccx_8723a(struct rtw_adapter *adapter, void *buf);
void rtl8723a_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
void rtl8723a_fill_fake_txdesc(struct rtw_adapter *padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull);
s32 rtl8723au_hal_xmitframe_enqueue(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8723au_xmit_buf_handler(struct rtw_adapter *padapter);
#define hal_xmit_handler rtl8723au_xmit_buf_handler
s32 rtl8723au_init_xmit_priv(struct rtw_adapter * padapter);
void rtl8723au_free_xmit_priv(struct rtw_adapter * padapter);
s32 rtl8723au_hal_xmit(struct rtw_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8723au_mgnt_xmit(struct rtw_adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8723au_xmitframe_complete(struct rtw_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTW_AP_H_
#define __RTW_AP_H_
#include <osdep_service.h>
#include <drv_types.h>
#ifdef CONFIG_8723AU_AP_MODE
/* external function */
void rtw_indicate_sta_assoc_event23a(struct rtw_adapter *padapter, struct sta_info *psta);
void rtw_indicate_sta_disassoc_event23a(struct rtw_adapter *padapter, struct sta_info *psta);
void init_mlme_ap_info23a(struct rtw_adapter *padapter);
void free_mlme_ap_info23a(struct rtw_adapter *padapter);
/* void update_BCNTIM(struct rtw_adapter *padapter); */
void rtw_add_bcn_ie(struct rtw_adapter *padapter, struct wlan_bssid_ex *pnetwork, u8 index, u8 *data, u8 len);
void rtw_remove_bcn_ie(struct rtw_adapter *padapter, struct wlan_bssid_ex *pnetwork, u8 index);
void update_beacon23a(struct rtw_adapter *padapter, u8 ie_id, u8 *oui, u8 tx);
void add_RATid23a(struct rtw_adapter *padapter, struct sta_info *psta, u8 rssi_level);
void expire_timeout_chk23a(struct rtw_adapter *padapter);
void update_sta_info23a_apmode23a(struct rtw_adapter *padapter, struct sta_info *psta);
int rtw_check_beacon_data23a(struct rtw_adapter *padapter, u8 *pbuf, int len);
void rtw_ap_restore_network(struct rtw_adapter *padapter);
void rtw_set_macaddr_acl23a(struct rtw_adapter *padapter, int mode);
int rtw_acl_add_sta23a(struct rtw_adapter *padapter, u8 *addr);
int rtw_acl_remove_sta23a(struct rtw_adapter *padapter, u8 *addr);
void associated_clients_update23a(struct rtw_adapter *padapter, u8 updated);
void bss_cap_update_on_sta_join23a(struct rtw_adapter *padapter, struct sta_info *psta);
u8 bss_cap_update_on_sta_leave23a(struct rtw_adapter *padapter, struct sta_info *psta);
void sta_info_update23a(struct rtw_adapter *padapter, struct sta_info *psta);
void ap_sta_info_defer_update23a(struct rtw_adapter *padapter, struct sta_info *psta);
u8 ap_free_sta23a(struct rtw_adapter *padapter, struct sta_info *psta, bool active, u16 reason);
int rtw_sta_flush23a(struct rtw_adapter *padapter);
int rtw_ap_inform_ch_switch23a(struct rtw_adapter *padapter, u8 new_ch, u8 ch_offset);
void start_ap_mode23a(struct rtw_adapter *padapter);
void stop_ap_mode23a(struct rtw_adapter *padapter);
#endif /* end of CONFIG_8723AU_AP_MODE */
#endif

835
drivers/staging/rtl8723au/include/rtw_cmd.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTW_CMD_H_
#define __RTW_CMD_H_
#include <wlan_bssdef.h>
#include <rtw_rf.h>
#include <rtw_led.h>
#define C2H_MEM_SZ (16*1024)
#include <osdep_service.h>
#include <ieee80211.h> /* <ieee80211/ieee80211.h> */
#define FREE_CMDOBJ_SZ 128
#define MAX_CMDSZ 1024
#define MAX_RSPSZ 512
#define MAX_EVTSZ 1024
#define CMDBUFF_ALIGN_SZ 512
struct cmd_obj {
struct rtw_adapter *padapter;
u16 cmdcode;
u8 res;
u8 *parmbuf;
u32 cmdsz;
u8 *rsp;
u32 rspsz;
/* struct semaphore cmd_sem; */
struct list_head list;
};
struct cmd_priv {
struct semaphore cmd_queue_sema;
/* struct semaphore cmd_done_sema; */
struct semaphore terminate_cmdthread_sema;
struct rtw_queue cmd_queue;
u8 cmd_seq;
u8 *cmd_buf; /* shall be non-paged, and 4 bytes aligned */
u8 *cmd_allocated_buf;
u8 *rsp_buf; /* shall be non-paged, and 4 bytes aligned */
u8 *rsp_allocated_buf;
u32 cmd_issued_cnt;
u32 cmd_done_cnt;
u32 rsp_cnt;
u8 cmdthd_running;
struct rtw_adapter *padapter;
};
#define C2H_QUEUE_MAX_LEN 10
struct evt_priv {
struct work_struct c2h_wk;
bool c2h_wk_alive;
struct rtw_cbuf *c2h_queue;
atomic_t event_seq;
u8 *evt_buf; /* shall be non-paged, and 4 bytes aligned */
u8 *evt_allocated_buf;
u32 evt_done_cnt;
};
#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \
do {\
INIT_LIST_HEAD(&pcmd->list);\
pcmd->cmdcode = code;\
pcmd->parmbuf = (u8 *)(pparm);\
pcmd->cmdsz = sizeof (*pparm);\
pcmd->rsp = NULL;\
pcmd->rspsz = 0;\
} while(0)
struct c2h_evt_hdr {
u8 id:4;
u8 plen:4;
u8 seq;
u8 payload[0];
};
#define c2h_evt_exist(c2h_evt) ((c2h_evt)->id || (c2h_evt)->plen)
u32 rtw_enqueue_cmd23a(struct cmd_priv *pcmdpriv, struct cmd_obj *obj);
void rtw_free_cmd_obj23a(struct cmd_obj *pcmd);
int rtw_cmd_thread23a(void *context);
int rtw_init_cmd_priv23a(struct cmd_priv *pcmdpriv);
void rtw_free_cmd_priv23a (struct cmd_priv *pcmdpriv);
u32 rtw_init_evt_priv23a (struct evt_priv *pevtpriv);
void rtw_free_evt_priv23a (struct evt_priv *pevtpriv);
void rtw_cmd_clr_isr23a(struct cmd_priv *pcmdpriv);
void rtw_evt_notify_isr(struct evt_priv *pevtpriv);
#ifdef CONFIG_8723AU_P2P
u8 p2p_protocol_wk_cmd23a(struct rtw_adapter*padapter, int intCmdType );
#endif /* CONFIG_8723AU_P2P */
enum rtw_drvextra_cmd_id
{
NONE_WK_CID,
DYNAMIC_CHK_WK_CID,
DM_CTRL_WK_CID,
PBC_POLLING_WK_CID,
POWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */
LPS_CTRL_WK_CID,
ANT_SELECT_WK_CID,
P2P_PS_WK_CID,
P2P_PROTO_WK_CID,
CHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */
C2H_WK_CID,
RTP_TIMER_CFG_WK_CID,
MAX_WK_CID
};
enum LPS_CTRL_TYPE
{
LPS_CTRL_SCAN=0,
LPS_CTRL_JOINBSS=1,
LPS_CTRL_CONNECT=2,
LPS_CTRL_DISCONNECT=3,
LPS_CTRL_SPECIAL_PACKET=4,
LPS_CTRL_LEAVE=5,
};
enum RFINTFS {
SWSI,
HWSI,
HWPI,
};
/*
Caller Mode: Infra, Ad-HoC(C)
Notes: To enter USB suspend mode
Command Mode
*/
struct usb_suspend_parm {
u32 action;/* 1: sleep, 0:resume */
};
/*
Caller Mode: Infra, Ad-HoC
Notes: To join a known BSS.
Command-Event Mode
*/
/*
Caller Mode: Infra, Ad-HoC(C)
Notes: To disconnect the current associated BSS
Command Mode
*/
struct disconnect_parm {
u32 deauth_timeout_ms;
};
struct setopmode_parm {
u8 mode;
u8 rsvd[3];
};
/*
Caller Mode: AP, Ad-HoC, Infra
Notes: To ask RTL8711 performing site-survey
Command-Event Mode
*/
#define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */
#define RTW_CHANNEL_SCAN_AMOUNT (14+37)
struct sitesurvey_parm {
int scan_mode; /* active: 1, passive: 0 */
u8 ssid_num;
u8 ch_num;
struct cfg80211_ssid ssid[RTW_SSID_SCAN_AMOUNT];
struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
};
/*
Caller Mode: Any
Notes: To set the auth type of RTL8711. open/shared/802.1x
Command Mode
*/
struct setauth_parm {
u8 mode; /* 0: legacy open, 1: legacy shared 2: 802.1x */
u8 _1x; /* 0: PSK, 1: TLS */
u8 rsvd[2];
};
/*
Caller Mode: Infra
a. algorithm: wep40, wep104, tkip & aes
b. keytype: grp key/unicast key
c. key contents
when shared key ==> keyid is the camid
when 802.1x ==> keyid [0:1] ==> grp key
when 802.1x ==> keyid > 2 ==> unicast key
*/
struct setkey_parm {
u8 algorithm; /* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */
u8 keyid;
u8 grpkey; /* 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x */
u8 set_tx; /* 1: main tx key for wep. 0: other key. */
u8 key[16]; /* this could be 40 or 104 */
};
/*
When in AP or Ad-Hoc mode, this is used to
allocate an sw/hw entry for a newly associated sta.
Command
when shared key ==> algorithm/keyid
*/
struct set_stakey_parm {
u8 addr[ETH_ALEN];
u8 algorithm;
u8 id;/* currently for erasing cam entry if algorithm == _NO_PRIVACY_ */
u8 key[16];
};
struct set_stakey_rsp {
u8 addr[ETH_ALEN];
u8 keyid;
u8 rsvd;
};
/*
Caller Ad-Hoc/AP
Command -Rsp(AID == CAMID) mode
This is to force fw to add an sta_data entry per driver's request.
FW will write an cam entry associated with it.
*/
struct set_assocsta_parm {
u8 addr[ETH_ALEN];
};
struct set_assocsta_rsp {
u8 cam_id;
u8 rsvd[3];
};
/*
Caller Ad-Hoc/AP
Command mode
This is to force fw to del an sta_data entry per driver's request
FW will invalidate the cam entry associated with it.
*/
struct del_assocsta_parm {
u8 addr[ETH_ALEN];
};
/*
Caller Mode: AP/Ad-HoC(M)
Notes: To notify fw that given staid has changed its power state
Command Mode
*/
struct setstapwrstate_parm {
u8 staid;
u8 status;
u8 hwaddr[6];
};
/*
Caller Mode: Any
Notes: To setup the basic rate of RTL8711
Command Mode
*/
struct setbasicrate_parm {
u8 basicrates[NumRates];
};
/*
Caller Mode: Any
Notes: To read the current basic rate
Command-Rsp Mode
*/
struct getbasicrate_parm {
u32 rsvd;
};
struct getbasicrate_rsp {
u8 basicrates[NumRates];
};
/*
Caller Mode: Any
Notes: To setup the data rate of RTL8711
Command Mode
*/
struct setdatarate_parm {
u8 mac_id;
u8 datarates[NumRates];
};
/*
Caller Mode: Any
Notes: To read the current data rate
Command-Rsp Mode
*/
struct getdatarate_parm {
u32 rsvd;
};
struct getdatarate_rsp {
u8 datarates[NumRates];
};
/*
Caller Mode: Any
AP: AP can use the info for the contents of beacon frame
Infra: STA can use the info when sitesurveying
Ad-HoC(M): Like AP
Ad-HoC(C): Like STA
Notes: To set the phy capability of the NIC
Command Mode
*/
struct setphyinfo_parm {
struct regulatory_class class_sets[NUM_REGULATORYS];
u8 status;
};
struct getphyinfo_parm {
u32 rsvd;
};
struct getphyinfo_rsp {
struct regulatory_class class_sets[NUM_REGULATORYS];
u8 status;
};
/*
Caller Mode: Any
Notes: To set the channel/modem/band
This command will be used when channel/modem/band is changed.
Command Mode
*/
struct setphy_parm {
u8 rfchannel;
u8 modem;
};
/*
Caller Mode: Any
Notes: To get the current setting of channel/modem/band
Command-Rsp Mode
*/
struct getphy_parm {
u32 rsvd;
};
struct getphy_rsp {
u8 rfchannel;
u8 modem;
};
struct readBB_parm {
u8 offset;
};
struct readBB_rsp {
u8 value;
};
struct readTSSI_parm {
u8 offset;
};
struct readTSSI_rsp {
u8 value;
};
struct writeBB_parm {
u8 offset;
u8 value;
};
struct readRF_parm {
u8 offset;
};
struct readRF_rsp {
u32 value;
};
struct writeRF_parm {
u32 offset;
u32 value;
};
struct getrfintfs_parm {
u8 rfintfs;
};
struct Tx_Beacon_param
{
struct wlan_bssid_ex network;
};
/* CMD param Formart for driver extra cmd handler */
struct drvextra_cmd_parm {
int ec_id; /* extra cmd id */
int type_size; /* Can use this field as the type id or command size */
unsigned char *pbuf;
};
/*------------------- Below are used for RF/BB tunning ---------------------*/
struct setantenna_parm {
u8 tx_antset;
u8 rx_antset;
u8 tx_antenna;
u8 rx_antenna;
};
struct enrateadaptive_parm {
u32 en;
};
struct settxagctbl_parm {
u32 txagc[MAX_RATES_LENGTH];
};
struct gettxagctbl_parm {
u32 rsvd;
};
struct gettxagctbl_rsp {
u32 txagc[MAX_RATES_LENGTH];
};
struct setagcctrl_parm {
u32 agcctrl; /* 0: pure hw, 1: fw */
};
struct setssup_parm {
u32 ss_ForceUp[MAX_RATES_LENGTH];
};
struct getssup_parm {
u32 rsvd;
};
struct getssup_rsp {
u8 ss_ForceUp[MAX_RATES_LENGTH];
};
struct setssdlevel_parm {
u8 ss_DLevel[MAX_RATES_LENGTH];
};
struct getssdlevel_parm {
u32 rsvd;
};
struct getssdlevel_rsp {
u8 ss_DLevel[MAX_RATES_LENGTH];
};
struct setssulevel_parm {
u8 ss_ULevel[MAX_RATES_LENGTH];
};
struct getssulevel_parm {
u32 rsvd;
};
struct getssulevel_rsp {
u8 ss_ULevel[MAX_RATES_LENGTH];
};
struct setcountjudge_parm {
u8 count_judge[MAX_RATES_LENGTH];
};
struct getcountjudge_parm {
u32 rsvd;
};
struct getcountjudge_rsp {
u8 count_judge[MAX_RATES_LENGTH];
};
struct setratable_parm {
u8 ss_ForceUp[NumRates];
u8 ss_ULevel[NumRates];
u8 ss_DLevel[NumRates];
u8 count_judge[NumRates];
};
struct getratable_parm {
uint rsvd;
};
struct getratable_rsp {
u8 ss_ForceUp[NumRates];
u8 ss_ULevel[NumRates];
u8 ss_DLevel[NumRates];
u8 count_judge[NumRates];
};
/* to get TX,RX retry count */
struct gettxretrycnt_parm{
unsigned int rsvd;
};
struct gettxretrycnt_rsp{
unsigned long tx_retrycnt;
};
struct getrxretrycnt_parm{
unsigned int rsvd;
};
struct getrxretrycnt_rsp{
unsigned long rx_retrycnt;
};
/* to get BCNOK,BCNERR count */
struct getbcnokcnt_parm{
unsigned int rsvd;
};
struct getbcnokcnt_rsp{
unsigned long bcnokcnt;
};
struct getbcnerrcnt_parm{
unsigned int rsvd;
};
struct getbcnerrcnt_rsp{
unsigned long bcnerrcnt;
};
/* to get current TX power level */
struct getcurtxpwrlevel_parm{
unsigned int rsvd;
};
struct getcurtxpwrlevel_rsp{
unsigned short tx_power;
};
struct setprobereqextraie_parm {
unsigned char e_id;
unsigned char ie_len;
unsigned char ie[0];
};
struct setassocreqextraie_parm {
unsigned char e_id;
unsigned char ie_len;
unsigned char ie[0];
};
struct setproberspextraie_parm {
unsigned char e_id;
unsigned char ie_len;
unsigned char ie[0];
};
struct setassocrspextraie_parm {
unsigned char e_id;
unsigned char ie_len;
unsigned char ie[0];
};
struct addBaReq_parm {
unsigned int tid;
u8 addr[ETH_ALEN];
};
/*H2C Handler index: 46 */
struct set_ch_parm {
u8 ch;
u8 bw;
u8 ch_offset;
};
/*H2C Handler index: 59 */
struct SetChannelPlan_param {
u8 channel_plan;
};
/*H2C Handler index: 60 */
struct LedBlink_param {
struct led_8723a *pLed;
};
/*H2C Handler index: 61 */
struct SetChannelSwitch_param {
u8 new_ch_no;
};
/*H2C Handler index: 62 */
struct TDLSoption_param {
u8 addr[ETH_ALEN];
u8 option;
};
#define GEN_CMD_CODE(cmd) cmd ## _CMD_
/*
Result:
0x00: success
0x01: sucess, and check Response.
0x02: cmd ignored due to duplicated sequcne number
0x03: cmd dropped due to invalid cmd code
0x04: reserved.
*/
#define H2C_RSP_OFFSET 512
#define H2C_SUCCESS 0x00
#define H2C_SUCCESS_RSP 0x01
#define H2C_DUPLICATED 0x02
#define H2C_DROPPED 0x03
#define H2C_PARAMETERS_ERROR 0x04
#define H2C_REJECTED 0x05
#define H2C_CMD_OVERFLOW 0x06
#define H2C_RESERVED 0x07
u8 rtw_setassocsta_cmd(struct rtw_adapter *padapter, u8 *mac_addr);
u8 rtw_setstandby_cmd(struct rtw_adapter *padapter, uint action);
u8 rtw_sitesurvey_cmd23a(struct rtw_adapter *padapter, struct cfg80211_ssid *ssid, int ssid_num, struct rtw_ieee80211_channel *ch, int ch_num);
u8 rtw_createbss_cmd23a(struct rtw_adapter *padapter);
u8 rtw_createbss_cmd23a_ex(struct rtw_adapter *padapter, unsigned char *pbss, unsigned int sz);
u8 rtw_setphy_cmd(struct rtw_adapter *padapter, u8 modem, u8 ch);
u8 rtw_setstakey_cmd23a(struct rtw_adapter *padapter, u8 *psta, u8 unicast_key);
u8 rtw_clearstakey_cmd23a(struct rtw_adapter *padapter, u8 *psta, u8 entry, u8 enqueue);
u8 rtw_joinbss_cmd23a(struct rtw_adapter *padapter, struct wlan_network* pnetwork);
u8 rtw_disassoc_cmd23a(struct rtw_adapter *padapter, u32 deauth_timeout_ms, bool enqueue);
u8 rtw_setopmode_cmd23a(struct rtw_adapter *padapter, enum ndis_802_11_net_infra networktype);
u8 rtw_setdatarate_cmd(struct rtw_adapter *padapter, u8 *rateset);
u8 rtw_setbasicrate_cmd(struct rtw_adapter *padapter, u8 *rateset);
u8 rtw_setbbreg_cmd(struct rtw_adapter * padapter, u8 offset, u8 val);
u8 rtw_setrfreg_cmd(struct rtw_adapter * padapter, u8 offset, u32 val);
u8 rtw_getbbreg_cmd(struct rtw_adapter * padapter, u8 offset, u8 * pval);
u8 rtw_getrfreg_cmd(struct rtw_adapter * padapter, u8 offset, u8 * pval);
u8 rtw_setrfintfs_cmd(struct rtw_adapter *padapter, u8 mode);
u8 rtw_setrttbl_cmd(struct rtw_adapter *padapter, struct setratable_parm *prate_table);
u8 rtw_getrttbl_cmd(struct rtw_adapter *padapter, struct getratable_rsp *pval);
u8 rtw_gettssi_cmd(struct rtw_adapter *padapter, u8 offset,u8 *pval);
u8 rtw_setfwdig_cmd(struct rtw_adapter*padapter, u8 type);
u8 rtw_setfwra_cmd(struct rtw_adapter*padapter, u8 type);
u8 rtw_addbareq_cmd23a(struct rtw_adapter*padapter, u8 tid, u8 *addr);
u8 rtw_dynamic_chk_wk_cmd23a(struct rtw_adapter *adapter);
u8 rtw_lps_ctrl_wk_cmd23a(struct rtw_adapter*padapter, u8 lps_ctrl_type, u8 enqueue);
u8 rtw_ps_cmd23a(struct rtw_adapter*padapter);
#ifdef CONFIG_8723AU_AP_MODE
u8 rtw_chk_hi_queue_cmd23a(struct rtw_adapter*padapter);
#endif
u8 rtw_set_ch_cmd23a(struct rtw_adapter*padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue);
u8 rtw_set_chplan_cmd(struct rtw_adapter*padapter, u8 chplan, u8 enqueue);
u8 rtw_led_blink_cmd(struct rtw_adapter*padapter, struct led_8723a *pLed);
u8 rtw_set_csa_cmd(struct rtw_adapter*padapter, u8 new_ch_no);
u8 rtw_tdls_cmd(struct rtw_adapter*padapter, u8 *addr, u8 option);
u8 rtw_c2h_wk_cmd23a(struct rtw_adapter *padapter, u8 *c2h_evt);
u8 rtw_drvextra_cmd_hdl23a(struct rtw_adapter *padapter, unsigned char *pbuf);
void rtw_survey_cmd_callback23a(struct rtw_adapter *padapter, struct cmd_obj *pcmd);
void rtw_disassoc_cmd23a_callback(struct rtw_adapter *padapter, struct cmd_obj *pcmd);
void rtw_joinbss_cmd23a_callback(struct rtw_adapter *padapter, struct cmd_obj *pcmd);
void rtw_createbss_cmd23a_callback(struct rtw_adapter *padapter, struct cmd_obj *pcmd);
void rtw_getbbrfreg_cmdrsp_callback23a(struct rtw_adapter *padapter, struct cmd_obj *pcmd);
void rtw_readtssi_cmdrsp_callback(struct rtw_adapter* padapter, struct cmd_obj *pcmd);
void rtw_setstaKey_cmdrsp_callback23a(struct rtw_adapter *padapter, struct cmd_obj *pcmd);
void rtw_setassocsta_cmdrsp_callback23a(struct rtw_adapter *padapter, struct cmd_obj *pcmd);
void rtw_getrttbl_cmdrsp_callback(struct rtw_adapter *padapter, struct cmd_obj *pcmd);
struct _cmd_callback {
u32 cmd_code;
void (*callback)(struct rtw_adapter *padapter, struct cmd_obj *cmd);
};
enum rtw_h2c_cmd {
GEN_CMD_CODE(_Read_MACREG) , /*0*/
GEN_CMD_CODE(_Write_MACREG) ,
GEN_CMD_CODE(_Read_BBREG) ,
GEN_CMD_CODE(_Write_BBREG) ,
GEN_CMD_CODE(_Read_RFREG) ,
GEN_CMD_CODE(_Write_RFREG) , /*5*/
GEN_CMD_CODE(_Read_EEPROM) ,
GEN_CMD_CODE(_Write_EEPROM) ,
GEN_CMD_CODE(_Read_EFUSE) ,
GEN_CMD_CODE(_Write_EFUSE) ,
GEN_CMD_CODE(_Read_CAM) , /*10*/
GEN_CMD_CODE(_Write_CAM) ,
GEN_CMD_CODE(_setBCNITV),
GEN_CMD_CODE(_setMBIDCFG),
GEN_CMD_CODE(_JoinBss), /*14*/
GEN_CMD_CODE(_DisConnect) , /*15*/
GEN_CMD_CODE(_CreateBss) ,
GEN_CMD_CODE(_SetOpMode) ,
GEN_CMD_CODE(_SiteSurvey), /*18*/
GEN_CMD_CODE(_SetAuth) ,
GEN_CMD_CODE(_SetKey) , /*20*/
GEN_CMD_CODE(_SetStaKey) ,
GEN_CMD_CODE(_SetAssocSta) ,
GEN_CMD_CODE(_DelAssocSta) ,
GEN_CMD_CODE(_SetStaPwrState) ,
GEN_CMD_CODE(_SetBasicRate) , /*25*/
GEN_CMD_CODE(_GetBasicRate) ,
GEN_CMD_CODE(_SetDataRate) ,
GEN_CMD_CODE(_GetDataRate) ,
GEN_CMD_CODE(_SetPhyInfo) ,
GEN_CMD_CODE(_GetPhyInfo) , /*30*/
GEN_CMD_CODE(_SetPhy) ,
GEN_CMD_CODE(_GetPhy) ,
GEN_CMD_CODE(_readRssi) ,
GEN_CMD_CODE(_readGain) ,
GEN_CMD_CODE(_SetAtim) , /*35*/
GEN_CMD_CODE(_SetPwrMode) ,
GEN_CMD_CODE(_JoinbssRpt),
GEN_CMD_CODE(_SetRaTable) ,
GEN_CMD_CODE(_GetRaTable) ,
GEN_CMD_CODE(_GetCCXReport), /*40*/
GEN_CMD_CODE(_GetDTMReport),
GEN_CMD_CODE(_GetTXRateStatistics),
GEN_CMD_CODE(_SetUsbSuspend),
GEN_CMD_CODE(_SetH2cLbk),
GEN_CMD_CODE(_AddBAReq) , /*45*/
GEN_CMD_CODE(_SetChannel), /*46*/
GEN_CMD_CODE(_SetTxPower),
GEN_CMD_CODE(_SwitchAntenna),
GEN_CMD_CODE(_SetCrystalCap),
GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/
GEN_CMD_CODE(_SetSingleToneTx),/*51*/
GEN_CMD_CODE(_SetCarrierSuppressionTx),
GEN_CMD_CODE(_SetContinuousTx),
GEN_CMD_CODE(_SwitchBandwidth), /*54*/
GEN_CMD_CODE(_TX_Beacon), /*55*/
GEN_CMD_CODE(_Set_MLME_EVT), /*56*/
GEN_CMD_CODE(_Set_Drv_Extra), /*57*/
GEN_CMD_CODE(_Set_H2C_MSG), /*58*/
GEN_CMD_CODE(_SetChannelPlan), /*59*/
GEN_CMD_CODE(_LedBlink), /*60*/
GEN_CMD_CODE(_SetChannelSwitch), /*61*/
GEN_CMD_CODE(_TDLS), /*62*/
MAX_H2CCMD
};
#define _GetBBReg_CMD_ _Read_BBREG_CMD_
#define _SetBBReg_CMD_ _Write_BBREG_CMD_
#define _GetRFReg_CMD_ _Read_RFREG_CMD_
#define _SetRFReg_CMD_ _Write_RFREG_CMD_
extern struct _cmd_callback rtw_cmd_callback[];
#endif /* _CMD_H_ */

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drivers/staging/rtl8723au/include/rtw_debug.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*
******************************************************************************/
#ifndef __RTW_DEBUG_H__
#define __RTW_DEBUG_H__
#include <osdep_service.h>
#include <drv_types.h>
#define _drv_always_ 1
#define _drv_emerg_ 2
#define _drv_alert_ 3
#define _drv_err_ 4
#define _drv_warning_ 5
#define _drv_notice_ 6
#define _drv_info_ 7
#define _drv_debug_ 8
#define _module_rtl871x_xmit_c_ BIT(0)
#define _module_xmit_osdep_c_ BIT(1)
#define _module_rtl871x_recv_c_ BIT(2)
#define _module_recv_osdep_c_ BIT(3)
#define _module_rtl871x_mlme_c_ BIT(4)
#define _module_mlme_osdep_c_ BIT(5)
#define _module_rtl871x_sta_mgt_c_ BIT(6)
#define _module_rtl871x_cmd_c_ BIT(7)
#define _module_cmd_osdep_c_ BIT(8)
#define _module_rtl871x_io_c_ BIT(9)
#define _module_io_osdep_c_ BIT(10)
#define _module_os_intfs_c_ BIT(11)
#define _module_rtl871x_security_c_ BIT(12)
#define _module_rtl871x_eeprom_c_ BIT(13)
#define _module_hal_init_c_ BIT(14)
#define _module_hci_hal_init_c_ BIT(15)
#define _module_rtl871x_ioctl_c_ BIT(16)
#define _module_rtl871x_ioctl_set_c_ BIT(17)
#define _module_rtl871x_ioctl_query_c_ BIT(18)
#define _module_rtl871x_pwrctrl_c_ BIT(19)
#define _module_hci_intfs_c_ BIT(20)
#define _module_hci_ops_c_ BIT(21)
#define _module_osdep_service_c_ BIT(22)
#define _module_mp_ BIT(23)
#define _module_hci_ops_os_c_ BIT(24)
#define _module_rtl871x_ioctl_os_c BIT(25)
#define _module_rtl8712_cmd_c_ BIT(26)
#define _module_rtl8192c_xmit_c_ BIT(28)
#define _module_hal_xmit_c_ BIT(28) /* duplication intentional */
#define _module_efuse_ BIT(29)
#define _module_rtl8712_recv_c_ BIT(30)
#define _module_rtl8712_led_c_ BIT(31)
#undef _MODULE_DEFINE_
#if defined _RTW_XMIT_C_
#define _MODULE_DEFINE_ _module_rtl871x_xmit_c_
#elif defined _XMIT_OSDEP_C_
#define _MODULE_DEFINE_ _module_xmit_osdep_c_
#elif defined _RTW_RECV_C_
#define _MODULE_DEFINE_ _module_rtl871x_recv_c_
#elif defined _RECV_OSDEP_C_
#define _MODULE_DEFINE_ _module_recv_osdep_c_
#elif defined _RTW_MLME_C_
#define _MODULE_DEFINE_ _module_rtl871x_mlme_c_
#elif defined _MLME_OSDEP_C_
#define _MODULE_DEFINE_ _module_mlme_osdep_c_
#elif defined _RTW_MLME_EXT_C_
#define _MODULE_DEFINE_ 1
#elif defined _RTW_STA_MGT_C_
#define _MODULE_DEFINE_ _module_rtl871x_sta_mgt_c_
#elif defined _RTW_CMD_C_
#define _MODULE_DEFINE_ _module_rtl871x_cmd_c_
#elif defined _CMD_OSDEP_C_
#define _MODULE_DEFINE_ _module_cmd_osdep_c_
#elif defined _RTW_IO_C_
#define _MODULE_DEFINE_ _module_rtl871x_io_c_
#elif defined _IO_OSDEP_C_
#define _MODULE_DEFINE_ _module_io_osdep_c_
#elif defined _OS_INTFS_C_
#define _MODULE_DEFINE_ _module_os_intfs_c_
#elif defined _RTW_SECURITY_C_
#define _MODULE_DEFINE_ _module_rtl871x_security_c_
#elif defined _RTW_EEPROM_C_
#define _MODULE_DEFINE_ _module_rtl871x_eeprom_c_
#elif defined _HAL_INTF_C_
#define _MODULE_DEFINE_ _module_hal_init_c_
#elif (defined _HCI_HAL_INIT_C_) || (defined _SDIO_HALINIT_C_)
#define _MODULE_DEFINE_ _module_hci_hal_init_c_
#elif defined _RTL871X_IOCTL_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_c_
#elif defined _RTL871X_IOCTL_SET_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_set_c_
#elif defined _RTL871X_IOCTL_QUERY_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_query_c_
#elif defined _RTL871X_PWRCTRL_C_
#define _MODULE_DEFINE_ _module_rtl871x_pwrctrl_c_
#elif defined _RTW_PWRCTRL_C_
#define _MODULE_DEFINE_ 1
#elif defined _HCI_INTF_C_
#define _MODULE_DEFINE_ _module_hci_intfs_c_
#elif defined _HCI_OPS_C_
#define _MODULE_DEFINE_ _module_hci_ops_c_
#elif defined _SDIO_OPS_C_
#define _MODULE_DEFINE_ 1
#elif defined _OSDEP_HCI_INTF_C_
#define _MODULE_DEFINE_ _module_hci_intfs_c_
#elif defined _OSDEP_SERVICE_C_
#define _MODULE_DEFINE_ _module_osdep_service_c_
#elif defined _HCI_OPS_OS_C_
#define _MODULE_DEFINE_ _module_hci_ops_os_c_
#elif defined _RTL871X_IOCTL_LINUX_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_os_c
#elif defined _RTL8712_CMD_C_
#define _MODULE_DEFINE_ _module_rtl8712_cmd_c_
#elif defined _RTL8192C_XMIT_C_
#define _MODULE_DEFINE_ 1
#elif defined _RTL8723AS_XMIT_C_
#define _MODULE_DEFINE_ 1
#elif defined _RTL8712_RECV_C_
#define _MODULE_DEFINE_ _module_rtl8712_recv_c_
#elif defined _RTL8192CU_RECV_C_
#define _MODULE_DEFINE_ _module_rtl8712_recv_c_
#elif defined _RTL871X_MLME_EXT_C_
#define _MODULE_DEFINE_ _module_mlme_osdep_c_
#elif defined _RTW_MP_C_
#define _MODULE_DEFINE_ _module_mp_
#elif defined _RTW_MP_IOCTL_C_
#define _MODULE_DEFINE_ _module_mp_
#elif defined _RTW_EFUSE_C_
#define _MODULE_DEFINE_ _module_efuse_
#endif
#define DRIVER_PREFIX "RTL8723AU: "
#define DEBUG_LEVEL (_drv_err_)
#define DBG_8723A_LEVEL(_level, fmt, arg...) \
do { \
if (_level <= GlobalDebugLevel23A) \
pr_info(DRIVER_PREFIX"ERROR " fmt, ##arg);\
} while (0)
#define DBG_8723A(...) \
do { \
if (_drv_err_ <= GlobalDebugLevel23A) \
pr_info(DRIVER_PREFIX __VA_ARGS__); \
} while (0)
#define MSG_8723A(...) \
do { \
if (_drv_err_ <= GlobalDebugLevel23A) \
pr_info(DRIVER_PREFIX __VA_ARGS__); \
} while (0)
extern u32 GlobalDebugLevel23A;
#define RT_TRACE(_Comp, _Level, Fmt) \
do { \
if (_Level <= GlobalDebugLevel23A) { \
pr_info("%s [0x%08x,%d]", DRIVER_PREFIX, \
(unsigned int)_Comp, _Level); \
pr_info Fmt; \
} \
} while (0)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, \
_HexDataLen) \
if (_Level <= GlobalDebugLevel23A) { \
int __i; \
u8 *ptr = (u8 *)_HexData; \
pr_info("%s", DRIVER_PREFIX); \
pr_info(_TitleString); \
for (__i = 0; __i < (int)_HexDataLen; __i++) { \
printk("%02X%s", ptr[__i], \
(((__i + 1) % 4) == 0) ? " " : " "); \
if (((__i + 1) % 16) == 0) \
printk("\n"); \
} \
printk("\n"); \
}
#endif /* __RTW_DEBUG_H__ */

135
drivers/staging/rtl8723au/include/rtw_eeprom.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __RTW_EEPROM_H__
#define __RTW_EEPROM_H__
#include <osdep_service.h>
#include <drv_types.h>
#define RTL8712_EEPROM_ID 0x8712
/* define EEPROM_MAX_SIZE 256 */
#define HWSET_MAX_SIZE_512 512
#define EEPROM_MAX_SIZE HWSET_MAX_SIZE_512
#define CLOCK_RATE 50 /* 100us */
/* EEPROM opcodes */
#define EEPROM_READ_OPCODE 06
#define EEPROM_WRITE_OPCODE 05
#define EEPROM_ERASE_OPCODE 07
#define EEPROM_EWEN_OPCODE 19 /* Erase/write enable */
#define EEPROM_EWDS_OPCODE 16 /* Erase/write disable */
/* Country codes */
#define USA 0x555320
#define EUROPE 0x1 /* temp, should be provided later */
#define JAPAN 0x2 /* temp, should be provided later */
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_ALPHA 0x1
#define EEPROM_CID_Senao 0x3
#define EEPROM_CID_NetCore 0x5
#define EEPROM_CID_CAMEO 0X8
#define EEPROM_CID_SITECOM 0x9
#define EEPROM_CID_COREGA 0xB
#define EEPROM_CID_EDIMAX_BELKIN 0xC
#define EEPROM_CID_SERCOMM_BELKIN 0xE
#define EEPROM_CID_CAMEO1 0xF
#define EEPROM_CID_WNC_COREGA 0x12
#define EEPROM_CID_CLEVO 0x13
#define EEPROM_CID_WHQL 0xFE /* added by chiyoko for dtm, 20090108 */
/* */
/* Customer ID, note that: */
/* This variable is initiailzed through EEPROM or registry, */
/* however, its definition may be different with that in EEPROM for */
/* EEPROM size consideration. So, we have to perform proper translation between them. */
/* Besides, CustomerID of registry has precedence of that of EEPROM. */
/* defined below. 060703, by rcnjko. */
/* */
enum rt_customer_id
{
RT_CID_DEFAULT = 0,
RT_CID_8187_ALPHA0 = 1,
RT_CID_8187_SERCOMM_PS = 2,
RT_CID_8187_HW_LED = 3,
RT_CID_8187_NETGEAR = 4,
RT_CID_WHQL = 5,
RT_CID_819x_CAMEO = 6,
RT_CID_819x_RUNTOP = 7,
RT_CID_819x_Senao = 8,
RT_CID_TOSHIBA = 9, /* Merge by Jacken, 2008/01/31. */
RT_CID_819x_Netcore = 10,
RT_CID_Nettronix = 11,
RT_CID_DLINK = 12,
RT_CID_PRONET = 13,
RT_CID_COREGA = 14,
RT_CID_CHINA_MOBILE = 15,
RT_CID_819x_ALPHA = 16,
RT_CID_819x_Sitecom = 17,
RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. */
RT_CID_819x_Lenovo = 19,
RT_CID_819x_QMI = 20,
RT_CID_819x_Edimax_Belkin = 21,
RT_CID_819x_Sercomm_Belkin = 22,
RT_CID_819x_CAMEO1 = 23,
RT_CID_819x_MSI = 24,
RT_CID_819x_Acer = 25,
RT_CID_819x_AzWave_ASUS = 26,
RT_CID_819x_AzWave = 27, /* For AzWave in PCIe, The ID is AzWave use and not only Asus */
RT_CID_819x_HP = 28,
RT_CID_819x_WNC_COREGA = 29,
RT_CID_819x_Arcadyan_Belkin = 30,
RT_CID_819x_SAMSUNG = 31,
RT_CID_819x_CLEVO = 32,
RT_CID_819x_DELL = 33,
RT_CID_819x_PRONETS = 34,
RT_CID_819x_Edimax_ASUS = 35,
RT_CID_819x_CAMEO_NETGEAR = 36,
RT_CID_PLANEX = 37,
RT_CID_CC_C = 38,
RT_CID_819x_Xavi = 39,
RT_CID_819x_FUNAI_TV = 40,
RT_CID_819x_ALPHA_WD=41,
};
struct eeprom_priv {
u8 bautoload_fail_flag;
u8 bloadfile_fail_flag;
u8 bloadmac_fail_flag;
/* u8 bempty; */
/* u8 sys_config; */
u8 mac_addr[6]; /* PermanentAddress */
/* u8 config0; */
u16 channel_plan;
/* u8 country_string[3]; */
/* u8 tx_power_b[15]; */
/* u8 tx_power_g[15]; */
/* u8 tx_power_a[201]; */
u8 EepromOrEfuse;
u8 efuse_eeprom_data[HWSET_MAX_SIZE_512]; /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
};
void eeprom_write16(struct rtw_adapter *padapter, u16 reg, u16 data);
u16 eeprom_read16(struct rtw_adapter *padapter, u16 reg);
void read_eeprom_content(struct rtw_adapter *padapter);
void eeprom_read_sz(struct rtw_adapter * padapter, u16 reg,u8* data, u32 sz);
void read_eeprom_content_by_attrib(struct rtw_adapter *padapter);
#endif /* __RTL871X_EEPROM_H__ */

109
drivers/staging/rtl8723au/include/rtw_efuse.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*
******************************************************************************/
#ifndef __RTW_EFUSE_H__
#define __RTW_EFUSE_H__
#include <osdep_service.h>
#define EFUSE_ERROE_HANDLE 1
#define PG_STATE_HEADER 0x01
#define PG_STATE_WORD_0 0x02
#define PG_STATE_WORD_1 0x04
#define PG_STATE_WORD_2 0x08
#define PG_STATE_WORD_3 0x10
#define PG_STATE_DATA 0x20
#define PG_SWBYTE_H 0x01
#define PG_SWBYTE_L 0x02
#define PGPKT_DATA_SIZE 8
#define EFUSE_WIFI 0
#define EFUSE_BT 1
enum _EFUSE_DEF_TYPE {
TYPE_EFUSE_MAX_SECTION = 0,
TYPE_EFUSE_REAL_CONTENT_LEN = 1,
TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2,
TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3,
TYPE_EFUSE_MAP_LEN = 4,
TYPE_EFUSE_PROTECT_BYTES_BANK = 5,
TYPE_EFUSE_CONTENT_LEN_BANK = 6,
};
/* E-Fuse */
#define EFUSE_MAP_SIZE 256
#define EFUSE_MAX_SIZE 512
/* end of E-Fuse */
#define EFUSE_MAX_MAP_LEN 256
#define EFUSE_MAX_HW_SIZE 512
#define EFUSE_MAX_SECTION_BASE 16
#define EXT_HEADER(header) ((header & 0x1F ) == 0x0F)
#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F)
#define GET_HDR_OFFSET_2_0(header) ( (header & 0xE0) >> 5)
#define EFUSE_REPEAT_THRESHOLD_ 3
/* */
/* The following is for BT Efuse definition */
/* */
#define EFUSE_BT_MAX_MAP_LEN 1024
#define EFUSE_MAX_BANK 4
#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1)
/* */
/*--------------------------Define Parameters-------------------------------*/
#define EFUSE_MAX_WORD_UNIT 4
/*------------------------------Define structure----------------------------*/
struct pg_pkt_struct {
u8 offset;
u8 word_en;
u8 data[8];
u8 word_cnts;
};
/*------------------------Export global variable----------------------------*/
u8 efuse_GetCurrentSize23a(struct rtw_adapter *padapter, u16 *size);
u16 efuse_GetMaxSize23a(struct rtw_adapter *padapter);
u8 rtw_efuse_access23a(struct rtw_adapter *padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data);
u8 rtw_efuse_map_read23a(struct rtw_adapter *padapter, u16 addr, u16 cnts, u8 *data);
u8 rtw_efuse_map_write(struct rtw_adapter *padapter, u16 addr, u16 cnts, u8 *data);
u8 rtw_BT_efuse_map_read23a(struct rtw_adapter *padapter, u16 addr, u16 cnts, u8 *data);
u8 rtw_BT_efuse_map_write(struct rtw_adapter *padapter, u16 addr, u16 cnts, u8 *data);
u16 Efuse_GetCurrentSize23a(struct rtw_adapter *pAdapter, u8 efuseType);
u8 Efuse_CalculateWordCnts23a(u8 word_en);
void ReadEFuseByte23a(struct rtw_adapter *Adapter, u16 _offset, u8 *pbuf);
void EFUSE_GetEfuseDefinition23a(struct rtw_adapter *pAdapter, u8 efuseType, u8 type, void *pOut);
u8 efuse_OneByteRead23a(struct rtw_adapter *pAdapter, u16 addr, u8 *data);
u8 efuse_OneByteWrite23a(struct rtw_adapter *pAdapter, u16 addr, u8 data);
void Efuse_PowerSwitch23a(struct rtw_adapter *pAdapter,u8 bWrite,u8 PwrState);
int Efuse_PgPacketRead23a(struct rtw_adapter *pAdapter, u8 offset, u8 *data);
int Efuse_PgPacketWrite23a(struct rtw_adapter *pAdapter, u8 offset, u8 word_en, u8 *data);
void efuse_WordEnableDataRead23a(u8 word_en, u8 *sourdata, u8 *targetdata);
u8 Efuse_WordEnableDataWrite23a(struct rtw_adapter *pAdapter, u16 efuse_addr, u8 word_en, u8 *data);
u8 EFUSE_Read1Byte23a(struct rtw_adapter *pAdapter, u16 Address);
void EFUSE_ShadowMapUpdate23a(struct rtw_adapter *pAdapter, u8 efuseType);
void EFUSE_ShadowRead23a(struct rtw_adapter *pAdapter, u8 Type, u16 Offset, u32 *Value);
#endif

114
drivers/staging/rtl8723au/include/rtw_event.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _RTW_EVENT_H_
#define _RTW_EVENT_H_
#include <osdep_service.h>
#include <wlan_bssdef.h>
/*
Used to report a bss has been scanned
*/
struct survey_event {
struct wlan_bssid_ex bss;
};
/*
Used to report that the requested site survey has been done.
bss_cnt indicates the number of bss that has been reported.
*/
struct surveydone_event {
unsigned int bss_cnt;
};
/*
Used to report the link result of joinning the given bss
join_res:
-1: authentication fail
-2: association fail
> 0: TID
*/
struct joinbss_event {
struct wlan_network network;
};
/*
Used to report a given STA has joinned the created BSS.
It is used in AP/Ad-HoC(M) mode.
*/
struct stassoc_event {
unsigned char macaddr[6];
unsigned char rsvd[2];
int cam_id;
};
struct stadel_event {
unsigned char macaddr[6];
unsigned char rsvd[2]; /* for reason */
int mac_id;
};
struct addba_event
{
unsigned int tid;
};
#define GEN_EVT_CODE(event) event ## _EVT_
struct fwevent {
u32 parmsize;
void (*event_callback)(struct rtw_adapter *dev, u8 *pbuf);
};
#define C2HEVENT_SZ 32
struct event_node{
unsigned char *node;
unsigned char evt_code;
unsigned short evt_sz;
volatile int *caller_ff_tail;
int caller_ff_sz;
};
struct c2hevent_queue {
volatile int head;
volatile int tail;
struct event_node nodes[C2HEVENT_SZ];
unsigned char seq;
};
#define NETWORK_QUEUE_SZ 4
struct network_queue {
volatile int head;
volatile int tail;
struct wlan_bssid_ex networks[NETWORK_QUEUE_SZ];
};
#endif /* _WLANEVENT_H_ */

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