pinctrl: actions: define constructor generic to Actions Semi SoC's
Move generic defines common to the Owl family out of S900 driver. Signed-off-by: Parthiban Nallathambi <pn@denx.de> Signed-off-by: Saravanan Sekar <sravanhome@gmail.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -15,6 +15,136 @@
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#define OWL_PINCONF_SLEW_SLOW 0
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#define OWL_PINCONF_SLEW_FAST 1
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#define MUX_PG(group_name, reg, shift, width) \
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{ \
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.name = #group_name, \
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.pads = group_name##_pads, \
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.npads = ARRAY_SIZE(group_name##_pads), \
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.funcs = group_name##_funcs, \
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.nfuncs = ARRAY_SIZE(group_name##_funcs), \
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.mfpctl_reg = MFCTL##reg, \
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.mfpctl_shift = shift, \
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.mfpctl_width = width, \
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.drv_reg = -1, \
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.drv_shift = -1, \
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.drv_width = -1, \
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.sr_reg = -1, \
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.sr_shift = -1, \
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.sr_width = -1, \
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}
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#define DRV_PG(group_name, reg, shift, width) \
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{ \
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.name = #group_name, \
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.pads = group_name##_pads, \
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.npads = ARRAY_SIZE(group_name##_pads), \
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.mfpctl_reg = -1, \
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.mfpctl_shift = -1, \
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.mfpctl_width = -1, \
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.drv_reg = PAD_DRV##reg, \
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.drv_shift = shift, \
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.drv_width = width, \
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.sr_reg = -1, \
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.sr_shift = -1, \
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.sr_width = -1, \
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}
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#define SR_PG(group_name, reg, shift, width) \
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{ \
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.name = #group_name, \
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.pads = group_name##_pads, \
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.npads = ARRAY_SIZE(group_name##_pads), \
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.mfpctl_reg = -1, \
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.mfpctl_shift = -1, \
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.mfpctl_width = -1, \
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.drv_reg = -1, \
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.drv_shift = -1, \
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.drv_width = -1, \
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.sr_reg = PAD_SR##reg, \
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.sr_shift = shift, \
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.sr_width = width, \
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}
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#define FUNCTION(fname) \
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{ \
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.name = #fname, \
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.groups = fname##_groups, \
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.ngroups = ARRAY_SIZE(fname##_groups), \
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}
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/* PAD PULL UP/DOWN CONFIGURES */
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#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
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{ \
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.reg = PAD_PULLCTL##pull_reg, \
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.shift = pull_sft, \
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.width = pull_wdt, \
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}
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#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
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struct owl_pullctl pad_name##_pullctl_conf \
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= PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
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#define ST_CONF(st_reg, st_sft, st_wdt) \
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{ \
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.reg = PAD_ST##st_reg, \
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.shift = st_sft, \
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.width = st_wdt, \
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}
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#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \
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struct owl_st pad_name##_st_conf \
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= ST_CONF(st_reg, st_sft, st_wdt)
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#define PAD_INFO(name) \
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{ \
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.pad = name, \
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.pullctl = NULL, \
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.st = NULL, \
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}
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#define PAD_INFO_ST(name) \
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{ \
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.pad = name, \
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.pullctl = NULL, \
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.st = &name##_st_conf, \
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}
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#define PAD_INFO_PULLCTL(name) \
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{ \
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.pad = name, \
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.pullctl = &name##_pullctl_conf, \
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.st = NULL, \
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}
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#define PAD_INFO_PULLCTL_ST(name) \
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{ \
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.pad = name, \
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.pullctl = &name##_pullctl_conf, \
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.st = &name##_st_conf, \
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}
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#define OWL_GPIO_PORT_A 0
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#define OWL_GPIO_PORT_B 1
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#define OWL_GPIO_PORT_C 2
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#define OWL_GPIO_PORT_D 3
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#define OWL_GPIO_PORT_E 4
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#define OWL_GPIO_PORT_F 5
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#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\
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_intc_pd, _intc_msk, _intc_type, _share) \
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[OWL_GPIO_PORT_##port] = { \
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.offset = base, \
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.pins = count, \
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.outen = _outen, \
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.inen = _inen, \
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.dat = _dat, \
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.intc_ctl = _intc_ctl, \
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.intc_pd = _intc_pd, \
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.intc_msk = _intc_msk, \
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.intc_type = _intc_type, \
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.shared_ctl_offset = _share, \
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}
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enum owl_pinconf_pull {
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OWL_PINCONF_PULL_HIZ,
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OWL_PINCONF_PULL_DOWN,
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@ -148,6 +278,7 @@ struct owl_gpio_port {
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unsigned int intc_pd;
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unsigned int intc_msk;
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unsigned int intc_type;
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u8 shared_ctl_offset;
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};
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/**
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@ -33,13 +33,6 @@
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#define PAD_SR1 (0x0274)
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#define PAD_SR2 (0x0278)
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#define OWL_GPIO_PORT_A 0
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#define OWL_GPIO_PORT_B 1
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#define OWL_GPIO_PORT_C 2
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#define OWL_GPIO_PORT_D 3
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#define OWL_GPIO_PORT_E 4
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#define OWL_GPIO_PORT_F 5
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#define _GPIOA(offset) (offset)
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#define _GPIOB(offset) (32 + (offset))
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#define _GPIOC(offset) (64 + (offset))
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@ -892,55 +885,6 @@ static unsigned int i2c2_sr_pads[] = { I2C2_SCLK, I2C2_SDATA };
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static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK,
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SENSOR0_CKOUT };
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#define MUX_PG(group_name, reg, shift, width) \
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{ \
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.name = #group_name, \
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.pads = group_name##_pads, \
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.npads = ARRAY_SIZE(group_name##_pads), \
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.funcs = group_name##_funcs, \
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.nfuncs = ARRAY_SIZE(group_name##_funcs), \
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.mfpctl_reg = MFCTL##reg, \
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.mfpctl_shift = shift, \
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.mfpctl_width = width, \
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.drv_reg = -1, \
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.drv_shift = -1, \
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.drv_width = -1, \
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.sr_reg = -1, \
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.sr_shift = -1, \
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.sr_width = -1, \
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}
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#define DRV_PG(group_name, reg, shift, width) \
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{ \
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.name = #group_name, \
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.pads = group_name##_pads, \
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.npads = ARRAY_SIZE(group_name##_pads), \
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.mfpctl_reg = -1, \
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.mfpctl_shift = -1, \
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.mfpctl_width = -1, \
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.drv_reg = PAD_DRV##reg, \
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.drv_shift = shift, \
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.drv_width = width, \
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.sr_reg = -1, \
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.sr_shift = -1, \
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.sr_width = -1, \
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}
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#define SR_PG(group_name, reg, shift, width) \
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{ \
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.name = #group_name, \
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.pads = group_name##_pads, \
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.npads = ARRAY_SIZE(group_name##_pads), \
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.mfpctl_reg = -1, \
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.mfpctl_shift = -1, \
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.mfpctl_width = -1, \
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.drv_reg = -1, \
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.drv_shift = -1, \
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.drv_width = -1, \
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.sr_reg = PAD_SR##reg, \
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.sr_shift = shift, \
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.sr_width = width, \
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}
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/* Pinctrl groups */
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static const struct owl_pingroup s900_groups[] = {
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@ -1442,13 +1386,6 @@ static const char * const sirq2_groups[] = {
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"sirq2_dummy",
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};
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#define FUNCTION(fname) \
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{ \
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.name = #fname, \
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.groups = fname##_groups, \
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.ngroups = ARRAY_SIZE(fname##_groups), \
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}
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static const struct owl_pinmux_func s900_functions[] = {
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[S900_MUX_ERAM] = FUNCTION(eram),
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[S900_MUX_ETH_RMII] = FUNCTION(eth_rmii),
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@ -1500,28 +1437,6 @@ static const struct owl_pinmux_func s900_functions[] = {
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[S900_MUX_SIRQ1] = FUNCTION(sirq1),
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[S900_MUX_SIRQ2] = FUNCTION(sirq2)
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};
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/* PAD PULL UP/DOWN CONFIGURES */
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#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
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{ \
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.reg = PAD_PULLCTL##pull_reg, \
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.shift = pull_sft, \
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.width = pull_wdt, \
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}
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#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
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struct owl_pullctl pad_name##_pullctl_conf \
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= PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
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#define ST_CONF(st_reg, st_sft, st_wdt) \
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{ \
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.reg = PAD_ST##st_reg, \
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.shift = st_sft, \
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.width = st_wdt, \
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}
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#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \
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struct owl_st pad_name##_st_conf \
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= ST_CONF(st_reg, st_sft, st_wdt)
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/* PAD_PULLCTL0 */
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static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2);
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@ -1639,34 +1554,6 @@ static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
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static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
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static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
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#define PAD_INFO(name) \
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{ \
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.pad = name, \
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.pullctl = NULL, \
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.st = NULL, \
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}
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#define PAD_INFO_ST(name) \
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{ \
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.pad = name, \
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.pullctl = NULL, \
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.st = &name##_st_conf, \
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}
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#define PAD_INFO_PULLCTL(name) \
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{ \
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.pad = name, \
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.pullctl = &name##_pullctl_conf, \
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.st = NULL, \
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}
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#define PAD_INFO_PULLCTL_ST(name) \
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{ \
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.pad = name, \
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.pullctl = &name##_pullctl_conf, \
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.st = &name##_st_conf, \
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}
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/* Pad info table */
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static struct owl_padinfo s900_padinfo[NUM_PADS] = {
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[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
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@ -1821,27 +1708,13 @@ static struct owl_padinfo s900_padinfo[NUM_PADS] = {
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[SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
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};
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#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, \
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_intc_ctl, _intc_pd, _intc_msk, _intc_type) \
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[OWL_GPIO_PORT_##port] = { \
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.offset = base, \
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.pins = count, \
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.outen = _outen, \
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.inen = _inen, \
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.dat = _dat, \
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.intc_ctl = _intc_ctl, \
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.intc_pd = _intc_pd, \
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.intc_msk = _intc_msk, \
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.intc_type = _intc_type, \
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}
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static const struct owl_gpio_port s900_gpio_ports[] = {
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OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240),
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OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C),
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OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238),
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OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234),
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OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230),
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OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178)
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OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240, 0),
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OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C, 0),
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OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0),
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OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234, 0),
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OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230, 0),
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OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178, 0)
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};
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static struct owl_pinctrl_soc_data s900_pinctrl_data = {
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