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spelling fixes: arch/sh64/ 

Spelling fixes in arch/sh64/.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Simon Arlott 2007-05-14 08:25:48 +09:00 committed by Paul Mundt
parent 47e77eeecf
commit 0a354775af
6 changed files with 7 additions and 7 deletions
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2
arch/sh64/kernel/pci_sh5.h
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@ -4,7 +4,7 @@
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Defintions for the SH5 PCI hardware.
* Definitions for the SH5 PCI hardware.
*/
/* Product ID */

2
arch/sh64/kernel/process.c
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@ -387,7 +387,7 @@ ATTRIB_NORET void kernel_thread_helper(void *arg, int (*fn)(void *))
* NOTE! Only a kernel-only process(ie the swapper or direct descendants
* who haven't done an "execve()") should use this: it will work within
* a system call from a "real" process, but the process memory space will
* not be free'd until both the parent and the child have exited.
* not be freed until both the parent and the child have exited.
*/
int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
{

2
arch/sh64/kernel/time.c
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@ -123,7 +123,7 @@ static unsigned long long usecs_per_jiffy = 1000000/HZ; /* Approximation */
static unsigned long long scaled_recip_ctc_ticks_per_jiffy;
/* Estimate number of microseconds that have elapsed since the last timer tick,
by scaling the delta that has occured in the CTC register.
by scaling the delta that has occurred in the CTC register.
WARNING WARNING WARNING : This algorithm relies on the CTC decrementing at
the CPU clock rate. If the CPU sleeps, the CTC stops counting. Bear this

2
arch/sh64/mach-cayman/setup.c
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@ -213,7 +213,7 @@ static int __init smsc_superio_setup(void)
SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
#endif
/* Exit the configuraton state */
/* Exit the configuration state */
outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
return 0;

2
arch/sh64/mm/fault.c
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@ -135,7 +135,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess,
/* SIM
* Note this is now called with interrupts still disabled
* This is to cope with being called for a missing IO port
* address with interupts disabled. This should be fixed as
* address with interrupts disabled. This should be fixed as
* soon as we have a better 'fast path' miss handler.
*
* Plus take care how you try and debug this stuff.

4
arch/sh64/mm/tlbmiss.c
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@ -14,7 +14,7 @@
* IMPORTANT NOTES :
* The do_fast_page_fault function is called from a context in entry.S where very few registers
* have been saved. In particular, the code in this file must be compiled not to use ANY
* caller-save regiseters that are not part of the restricted save set. Also, it means that
* caller-save registers that are not part of the restricted save set. Also, it means that
* code in this file must not make calls to functions elsewhere in the kernel, or else the
* excepting context will see corruption in its caller-save registers. Plus, the entry.S save
* area is non-reentrant, so this code has to run with SR.BL==1, i.e. no interrupts taken inside
@ -249,7 +249,7 @@ asmlinkage int do_fast_page_fault(unsigned long long ssr_md, unsigned long long
/* SIM
* Note this is now called with interrupts still disabled
* This is to cope with being called for a missing IO port
* address with interupts disabled. This should be fixed as
* address with interrupts disabled. This should be fixed as
* soon as we have a better 'fast path' miss handler.
*
* Plus take care how you try and debug this stuff.