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clk: ux500: Define smp_twd clock for u8500 

The smp_twd clock is based upon a prcmu_rate clock type
for the PRCMU_ARMSS clock.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Ulf Hansson 2012-08-31 14:21:31 +02:00 committed by Mike Turquette
parent 20aee5b6d7
commit 09b9b2b204
1 changed files with 8 additions and 4 deletions
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12
drivers/clk/ux500/u8500_clk.c
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@ -205,12 +205,16 @@ void u8500_clk_init(void)
clk_register_clkdev(clk, "dsilp2", "dsilink.2");
clk_register_clkdev(clk, "dsilp2", "mcde");
clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS,
CLK_IS_ROOT|CLK_GET_RATE_NOCACHE|
CLK_IGNORE_UNUSED);
clk_register_clkdev(clk, NULL, "smp_twd");
/*
* FIXME: Add special handled PRCMU clocks here:
* 1. smp_twd, use PRCMU_ARMSS.
* 2. clk_arm, use PRCMU_ARMCLK.
* 3. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
* 4. ab9540_clkout1yuv, see clkout0yuv
* 1. clk_arm, use PRCMU_ARMCLK.
* 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
* 3. ab9540_clkout1yuv, see clkout0yuv
*/
/* PRCC P-clocks */