powerpc updates for 4.2
- Disable the 32-bit vdso when building LE, so we can build with a 64-bit only
toolchain.
- EEH fixes from Gavin & Richard.
- Enable the sys_kcmp syscall from Laurent.
- Sysfs control for fastsleep workaround from Shreyas.
- Expose OPAL events as an irq chip by Alistair.
- MSI ops moved to pci_controller_ops by Daniel.
- Fix for kernel to userspace backtraces for perf from Anton.
- Merge pseries and pseries_le defconfigs from Cyril.
- CXL in-kernel API from Mikey.
- OPAL prd driver from Jeremy.
- Fix for DSCR handling & tests from Anshuman.
- Powernv flash mtd driver from Cyril.
- Dynamic DMA Window support on powernv from Alexey.
- LLVM clang fixes & workarounds from Anton.
- Reworked version of the patch to abort syscalls when transactional.
- Fix the swap encoding to support 4TB, from Aneesh.
- Various fixes as usual.
- Freescale updates from Scott: Highlights include more 8xx optimizations, an
e6500 hugetlb optimization, QMan device tree nodes, t1024/t1023 support, and
various fixes and cleanup.
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Merge tag 'powerpc-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux
Pull powerpc updates from Michael Ellerman:
- disable the 32-bit vdso when building LE, so we can build with a
64-bit only toolchain.
- EEH fixes from Gavin & Richard.
- enable the sys_kcmp syscall from Laurent.
- sysfs control for fastsleep workaround from Shreyas.
- expose OPAL events as an irq chip by Alistair.
- MSI ops moved to pci_controller_ops by Daniel.
- fix for kernel to userspace backtraces for perf from Anton.
- merge pseries and pseries_le defconfigs from Cyril.
- CXL in-kernel API from Mikey.
- OPAL prd driver from Jeremy.
- fix for DSCR handling & tests from Anshuman.
- Powernv flash mtd driver from Cyril.
- dynamic DMA Window support on powernv from Alexey.
- LLVM clang fixes & workarounds from Anton.
- reworked version of the patch to abort syscalls when transactional.
- fix the swap encoding to support 4TB, from Aneesh.
- various fixes as usual.
- Freescale updates from Scott: Highlights include more 8xx
optimizations, an e6500 hugetlb optimization, QMan device tree nodes,
t1024/t1023 support, and various fixes and cleanup.
* tag 'powerpc-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux: (180 commits)
cxl: Fix typo in debug print
cxl: Add CXL_KERNEL_API config option
powerpc/powernv: Fix wrong IOMMU table in pnv_ioda_setup_bus_dma()
powerpc/mm: Change the swap encoding in pte.
powerpc/mm: PTE_RPN_MAX is not used, remove the same
powerpc/tm: Abort syscalls in active transactions
powerpc/iommu/ioda2: Enable compile with IOV=on and IOMMU_API=off
powerpc/include: Add opal-prd to installed uapi headers
powerpc/powernv: fix construction of opal PRD messages
powerpc/powernv: Increase opal-irqchip initcall priority
powerpc: Make doorbell check preemption safe
powerpc/powernv: pnv_init_idle_states() should only run on powernv
macintosh/nvram: Remove as unused
powerpc: Don't use gcc specific options on clang
powerpc: Don't use -mno-strict-align on clang
powerpc: Only use -mtraceback=no, -mno-string and -msoft-float if toolchain supports it
powerpc: Only use -mabi=altivec if toolchain supports it
powerpc: Fix duplicate const clang warning in user access code
vfio: powerpc/spapr: Support Dynamic DMA windows
vfio: powerpc/spapr: Register memory and define IOMMU v2
...
This commit is contained in:
Linus Torvalds
commit
08d183e3c1
|
|
@ -6,6 +6,17 @@ Example: The real path of the attribute /sys/class/cxl/afu0.0s/irqs_max is
|
|||
|
||||
Slave contexts (eg. /sys/class/cxl/afu0.0s):
|
||||
|
||||
What: /sys/class/cxl/<afu>/afu_err_buf
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
AFU Error Buffer contents. The contents of this file are
|
||||
application specific and depends on the AFU being used.
|
||||
Applications interacting with the AFU can use this attribute
|
||||
to know about the current error condition and take appropriate
|
||||
action like logging the event etc.
|
||||
|
||||
|
||||
What: /sys/class/cxl/<afu>/irqs_max
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
|
|
@ -15,6 +26,7 @@ Description: read/write
|
|||
that hardware can support (eg. 2037). Write values will limit
|
||||
userspace applications to that many userspace interrupts. Must
|
||||
be >= irqs_min.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>/irqs_min
|
||||
Date: September 2014
|
||||
|
|
@ -24,6 +36,7 @@ Description: read only
|
|||
userspace must request on a CXL_START_WORK ioctl. Userspace may
|
||||
omit the num_interrupts field in the START_WORK IOCTL to get
|
||||
this minimum automatically.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>/mmio_size
|
||||
Date: September 2014
|
||||
|
|
@ -31,6 +44,7 @@ Contact: linuxppc-dev@lists.ozlabs.org
|
|||
Description: read only
|
||||
Decimal value of the size of the MMIO space that may be mmaped
|
||||
by userspace.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>/modes_supported
|
||||
Date: September 2014
|
||||
|
|
@ -38,6 +52,7 @@ Contact: linuxppc-dev@lists.ozlabs.org
|
|||
Description: read only
|
||||
List of the modes this AFU supports. One per line.
|
||||
Valid entries are: "dedicated_process" and "afu_directed"
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>/mode
|
||||
Date: September 2014
|
||||
|
|
@ -46,6 +61,7 @@ Description: read/write
|
|||
The current mode the AFU is using. Will be one of the modes
|
||||
given in modes_supported. Writing will change the mode
|
||||
provided that no user contexts are attached.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
|
||||
What: /sys/class/cxl/<afu>/prefault_mode
|
||||
|
|
@ -59,6 +75,7 @@ Description: read/write
|
|||
descriptor as an effective address and
|
||||
prefault what it points to.
|
||||
all: all segments process calling START_WORK maps.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>/reset
|
||||
Date: September 2014
|
||||
|
|
@ -66,12 +83,14 @@ Contact: linuxppc-dev@lists.ozlabs.org
|
|||
Description: write only
|
||||
Writing 1 here will reset the AFU provided there are not
|
||||
contexts active on the AFU.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>/api_version
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the current version of the kernel/user API.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>/api_version_compatible
|
||||
Date: September 2014
|
||||
|
|
@ -79,6 +98,7 @@ Contact: linuxppc-dev@lists.ozlabs.org
|
|||
Description: read only
|
||||
Decimal value of the the lowest version of the userspace API
|
||||
this this kernel supports.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
|
||||
AFU configuration records (eg. /sys/class/cxl/afu0.0/cr0):
|
||||
|
|
@ -92,6 +112,7 @@ Contact: linuxppc-dev@lists.ozlabs.org
|
|||
Description: read only
|
||||
Hexadecimal value of the vendor ID found in this AFU
|
||||
configuration record.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>/cr<config num>/device
|
||||
Date: February 2015
|
||||
|
|
@ -99,6 +120,7 @@ Contact: linuxppc-dev@lists.ozlabs.org
|
|||
Description: read only
|
||||
Hexadecimal value of the device ID found in this AFU
|
||||
configuration record.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>/cr<config num>/class
|
||||
Date: February 2015
|
||||
|
|
@ -106,6 +128,7 @@ Contact: linuxppc-dev@lists.ozlabs.org
|
|||
Description: read only
|
||||
Hexadecimal value of the class code found in this AFU
|
||||
configuration record.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>/cr<config num>/config
|
||||
Date: February 2015
|
||||
|
|
@ -115,6 +138,7 @@ Description: read only
|
|||
record. The format is expected to match the either the standard
|
||||
or extended configuration space defined by the PCIe
|
||||
specification.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
|
||||
|
||||
|
|
@ -126,18 +150,21 @@ Contact: linuxppc-dev@lists.ozlabs.org
|
|||
Description: read only
|
||||
Decimal value of the size of the MMIO space that may be mmaped
|
||||
by userspace. This includes all slave contexts space also.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>m/pp_mmio_len
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the Per Process MMIO space length.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<afu>m/pp_mmio_off
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the Per Process MMIO space offset.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
|
||||
Card info (eg. /sys/class/cxl/card0)
|
||||
|
|
@ -147,12 +174,14 @@ Date: September 2014
|
|||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Identifies the CAIA Version the card implements.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<card>/psl_revision
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Identifies the revision level of the PSL.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<card>/base_image
|
||||
Date: September 2014
|
||||
|
|
@ -162,6 +191,7 @@ Description: read only
|
|||
that support loadable PSLs. For FPGAs this field identifies
|
||||
the image contained in the on-adapter flash which is loaded
|
||||
during the initial program load.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<card>/image_loaded
|
||||
Date: September 2014
|
||||
|
|
@ -169,6 +199,7 @@ Contact: linuxppc-dev@lists.ozlabs.org
|
|||
Description: read only
|
||||
Will return "user" or "factory" depending on the image loaded
|
||||
onto the card.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<card>/load_image_on_perst
|
||||
Date: December 2014
|
||||
|
|
@ -183,6 +214,7 @@ Description: read/write
|
|||
user or factory image to be loaded.
|
||||
Default is to reload on PERST whichever image the card has
|
||||
loaded.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
What: /sys/class/cxl/<card>/reset
|
||||
Date: October 2014
|
||||
|
|
@ -190,3 +222,4 @@ Contact: linuxppc-dev@lists.ozlabs.org
|
|||
Description: write only
|
||||
Writing 1 will issue a PERST to card which may cause the card
|
||||
to reload the FPGA depending on load_image_on_perst.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
|
|
|||
|
|
@ -189,6 +189,19 @@ PROPERTIES
|
|||
Definition: There is one reg region describing the port
|
||||
configuration registers.
|
||||
|
||||
- fsl,fman-10g-port
|
||||
Usage: optional
|
||||
Value type: boolean
|
||||
Definition: The default port rate is 1G.
|
||||
If this property exists, the port is s 10G port.
|
||||
|
||||
- fsl,fman-best-effort-port
|
||||
Usage: optional
|
||||
Value type: boolean
|
||||
Definition: Can be defined only if 10G-support is set.
|
||||
This property marks a best-effort 10G port (10G port that
|
||||
may not be capable of line rate).
|
||||
|
||||
EXAMPLE
|
||||
|
||||
port@a8000 {
|
||||
|
|
|
|||
|
|
@ -9,6 +9,11 @@ Required properties:
|
|||
|
||||
- compatible : Should define the compatible device type for
|
||||
global-utilities.
|
||||
Possible compatibles:
|
||||
"fsl,qoriq-device-config-1.0"
|
||||
"fsl,qoriq-device-config-2.0"
|
||||
"fsl,<chip>-device-config"
|
||||
"fsl,<chip>-guts"
|
||||
- reg : Offset and length of the register set for the device.
|
||||
|
||||
Recommended properties:
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ PROPERTIES
|
|||
|
||||
For additional details about the PAMU/LIODN binding(s) see pamu.txt
|
||||
|
||||
- fsl,qman-channel-id
|
||||
- cell-index
|
||||
Usage: Required
|
||||
Value type: <u32>
|
||||
Definition: The hardware index of the channel. This can also be
|
||||
|
|
@ -136,7 +136,7 @@ The example below shows a (P4080) QMan portals container/bus node with two porta
|
|||
reg = <0x4000 0x4000>, <0x101000 0x1000>;
|
||||
interrupts = <106 2 0 0>;
|
||||
fsl,liodn = <3 4>;
|
||||
fsl,qman-channel-id = <1>;
|
||||
cell-index = <1>;
|
||||
|
||||
fman0 {
|
||||
fsl,liodn = <0x22>;
|
||||
|
|
|
|||
|
|
@ -30,3 +30,5 @@ ptrace.txt
|
|||
- Information on the ptrace interfaces for hardware debug registers.
|
||||
transactional_memory.txt
|
||||
- Overview of the Power8 transactional memory support.
|
||||
dscr.txt
|
||||
- Overview DSCR (Data Stream Control Register) support.
|
||||
|
|
|
|||
|
|
@ -133,6 +133,9 @@ User API
|
|||
The following file operations are supported on both slave and
|
||||
master devices.
|
||||
|
||||
A userspace library libcxl is avaliable here:
|
||||
https://github.com/ibm-capi/libcxl
|
||||
This provides a C interface to this kernel API.
|
||||
|
||||
open
|
||||
----
|
||||
|
|
@ -366,6 +369,7 @@ Sysfs Class
|
|||
enumeration and tuning of the accelerators. Its layout is
|
||||
described in Documentation/ABI/testing/sysfs-class-cxl
|
||||
|
||||
|
||||
Udev rules
|
||||
==========
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,83 @@
|
|||
DSCR (Data Stream Control Register)
|
||||
================================================
|
||||
|
||||
DSCR register in powerpc allows user to have some control of prefetch of data
|
||||
stream in the processor. Please refer to the ISA documents or related manual
|
||||
for more detailed information regarding how to use this DSCR to attain this
|
||||
control of the pefetches . This document here provides an overview of kernel
|
||||
support for DSCR, related kernel objects, it's functionalities and exported
|
||||
user interface.
|
||||
|
||||
(A) Data Structures:
|
||||
|
||||
(1) thread_struct:
|
||||
dscr /* Thread DSCR value */
|
||||
dscr_inherit /* Thread has changed default DSCR */
|
||||
|
||||
(2) PACA:
|
||||
dscr_default /* per-CPU DSCR default value */
|
||||
|
||||
(3) sysfs.c:
|
||||
dscr_default /* System DSCR default value */
|
||||
|
||||
(B) Scheduler Changes:
|
||||
|
||||
Scheduler will write the per-CPU DSCR default which is stored in the
|
||||
CPU's PACA value into the register if the thread has dscr_inherit value
|
||||
cleared which means that it has not changed the default DSCR till now.
|
||||
If the dscr_inherit value is set which means that it has changed the
|
||||
default DSCR value, scheduler will write the changed value which will
|
||||
now be contained in thread struct's dscr into the register instead of
|
||||
the per-CPU default PACA based DSCR value.
|
||||
|
||||
NOTE: Please note here that the system wide global DSCR value never
|
||||
gets used directly in the scheduler process context switch at all.
|
||||
|
||||
(C) SYSFS Interface:
|
||||
|
||||
Global DSCR default: /sys/devices/system/cpu/dscr_default
|
||||
CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr
|
||||
|
||||
Changing the global DSCR default in the sysfs will change all the CPU
|
||||
specific DSCR defaults immediately in their PACA structures. Again if
|
||||
the current process has the dscr_inherit clear, it also writes the new
|
||||
value into every CPU's DSCR register right away and updates the current
|
||||
thread's DSCR value as well.
|
||||
|
||||
Changing the CPU specif DSCR default value in the sysfs does exactly
|
||||
the same thing as above but unlike the global one above, it just changes
|
||||
stuff for that particular CPU instead for all the CPUs on the system.
|
||||
|
||||
(D) User Space Instructions:
|
||||
|
||||
The DSCR register can be accessed in the user space using any of these
|
||||
two SPR numbers available for that purpose.
|
||||
|
||||
(1) Problem state SPR: 0x03 (Un-privileged, POWER8 only)
|
||||
(2) Privileged state SPR: 0x11 (Privileged)
|
||||
|
||||
Accessing DSCR through privileged SPR number (0x11) from user space
|
||||
works, as it is emulated following an illegal instruction exception
|
||||
inside the kernel. Both mfspr and mtspr instructions are emulated.
|
||||
|
||||
Accessing DSCR through user level SPR (0x03) from user space will first
|
||||
create a facility unavailable exception. Inside this exception handler
|
||||
all mfspr isntruction based read attempts will get emulated and returned
|
||||
where as the first mtspr instruction based write attempts will enable
|
||||
the DSCR facility for the next time around (both for read and write) by
|
||||
setting DSCR facility in the FSCR register.
|
||||
|
||||
(E) Specifics about 'dscr_inherit':
|
||||
|
||||
The thread struct element 'dscr_inherit' represents whether the thread
|
||||
in question has attempted and changed the DSCR itself using any of the
|
||||
following methods. This element signifies whether the thread wants to
|
||||
use the CPU default DSCR value or its own changed DSCR value in the
|
||||
kernel.
|
||||
|
||||
(1) mtspr instruction (SPR number 0x03)
|
||||
(2) mtspr instruction (SPR number 0x11)
|
||||
(3) ptrace interface (Explicitly set user DSCR value)
|
||||
|
||||
Any child of the process created after this event in the process inherits
|
||||
this same behaviour as well.
|
||||
|
|
@ -74,22 +74,23 @@ Causes of transaction aborts
|
|||
Syscalls
|
||||
========
|
||||
|
||||
Performing syscalls from within transaction is not recommended, and can lead
|
||||
to unpredictable results.
|
||||
Syscalls made from within an active transaction will not be performed and the
|
||||
transaction will be doomed by the kernel with the failure code TM_CAUSE_SYSCALL
|
||||
| TM_CAUSE_PERSISTENT.
|
||||
|
||||
Syscalls do not by design abort transactions, but beware: The kernel code will
|
||||
not be running in transactional state. The effect of syscalls will always
|
||||
remain visible, but depending on the call they may abort your transaction as a
|
||||
side-effect, read soon-to-be-aborted transactional data that should not remain
|
||||
invisible, etc. If you constantly retry a transaction that constantly aborts
|
||||
itself by calling a syscall, you'll have a livelock & make no progress.
|
||||
Syscalls made from within a suspended transaction are performed as normal and
|
||||
the transaction is not explicitly doomed by the kernel. However, what the
|
||||
kernel does to perform the syscall may result in the transaction being doomed
|
||||
by the hardware. The syscall is performed in suspended mode so any side
|
||||
effects will be persistent, independent of transaction success or failure. No
|
||||
guarantees are provided by the kernel about which syscalls will affect
|
||||
transaction success.
|
||||
|
||||
Simple syscalls (e.g. sigprocmask()) "could" be OK. Even things like write()
|
||||
from, say, printf() should be OK as long as the kernel does not access any
|
||||
memory that was accessed transactionally.
|
||||
|
||||
Consider any syscalls that happen to work as debug-only -- not recommended for
|
||||
production use. Best to queue them up till after the transaction is over.
|
||||
Care must be taken when relying on syscalls to abort during active transactions
|
||||
if the calls are made via a library. Libraries may cache values (which may
|
||||
give the appearance of success) or perform operations that cause transaction
|
||||
failure before entering the kernel (which may produce different failure codes).
|
||||
Examples are glibc's getpid() and lazy symbol resolution.
|
||||
|
||||
|
||||
Signals
|
||||
|
|
@ -176,8 +177,7 @@ kernel aborted a transaction:
|
|||
TM_CAUSE_RESCHED Thread was rescheduled.
|
||||
TM_CAUSE_TLBI Software TLB invalid.
|
||||
TM_CAUSE_FAC_UNAV FP/VEC/VSX unavailable trap.
|
||||
TM_CAUSE_SYSCALL Currently unused; future syscalls that must abort
|
||||
transactions for consistency will use this.
|
||||
TM_CAUSE_SYSCALL Syscall from active transaction.
|
||||
TM_CAUSE_SIGNAL Signal delivered.
|
||||
TM_CAUSE_MISC Currently unused.
|
||||
TM_CAUSE_ALIGNMENT Alignment fault.
|
||||
|
|
|
|||
|
|
@ -289,10 +289,12 @@ PPC64 sPAPR implementation note
|
|||
|
||||
This implementation has some specifics:
|
||||
|
||||
1) Only one IOMMU group per container is supported as an IOMMU group
|
||||
represents the minimal entity which isolation can be guaranteed for and
|
||||
groups are allocated statically, one per a Partitionable Endpoint (PE)
|
||||
1) On older systems (POWER7 with P5IOC2/IODA1) only one IOMMU group per
|
||||
container is supported as an IOMMU table is allocated at the boot time,
|
||||
one table per a IOMMU group which is a Partitionable Endpoint (PE)
|
||||
(PE is often a PCI domain but not always).
|
||||
Newer systems (POWER8 with IODA2) have improved hardware design which allows
|
||||
to remove this limitation and have multiple IOMMU groups per a VFIO container.
|
||||
|
||||
2) The hardware supports so called DMA windows - the PCI address range
|
||||
within which DMA transfer is allowed, any attempt to access address space
|
||||
|
|
@ -385,6 +387,18 @@ The code flow from the example above should be slightly changed:
|
|||
|
||||
....
|
||||
|
||||
/* Inject EEH error, which is expected to be caused by 32-bits
|
||||
* config load.
|
||||
*/
|
||||
pe_op.op = VFIO_EEH_PE_INJECT_ERR;
|
||||
pe_op.err.type = EEH_ERR_TYPE_32;
|
||||
pe_op.err.func = EEH_ERR_FUNC_LD_CFG_ADDR;
|
||||
pe_op.err.addr = 0ul;
|
||||
pe_op.err.mask = 0ul;
|
||||
ioctl(container, VFIO_EEH_PE_OP, &pe_op);
|
||||
|
||||
....
|
||||
|
||||
/* When 0xFF's returned from reading PCI config space or IO BARs
|
||||
* of the PCI device. Check the PE's state to see if that has been
|
||||
* frozen.
|
||||
|
|
@ -427,6 +441,48 @@ The code flow from the example above should be slightly changed:
|
|||
|
||||
....
|
||||
|
||||
5) There is v2 of SPAPR TCE IOMMU. It deprecates VFIO_IOMMU_ENABLE/
|
||||
VFIO_IOMMU_DISABLE and implements 2 new ioctls:
|
||||
VFIO_IOMMU_SPAPR_REGISTER_MEMORY and VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY
|
||||
(which are unsupported in v1 IOMMU).
|
||||
|
||||
PPC64 paravirtualized guests generate a lot of map/unmap requests,
|
||||
and the handling of those includes pinning/unpinning pages and updating
|
||||
mm::locked_vm counter to make sure we do not exceed the rlimit.
|
||||
The v2 IOMMU splits accounting and pinning into separate operations:
|
||||
|
||||
- VFIO_IOMMU_SPAPR_REGISTER_MEMORY/VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY ioctls
|
||||
receive a user space address and size of the block to be pinned.
|
||||
Bisecting is not supported and VFIO_IOMMU_UNREGISTER_MEMORY is expected to
|
||||
be called with the exact address and size used for registering
|
||||
the memory block. The userspace is not expected to call these often.
|
||||
The ranges are stored in a linked list in a VFIO container.
|
||||
|
||||
- VFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA ioctls only update the actual
|
||||
IOMMU table and do not do pinning; instead these check that the userspace
|
||||
address is from pre-registered range.
|
||||
|
||||
This separation helps in optimizing DMA for guests.
|
||||
|
||||
6) sPAPR specification allows guests to have an additional DMA window(s) on
|
||||
a PCI bus with a variable page size. Two ioctls have been added to support
|
||||
this: VFIO_IOMMU_SPAPR_TCE_CREATE and VFIO_IOMMU_SPAPR_TCE_REMOVE.
|
||||
The platform has to support the functionality or error will be returned to
|
||||
the userspace. The existing hardware supports up to 2 DMA windows, one is
|
||||
2GB long, uses 4K pages and called "default 32bit window"; the other can
|
||||
be as big as entire RAM, use different page size, it is optional - guests
|
||||
create those in run-time if the guest driver supports 64bit DMA.
|
||||
|
||||
VFIO_IOMMU_SPAPR_TCE_CREATE receives a page shift, a DMA window size and
|
||||
a number of TCE table levels (if a TCE table is going to be big enough and
|
||||
the kernel may not be able to allocate enough of physically contiguous memory).
|
||||
It creates a new window in the available slot and returns the bus address where
|
||||
the new window starts. Due to hardware limitation, the user space cannot choose
|
||||
the location of DMA windows.
|
||||
|
||||
VFIO_IOMMU_SPAPR_TCE_REMOVE receives the bus start address of the window
|
||||
and removes it.
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
[1] VFIO was originally an acronym for "Virtual Function I/O" in its
|
||||
|
|
|
|||
|
|
@ -2464,7 +2464,6 @@ F: Documentation/devicetree/bindings/net/ieee802154/cc2520.txt
|
|||
CELL BROADBAND ENGINE ARCHITECTURE
|
||||
M: Arnd Bergmann <arnd@arndb.de>
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
L: cbe-oss-dev@lists.ozlabs.org
|
||||
W: http://www.ibm.com/developerworks/power/cell/
|
||||
S: Supported
|
||||
F: arch/powerpc/include/asm/cell*.h
|
||||
|
|
@ -2979,7 +2978,7 @@ M: Michael Neuling <mikey@neuling.org>
|
|||
L: linuxppc-dev@lists.ozlabs.org
|
||||
S: Supported
|
||||
F: drivers/misc/cxl/
|
||||
F: include/misc/cxl.h
|
||||
F: include/misc/cxl*
|
||||
F: include/uapi/misc/cxl.h
|
||||
F: Documentation/powerpc/cxl.txt
|
||||
F: Documentation/powerpc/cxl.txt
|
||||
|
|
@ -7914,14 +7913,13 @@ F: drivers/net/wireless/prism54/
|
|||
PS3 NETWORK SUPPORT
|
||||
M: Geoff Levand <geoff@infradead.org>
|
||||
L: netdev@vger.kernel.org
|
||||
L: cbe-oss-dev@lists.ozlabs.org
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/toshiba/ps3_gelic_net.*
|
||||
|
||||
PS3 PLATFORM SUPPORT
|
||||
M: Geoff Levand <geoff@infradead.org>
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
L: cbe-oss-dev@lists.ozlabs.org
|
||||
S: Maintained
|
||||
F: arch/powerpc/boot/ps3*
|
||||
F: arch/powerpc/include/asm/lv1call.h
|
||||
|
|
@ -7935,7 +7933,7 @@ F: sound/ppc/snd_ps3*
|
|||
|
||||
PS3VRAM DRIVER
|
||||
M: Jim Paris <jim@jtan.com>
|
||||
L: cbe-oss-dev@lists.ozlabs.org
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
S: Maintained
|
||||
F: drivers/block/ps3vram.c
|
||||
|
||||
|
|
@ -9420,7 +9418,6 @@ F: drivers/net/ethernet/toshiba/spider_net*
|
|||
SPU FILE SYSTEM
|
||||
M: Jeremy Kerr <jk@ozlabs.org>
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
L: cbe-oss-dev@lists.ozlabs.org
|
||||
W: http://www.ibm.com/developerworks/power/cell/
|
||||
S: Supported
|
||||
F: Documentation/filesystems/spufs.txt
|
||||
|
|
|
|||
|
|
@ -19,6 +19,14 @@ config PPC_WERROR
|
|||
depends on !PPC_DISABLE_WERROR
|
||||
default y
|
||||
|
||||
config STRICT_MM_TYPECHECKS
|
||||
bool "Do extra type checking on mm types"
|
||||
default n
|
||||
help
|
||||
This option turns on extra type checking for some mm related types.
|
||||
|
||||
If you don't know what this means, say N.
|
||||
|
||||
config PRINT_STACK_DEPTH
|
||||
int "Stack depth to print" if DEBUG_KERNEL
|
||||
default 64
|
||||
|
|
|
|||
|
|
@ -66,7 +66,10 @@ endif
|
|||
UTS_MACHINE := $(OLDARCH)
|
||||
|
||||
ifeq ($(CONFIG_CPU_LITTLE_ENDIAN),y)
|
||||
override CC += -mlittle-endian -mno-strict-align
|
||||
override CC += -mlittle-endian
|
||||
ifneq ($(COMPILER),clang)
|
||||
override CC += -mno-strict-align
|
||||
endif
|
||||
override AS += -mlittle-endian
|
||||
override LD += -EL
|
||||
override CROSS32CC += -mlittle-endian
|
||||
|
|
@ -113,14 +116,14 @@ else
|
|||
endif
|
||||
endif
|
||||
|
||||
CFLAGS-$(CONFIG_PPC64) := -mtraceback=no
|
||||
CFLAGS-$(CONFIG_PPC64) := $(call cc-option,-mtraceback=no)
|
||||
ifeq ($(CONFIG_CPU_LITTLE_ENDIAN),y)
|
||||
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2,-mcall-aixdesc)
|
||||
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2,$(call cc-option,-mcall-aixdesc))
|
||||
AFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2)
|
||||
else
|
||||
CFLAGS-$(CONFIG_PPC64) += -mcall-aixdesc
|
||||
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcall-aixdesc)
|
||||
endif
|
||||
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcmodel=medium,-mminimal-toc)
|
||||
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcmodel=medium,$(call cc-option,-mminimal-toc))
|
||||
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mno-pointers-to-nested-functions)
|
||||
CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 $(MULTIPLEWORD)
|
||||
|
||||
|
|
@ -160,7 +163,8 @@ asinstr := $(call as-instr,lis 9$(comma)foo@high,-DHAVE_AS_ATHIGH=1)
|
|||
|
||||
KBUILD_CPPFLAGS += -Iarch/$(ARCH) $(asinstr)
|
||||
KBUILD_AFLAGS += -Iarch/$(ARCH) $(AFLAGS-y)
|
||||
KBUILD_CFLAGS += -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y)
|
||||
KBUILD_CFLAGS += $(call cc-option,-msoft-float)
|
||||
KBUILD_CFLAGS += -pipe -Iarch/$(ARCH) $(CFLAGS-y)
|
||||
CPP = $(CC) -E $(KBUILD_CFLAGS)
|
||||
|
||||
CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__
|
||||
|
|
@ -192,7 +196,7 @@ KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
|
|||
|
||||
# Never use string load/store instructions as they are
|
||||
# often slow when they are implemented at all
|
||||
KBUILD_CFLAGS += -mno-string
|
||||
KBUILD_CFLAGS += $(call cc-option,-mno-string)
|
||||
|
||||
ifeq ($(CONFIG_6xx),y)
|
||||
KBUILD_CFLAGS += -mcpu=powerpc
|
||||
|
|
@ -269,6 +273,21 @@ bootwrapper_install:
|
|||
%.dtb: scripts
|
||||
$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
|
||||
|
||||
# Used to create 'merged defconfigs'
|
||||
# To use it $(call) it with the first argument as the base defconfig
|
||||
# and the second argument as a space separated list of .config files to merge,
|
||||
# without the .config suffix.
|
||||
define merge_into_defconfig
|
||||
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \
|
||||
-m -O $(objtree) $(srctree)/arch/$(ARCH)/configs/$(1) \
|
||||
$(foreach config,$(2),$(srctree)/arch/$(ARCH)/configs/$(config).config)
|
||||
+$(Q)$(MAKE) -f $(srctree)/Makefile olddefconfig
|
||||
endef
|
||||
|
||||
PHONY += pseries_le_defconfig
|
||||
pseries_le_defconfig:
|
||||
$(call merge_into_defconfig,pseries_defconfig,le)
|
||||
|
||||
define archhelp
|
||||
@echo '* zImage - Build default images selected by kernel config'
|
||||
@echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
|
||||
|
|
@ -314,7 +333,8 @@ TOUT := .tmp_gas_check
|
|||
# - Require gcc 4.0 or above on 64-bit
|
||||
# - gcc-4.2.0 has issues compiling modules on 64-bit
|
||||
checkbin:
|
||||
@if test "$(cc-version)" = "0304" ; then \
|
||||
@if test "${COMPILER}" != "clang" \
|
||||
&& test "$(cc-version)" = "0304" ; then \
|
||||
if ! /bin/echo mftb 5 | $(AS) -v -mppc -many -o $(TOUT) >/dev/null 2>&1 ; then \
|
||||
echo -n '*** ${VERSION}.${PATCHLEVEL} kernels no longer build '; \
|
||||
echo 'correctly with gcc-3.4 and your version of binutils.'; \
|
||||
|
|
@ -322,13 +342,15 @@ checkbin:
|
|||
false; \
|
||||
fi ; \
|
||||
fi
|
||||
@if test "$(cc-version)" -lt "0400" \
|
||||
@if test "${COMPILER}" != "clang" \
|
||||
&& test "$(cc-version)" -lt "0400" \
|
||||
&& test "x${CONFIG_PPC64}" = "xy" ; then \
|
||||
echo -n "Sorry, GCC v4.0 or above is required to build " ; \
|
||||
echo "the 64-bit powerpc kernel." ; \
|
||||
false ; \
|
||||
fi
|
||||
@if test "$(cc-fullversion)" = "040200" \
|
||||
@if test "${COMPILER}" != "clang" \
|
||||
&& test "$(cc-fullversion)" = "040200" \
|
||||
&& test "x${CONFIG_MODULES}${CONFIG_PPC64}" = "xyy" ; then \
|
||||
echo -n '*** GCC-4.2.0 cannot compile the 64-bit powerpc ' ; \
|
||||
echo 'kernel with modules enabled.' ; \
|
||||
|
|
@ -336,6 +358,14 @@ checkbin:
|
|||
echo 'disable kernel modules' ; \
|
||||
false ; \
|
||||
fi
|
||||
@if test "x${CONFIG_CPU_LITTLE_ENDIAN}" = "xy" \
|
||||
&& $(LD) --version | head -1 | grep ' 2\.24$$' >/dev/null ; then \
|
||||
echo -n '*** binutils 2.24 miscompiles weak symbols ' ; \
|
||||
echo 'in some circumstances.' ; \
|
||||
echo -n '*** Please use a different binutils version.' ; \
|
||||
false ; \
|
||||
fi
|
||||
|
||||
|
||||
CLEAN_FILES += $(TOUT)
|
||||
|
||||
|
|
|
|||
|
|
@ -106,6 +106,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
|
|
@ -116,6 +124,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x2000000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff6000000 {
|
||||
ranges = <0x0 0xf 0xf6000000 0x2000000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -80,20 +80,9 @@
|
|||
compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
|
||||
};
|
||||
|
||||
/include/ "qoriq-clockgen2.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-2.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
|
||||
<&pll1 0>, <&pll1 1>, <&pll1 2>;
|
||||
clock-names = "pll0", "pll0-div2", "pll0-div4",
|
||||
"pll1", "pll1-div2", "pll1-div4";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
compatible = "fsl,b4420-clockgen", "fsl,b4-clockgen",
|
||||
"fsl,qoriq-clockgen-2.0";
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
|
|
|
|||
|
|
@ -167,6 +167,75 @@
|
|||
};
|
||||
};
|
||||
|
||||
&qportals {
|
||||
qportal14: qman-portal@38000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x38000 0x4000>, <0x100e000 0x1000>;
|
||||
interrupts = <132 0x2 0 0>;
|
||||
cell-index = <0xe>;
|
||||
};
|
||||
qportal15: qman-portal@3c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
|
||||
interrupts = <134 0x2 0 0>;
|
||||
cell-index = <0xf>;
|
||||
};
|
||||
qportal16: qman-portal@40000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x40000 0x4000>, <0x1010000 0x1000>;
|
||||
interrupts = <136 0x2 0 0>;
|
||||
cell-index = <0x10>;
|
||||
};
|
||||
qportal17: qman-portal@44000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x44000 0x4000>, <0x1011000 0x1000>;
|
||||
interrupts = <138 0x2 0 0>;
|
||||
cell-index = <0x11>;
|
||||
};
|
||||
qportal18: qman-portal@48000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x48000 0x4000>, <0x1012000 0x1000>;
|
||||
interrupts = <140 0x2 0 0>;
|
||||
cell-index = <0x12>;
|
||||
};
|
||||
qportal19: qman-portal@4c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
|
||||
interrupts = <142 0x2 0 0>;
|
||||
cell-index = <0x13>;
|
||||
};
|
||||
qportal20: qman-portal@50000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x50000 0x4000>, <0x1014000 0x1000>;
|
||||
interrupts = <144 0x2 0 0>;
|
||||
cell-index = <0x14>;
|
||||
};
|
||||
qportal21: qman-portal@54000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x54000 0x4000>, <0x1015000 0x1000>;
|
||||
interrupts = <146 0x2 0 0>;
|
||||
cell-index = <0x15>;
|
||||
};
|
||||
qportal22: qman-portal@58000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x58000 0x4000>, <0x1016000 0x1000>;
|
||||
interrupts = <148 0x2 0 0>;
|
||||
cell-index = <0x16>;
|
||||
};
|
||||
qportal23: qman-portal@5c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x5c000 0x4000>, <0x1017000 0x1000>;
|
||||
interrupts = <150 0x2 0 0>;
|
||||
cell-index = <0x17>;
|
||||
};
|
||||
qportal24: qman-portal@60000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x60000 0x4000>, <0x1018000 0x1000>;
|
||||
interrupts = <152 0x2 0 0>;
|
||||
cell-index = <0x18>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
|
|
@ -182,20 +251,9 @@
|
|||
compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
|
||||
};
|
||||
|
||||
/include/ "qoriq-clockgen2.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-2.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
|
||||
<&pll1 0>, <&pll1 1>, <&pll1 2>;
|
||||
clock-names = "pll0", "pll0-div2", "pll0-div4",
|
||||
"pll1", "pll1-div2", "pll1-div4";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
compatible = "fsl,b4860-clockgen", "fsl,b4-clockgen",
|
||||
"fsl,qoriq-clockgen-2.0";
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
|
|
|
|||
|
|
@ -37,6 +37,16 @@
|
|||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -210,6 +220,97 @@
|
|||
};
|
||||
};
|
||||
|
||||
&qportals {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
qportal0: qman-portal@0 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x0 0x4000>, <0x1000000 0x1000>;
|
||||
interrupts = <104 0x2 0 0>;
|
||||
cell-index = <0x0>;
|
||||
};
|
||||
qportal1: qman-portal@4000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x4000 0x4000>, <0x1001000 0x1000>;
|
||||
interrupts = <106 0x2 0 0>;
|
||||
cell-index = <0x1>;
|
||||
};
|
||||
qportal2: qman-portal@8000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x8000 0x4000>, <0x1002000 0x1000>;
|
||||
interrupts = <108 0x2 0 0>;
|
||||
cell-index = <0x2>;
|
||||
};
|
||||
qportal3: qman-portal@c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xc000 0x4000>, <0x1003000 0x1000>;
|
||||
interrupts = <110 0x2 0 0>;
|
||||
cell-index = <0x3>;
|
||||
};
|
||||
qportal4: qman-portal@10000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x10000 0x4000>, <0x1004000 0x1000>;
|
||||
interrupts = <112 0x2 0 0>;
|
||||
cell-index = <0x4>;
|
||||
};
|
||||
qportal5: qman-portal@14000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x14000 0x4000>, <0x1005000 0x1000>;
|
||||
interrupts = <114 0x2 0 0>;
|
||||
cell-index = <0x5>;
|
||||
};
|
||||
qportal6: qman-portal@18000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x18000 0x4000>, <0x1006000 0x1000>;
|
||||
interrupts = <116 0x2 0 0>;
|
||||
cell-index = <0x6>;
|
||||
};
|
||||
qportal7: qman-portal@1c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
|
||||
interrupts = <118 0x2 0 0>;
|
||||
cell-index = <0x7>;
|
||||
};
|
||||
qportal8: qman-portal@20000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x20000 0x4000>, <0x1008000 0x1000>;
|
||||
interrupts = <120 0x2 0 0>;
|
||||
cell-index = <0x8>;
|
||||
};
|
||||
qportal9: qman-portal@24000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x24000 0x4000>, <0x1009000 0x1000>;
|
||||
interrupts = <122 0x2 0 0>;
|
||||
cell-index = <0x9>;
|
||||
};
|
||||
qportal10: qman-portal@28000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x28000 0x4000>, <0x100a000 0x1000>;
|
||||
interrupts = <124 0x2 0 0>;
|
||||
cell-index = <0xa>;
|
||||
};
|
||||
qportal11: qman-portal@2c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
|
||||
interrupts = <126 0x2 0 0>;
|
||||
cell-index = <0xb>;
|
||||
};
|
||||
qportal12: qman-portal@30000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x30000 0x4000>, <0x100c000 0x1000>;
|
||||
interrupts = <128 0x2 0 0>;
|
||||
cell-index = <0xc>;
|
||||
};
|
||||
qportal13: qman-portal@34000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x34000 0x4000>, <0x100d000 0x1000>;
|
||||
interrupts = <130 0x2 0 0>;
|
||||
cell-index = <0xd>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -296,9 +397,21 @@
|
|||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-clockgen2.dtsi"
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-2.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
|
||||
<&pll1 0>, <&pll1 1>, <&pll1 2>;
|
||||
clock-names = "pll0", "pll0-div2", "pll0-div4",
|
||||
"pll1", "pll1-div2", "pll1-div4";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
|
|
@ -343,6 +456,11 @@
|
|||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-sec5.3-0.dtsi"
|
||||
|
||||
/include/ "qoriq-qman3.dtsi"
|
||||
qman: qman@318000 {
|
||||
interrupts = <16 2 1 28>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-bman1.dtsi"
|
||||
bman: bman@31a000 {
|
||||
interrupts = <16 2 1 29>;
|
||||
|
|
|
|||
|
|
@ -37,6 +37,16 @@
|
|||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -102,6 +112,31 @@
|
|||
};
|
||||
};
|
||||
|
||||
&qportals {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
qportal0: qman-portal@0 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x0 0x4000>, <0x100000 0x1000>;
|
||||
interrupts = <29 2 0 0>;
|
||||
cell-index = <0>;
|
||||
};
|
||||
qportal1: qman-portal@4000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x4000 0x4000>, <0x101000 0x1000>;
|
||||
interrupts = <31 2 0 0>;
|
||||
cell-index = <1>;
|
||||
};
|
||||
qportal2: qman-portal@8000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x8000 0x4000>, <0x102000 0x1000>;
|
||||
interrupts = <33 2 0 0>;
|
||||
cell-index = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&bportals {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -248,6 +283,14 @@
|
|||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
qman: qman@88000 {
|
||||
compatible = "fsl,qman";
|
||||
reg = <0x88000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
fsl,qman-portals = <&qportals>;
|
||||
memory-region = <&qman_fqd &qman_pfdr>;
|
||||
};
|
||||
|
||||
bman: bman@8a000 {
|
||||
compatible = "fsl,bman";
|
||||
reg = <0x8a000 0x1000>;
|
||||
|
|
|
|||
|
|
@ -37,6 +37,16 @@
|
|||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&lbc {
|
||||
compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
|
|
@ -223,6 +233,8 @@
|
|||
|
||||
/include/ "qoriq-bman1-portals.dtsi"
|
||||
|
||||
/include/ "qoriq-qman1-portals.dtsi"
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -416,5 +428,6 @@ crypto: crypto@300000 {
|
|||
fsl,iommu-parent = <&pamu1>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-qman1.dtsi"
|
||||
/include/ "qoriq-bman1.dtsi"
|
||||
};
|
||||
|
|
|
|||
|
|
@ -37,6 +37,16 @@
|
|||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&lbc {
|
||||
compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
|
|
@ -250,6 +260,8 @@
|
|||
|
||||
/include/ "qoriq-bman1-portals.dtsi"
|
||||
|
||||
/include/ "qoriq-qman1-portals.dtsi"
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -443,5 +455,6 @@ crypto: crypto@300000 {
|
|||
fsl,iommu-parent = <&pamu1>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-qman1.dtsi"
|
||||
/include/ "qoriq-bman1.dtsi"
|
||||
};
|
||||
|
|
|
|||
|
|
@ -37,6 +37,16 @@
|
|||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
};
|
||||
|
||||
&lbc {
|
||||
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
|
|
@ -250,6 +260,8 @@
|
|||
|
||||
/include/ "qoriq-bman1-portals.dtsi"
|
||||
|
||||
/include/ "qoriq-qman1-portals.dtsi"
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -499,5 +511,6 @@ crypto: crypto@300000 {
|
|||
fsl,iommu-parent = <&pamu1>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-qman1.dtsi"
|
||||
/include/ "qoriq-bman1.dtsi"
|
||||
};
|
||||
|
|
|
|||
|
|
@ -37,6 +37,16 @@
|
|||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&lbc {
|
||||
compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
|
|
@ -247,6 +257,8 @@
|
|||
|
||||
/include/ "qoriq-bman1-portals.dtsi"
|
||||
|
||||
/include/ "qoriq-qman1-portals.dtsi"
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -429,6 +441,7 @@
|
|||
fsl,iommu-parent = <&pamu1>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-qman1.dtsi"
|
||||
/include/ "qoriq-bman1.dtsi"
|
||||
|
||||
/include/ "qoriq-raid1.0-0.dtsi"
|
||||
|
|
|
|||
|
|
@ -37,6 +37,16 @@
|
|||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&lbc {
|
||||
compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
|
|
@ -202,6 +212,8 @@
|
|||
|
||||
/include/ "qoriq-bman1-portals.dtsi"
|
||||
|
||||
/include/ "qoriq-qman1-portals.dtsi"
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -408,5 +420,6 @@
|
|||
fsl,iommu-parent = <&pamu4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-qman1.dtsi"
|
||||
/include/ "qoriq-bman1.dtsi"
|
||||
};
|
||||
|
|
|
|||
|
|
@ -41,61 +41,61 @@
|
|||
compatible = "fsl,qman-portal";
|
||||
reg = <0x0 0x4000>, <0x100000 0x1000>;
|
||||
interrupts = <104 2 0 0>;
|
||||
fsl,qman-channel-id = <0x0>;
|
||||
cell-index = <0x0>;
|
||||
};
|
||||
qportal1: qman-portal@4000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x4000 0x4000>, <0x101000 0x1000>;
|
||||
interrupts = <106 2 0 0>;
|
||||
fsl,qman-channel-id = <1>;
|
||||
cell-index = <1>;
|
||||
};
|
||||
qportal2: qman-portal@8000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x8000 0x4000>, <0x102000 0x1000>;
|
||||
interrupts = <108 2 0 0>;
|
||||
fsl,qman-channel-id = <2>;
|
||||
cell-index = <2>;
|
||||
};
|
||||
qportal3: qman-portal@c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xc000 0x4000>, <0x103000 0x1000>;
|
||||
interrupts = <110 2 0 0>;
|
||||
fsl,qman-channel-id = <3>;
|
||||
cell-index = <3>;
|
||||
};
|
||||
qportal4: qman-portal@10000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x10000 0x4000>, <0x104000 0x1000>;
|
||||
interrupts = <112 2 0 0>;
|
||||
fsl,qman-channel-id = <4>;
|
||||
cell-index = <4>;
|
||||
};
|
||||
qportal5: qman-portal@14000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x14000 0x4000>, <0x105000 0x1000>;
|
||||
interrupts = <114 2 0 0>;
|
||||
fsl,qman-channel-id = <5>;
|
||||
cell-index = <5>;
|
||||
};
|
||||
qportal6: qman-portal@18000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x18000 0x4000>, <0x106000 0x1000>;
|
||||
interrupts = <116 2 0 0>;
|
||||
fsl,qman-channel-id = <6>;
|
||||
cell-index = <6>;
|
||||
};
|
||||
|
||||
qportal7: qman-portal@1c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x1c000 0x4000>, <0x107000 0x1000>;
|
||||
interrupts = <118 2 0 0>;
|
||||
fsl,qman-channel-id = <7>;
|
||||
cell-index = <7>;
|
||||
};
|
||||
qportal8: qman-portal@20000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x20000 0x4000>, <0x108000 0x1000>;
|
||||
interrupts = <120 2 0 0>;
|
||||
fsl,qman-channel-id = <8>;
|
||||
cell-index = <8>;
|
||||
};
|
||||
qportal9: qman-portal@24000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x24000 0x4000>, <0x109000 0x1000>;
|
||||
interrupts = <122 2 0 0>;
|
||||
fsl,qman-channel-id = <9>;
|
||||
cell-index = <9>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,330 @@
|
|||
/*
|
||||
* T1023 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
compatible = "fsl,t1023-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
interrupts = <20 2 0 0>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <20 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&pci1 {
|
||||
compatible = "fsl,t1023-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
interrupts = <21 2 0 0>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <21 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&pci2 {
|
||||
compatible = "fsl,t1023-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
interrupts = <22 2 0 0>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <22 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,t1023-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,t1023-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
reg = <0x1000 0x1000 0x1002000 0x10000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0x1A000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,t1023-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,t1023-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,t1023-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,t1023-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x30000 0x1000 0x1022000 0x10000>;
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,t1023-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x31000 0x1000 0x1042000 0x10000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@100000 {
|
||||
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x100000 0x1000 0x101000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@108000 {
|
||||
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x108000 0x1000 0x109000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <16>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v5.0",
|
||||
"fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,t1023-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000>;
|
||||
interrupts = <16 2 1 27>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet2-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x1000>;
|
||||
ranges = <0 0x20000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <128 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,t1023-device-config", "fsl,qoriq-device-config-2.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-clockgen2.dtsi"
|
||||
global-utilities@e1000 {
|
||||
compatible = "fsl,t1023-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 4>;
|
||||
compatible = "fsl,core-mux-clock";
|
||||
clocks = <&pll0 0>, <&pll0 1>;
|
||||
clock-names = "pll0_0", "pll0_1";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 4>;
|
||||
compatible = "fsl,core-mux-clock";
|
||||
clocks = <&pll0 0>, <&pll0 1>;
|
||||
clock-names = "pll0_0", "pll0_1";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,t1023-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,t1023-sfp";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,t1023-serdes";
|
||||
reg = <0xea000 0x4000>;
|
||||
};
|
||||
|
||||
scfg: global-utilities@fc000 {
|
||||
compatible = "fsl,t1023-scfg";
|
||||
reg = <0xfc000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "elo3-dma-0.dtsi"
|
||||
/include/ "elo3-dma-1.dtsi"
|
||||
|
||||
/include/ "qoriq-espi-0.dtsi"
|
||||
spi@110000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-esdhc-0.dtsi"
|
||||
sdhc@114000 {
|
||||
compatible = "fsl,t1023-esdhc", "fsl,esdhc";
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
|
||||
sdhci,auto-cmd12;
|
||||
no-1-8-v;
|
||||
};
|
||||
/include/ "qoriq-i2c-0.dtsi"
|
||||
/include/ "qoriq-i2c-1.dtsi"
|
||||
/include/ "qoriq-duart-0.dtsi"
|
||||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-gpio-0.dtsi"
|
||||
/include/ "qoriq-gpio-1.dtsi"
|
||||
/include/ "qoriq-gpio-2.dtsi"
|
||||
/include/ "qoriq-gpio-3.dtsi"
|
||||
/include/ "qoriq-usb2-mph-0.dtsi"
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
|
||||
phy_type = "utmi";
|
||||
port0;
|
||||
};
|
||||
/include/ "qoriq-usb2-dr-0.dtsi"
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
|
||||
dr_mode = "host";
|
||||
phy_type = "utmi";
|
||||
};
|
||||
/include/ "qoriq-sata2-0.dtsi"
|
||||
sata@220000 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-sec5.0-0.dtsi"
|
||||
};
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
* T1024 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "t1023si-post.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
vga = &display;
|
||||
display = &display;
|
||||
};
|
||||
|
||||
qe:qe@ffe140000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0x0 0xf 0xfe140000 0x40000>;
|
||||
reg = <0xf 0xfe140000 0 0x480>;
|
||||
fsl,qe-num-riscs = <1>;
|
||||
fsl,qe-num-snums = <28>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
display:display@180000 {
|
||||
compatible = "fsl,t1024-diu", "fsl,diu";
|
||||
reg = <0x180000 1000>;
|
||||
interrupts = <74 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&qe {
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2200 {
|
||||
cell-index = <3>;
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x6000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data", "fsl,cpm-muram-data";
|
||||
reg = <0x0 0x6000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* T1024/T1023 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e5500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
sdhc = &sdhc;
|
||||
|
||||
crypto = &crypto;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e5500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,e5500@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
clocks = <&mux1>;
|
||||
next-level-cache = <&L2_2>;
|
||||
L2_2: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -37,6 +37,16 @@
|
|||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -280,6 +290,73 @@
|
|||
};
|
||||
};
|
||||
|
||||
&qportals {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
qportal0: qman-portal@0 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x0 0x4000>, <0x1000000 0x1000>;
|
||||
interrupts = <104 0x2 0 0>;
|
||||
cell-index = <0x0>;
|
||||
};
|
||||
qportal1: qman-portal@4000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x4000 0x4000>, <0x1001000 0x1000>;
|
||||
interrupts = <106 0x2 0 0>;
|
||||
cell-index = <0x1>;
|
||||
};
|
||||
qportal2: qman-portal@8000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x8000 0x4000>, <0x1002000 0x1000>;
|
||||
interrupts = <108 0x2 0 0>;
|
||||
cell-index = <0x2>;
|
||||
};
|
||||
qportal3: qman-portal@c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xc000 0x4000>, <0x1003000 0x1000>;
|
||||
interrupts = <110 0x2 0 0>;
|
||||
cell-index = <0x3>;
|
||||
};
|
||||
qportal4: qman-portal@10000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x10000 0x4000>, <0x1004000 0x1000>;
|
||||
interrupts = <112 0x2 0 0>;
|
||||
cell-index = <0x4>;
|
||||
};
|
||||
qportal5: qman-portal@14000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x14000 0x4000>, <0x1005000 0x1000>;
|
||||
interrupts = <114 0x2 0 0>;
|
||||
cell-index = <0x5>;
|
||||
};
|
||||
qportal6: qman-portal@18000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x18000 0x4000>, <0x1006000 0x1000>;
|
||||
interrupts = <116 0x2 0 0>;
|
||||
cell-index = <0x6>;
|
||||
};
|
||||
qportal7: qman-portal@1c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
|
||||
interrupts = <118 0x2 0 0>;
|
||||
cell-index = <0x7>;
|
||||
};
|
||||
qportal8: qman-portal@20000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x20000 0x4000>, <0x1008000 0x1000>;
|
||||
interrupts = <120 0x2 0 0>;
|
||||
cell-index = <0x8>;
|
||||
};
|
||||
qportal9: qman-portal@24000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x24000 0x4000>, <0x1009000 0x1000>;
|
||||
interrupts = <122 0x2 0 0>;
|
||||
cell-index = <0x9>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -463,5 +540,6 @@
|
|||
fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
|
||||
};
|
||||
/include/ "qoriq-sec5.0-0.dtsi"
|
||||
/include/ "qoriq-qman3.dtsi"
|
||||
/include/ "qoriq-bman1.dtsi"
|
||||
};
|
||||
|
|
|
|||
|
|
@ -37,6 +37,16 @@
|
|||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -326,6 +336,121 @@
|
|||
};
|
||||
};
|
||||
|
||||
&qportals {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
qportal0: qman-portal@0 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x0 0x4000>, <0x1000000 0x1000>;
|
||||
interrupts = <104 0x2 0 0>;
|
||||
cell-index = <0x0>;
|
||||
};
|
||||
qportal1: qman-portal@4000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x4000 0x4000>, <0x1001000 0x1000>;
|
||||
interrupts = <106 0x2 0 0>;
|
||||
cell-index = <0x1>;
|
||||
};
|
||||
qportal2: qman-portal@8000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x8000 0x4000>, <0x1002000 0x1000>;
|
||||
interrupts = <108 0x2 0 0>;
|
||||
cell-index = <0x2>;
|
||||
};
|
||||
qportal3: qman-portal@c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xc000 0x4000>, <0x1003000 0x1000>;
|
||||
interrupts = <110 0x2 0 0>;
|
||||
cell-index = <0x3>;
|
||||
};
|
||||
qportal4: qman-portal@10000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x10000 0x4000>, <0x1004000 0x1000>;
|
||||
interrupts = <112 0x2 0 0>;
|
||||
cell-index = <0x4>;
|
||||
};
|
||||
qportal5: qman-portal@14000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x14000 0x4000>, <0x1005000 0x1000>;
|
||||
interrupts = <114 0x2 0 0>;
|
||||
cell-index = <0x5>;
|
||||
};
|
||||
qportal6: qman-portal@18000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x18000 0x4000>, <0x1006000 0x1000>;
|
||||
interrupts = <116 0x2 0 0>;
|
||||
cell-index = <0x6>;
|
||||
};
|
||||
qportal7: qman-portal@1c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
|
||||
interrupts = <118 0x2 0 0>;
|
||||
cell-index = <0x7>;
|
||||
};
|
||||
qportal8: qman-portal@20000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x20000 0x4000>, <0x1008000 0x1000>;
|
||||
interrupts = <120 0x2 0 0>;
|
||||
cell-index = <0x8>;
|
||||
};
|
||||
qportal9: qman-portal@24000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x24000 0x4000>, <0x1009000 0x1000>;
|
||||
interrupts = <122 0x2 0 0>;
|
||||
cell-index = <0x9>;
|
||||
};
|
||||
qportal10: qman-portal@28000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x28000 0x4000>, <0x100a000 0x1000>;
|
||||
interrupts = <124 0x2 0 0>;
|
||||
cell-index = <0xa>;
|
||||
};
|
||||
qportal11: qman-portal@2c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
|
||||
interrupts = <126 0x2 0 0>;
|
||||
cell-index = <0xb>;
|
||||
};
|
||||
qportal12: qman-portal@30000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x30000 0x4000>, <0x100c000 0x1000>;
|
||||
interrupts = <128 0x2 0 0>;
|
||||
cell-index = <0xc>;
|
||||
};
|
||||
qportal13: qman-portal@34000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x34000 0x4000>, <0x100d000 0x1000>;
|
||||
interrupts = <130 0x2 0 0>;
|
||||
cell-index = <0xd>;
|
||||
};
|
||||
qportal14: qman-portal@38000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x38000 0x4000>, <0x100e000 0x1000>;
|
||||
interrupts = <132 0x2 0 0>;
|
||||
cell-index = <0xe>;
|
||||
};
|
||||
qportal15: qman-portal@3c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
|
||||
interrupts = <134 0x2 0 0>;
|
||||
cell-index = <0xf>;
|
||||
};
|
||||
qportal16: qman-portal@40000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x40000 0x4000>, <0x1010000 0x1000>;
|
||||
interrupts = <136 0x2 0 0>;
|
||||
cell-index = <0x10>;
|
||||
};
|
||||
qportal17: qman-portal@44000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x44000 0x4000>, <0x1011000 0x1000>;
|
||||
interrupts = <138 0x2 0 0>;
|
||||
cell-index = <0x11>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -417,7 +542,7 @@
|
|||
compatible = "fsl,qoriq-core-mux-2.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
|
||||
<&pll1 0>, <&pll1 1>, <&pll1 2>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1-div4",
|
||||
clock-names = "pll0", "pll0-div2", "pll0-div4",
|
||||
"pll1", "pll1-div2", "pll1-div4";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
|
@ -428,7 +553,7 @@
|
|||
compatible = "fsl,qoriq-core-mux-2.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
|
||||
<&pll1 0>, <&pll1 1>, <&pll1 2>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1-div4",
|
||||
clock-names = "pll0", "pll0-div2", "pll0-div4",
|
||||
"pll1", "pll1-div2", "pll1-div4";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
|
@ -502,6 +627,7 @@
|
|||
phy_type = "utmi";
|
||||
};
|
||||
/include/ "qoriq-sec5.2-0.dtsi"
|
||||
/include/ "qoriq-qman3.dtsi"
|
||||
/include/ "qoriq-bman1.dtsi"
|
||||
|
||||
L2_1: l2-cache-controller@c20000 {
|
||||
|
|
|
|||
|
|
@ -37,6 +37,16 @@
|
|||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -556,6 +566,313 @@
|
|||
};
|
||||
};
|
||||
|
||||
&qportals {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
qportal0: qman-portal@0 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x0 0x4000>, <0x1000000 0x1000>;
|
||||
interrupts = <104 0x2 0 0>;
|
||||
cell-index = <0x0>;
|
||||
};
|
||||
qportal1: qman-portal@4000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x4000 0x4000>, <0x1001000 0x1000>;
|
||||
interrupts = <106 0x2 0 0>;
|
||||
cell-index = <0x1>;
|
||||
};
|
||||
qportal2: qman-portal@8000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x8000 0x4000>, <0x1002000 0x1000>;
|
||||
interrupts = <108 0x2 0 0>;
|
||||
cell-index = <0x2>;
|
||||
};
|
||||
qportal3: qman-portal@c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xc000 0x4000>, <0x1003000 0x1000>;
|
||||
interrupts = <110 0x2 0 0>;
|
||||
cell-index = <0x3>;
|
||||
};
|
||||
qportal4: qman-portal@10000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x10000 0x4000>, <0x1004000 0x1000>;
|
||||
interrupts = <112 0x2 0 0>;
|
||||
cell-index = <0x4>;
|
||||
};
|
||||
qportal5: qman-portal@14000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x14000 0x4000>, <0x1005000 0x1000>;
|
||||
interrupts = <114 0x2 0 0>;
|
||||
cell-index = <0x5>;
|
||||
};
|
||||
qportal6: qman-portal@18000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x18000 0x4000>, <0x1006000 0x1000>;
|
||||
interrupts = <116 0x2 0 0>;
|
||||
cell-index = <0x6>;
|
||||
};
|
||||
qportal7: qman-portal@1c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
|
||||
interrupts = <118 0x2 0 0>;
|
||||
cell-index = <0x7>;
|
||||
};
|
||||
qportal8: qman-portal@20000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x20000 0x4000>, <0x1008000 0x1000>;
|
||||
interrupts = <120 0x2 0 0>;
|
||||
cell-index = <0x8>;
|
||||
};
|
||||
qportal9: qman-portal@24000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x24000 0x4000>, <0x1009000 0x1000>;
|
||||
interrupts = <122 0x2 0 0>;
|
||||
cell-index = <0x9>;
|
||||
};
|
||||
qportal10: qman-portal@28000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x28000 0x4000>, <0x100a000 0x1000>;
|
||||
interrupts = <124 0x2 0 0>;
|
||||
cell-index = <0xa>;
|
||||
};
|
||||
qportal11: qman-portal@2c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
|
||||
interrupts = <126 0x2 0 0>;
|
||||
cell-index = <0xb>;
|
||||
};
|
||||
qportal12: qman-portal@30000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x30000 0x4000>, <0x100c000 0x1000>;
|
||||
interrupts = <128 0x2 0 0>;
|
||||
cell-index = <0xc>;
|
||||
};
|
||||
qportal13: qman-portal@34000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x34000 0x4000>, <0x100d000 0x1000>;
|
||||
interrupts = <130 0x2 0 0>;
|
||||
cell-index = <0xd>;
|
||||
};
|
||||
qportal14: qman-portal@38000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x38000 0x4000>, <0x100e000 0x1000>;
|
||||
interrupts = <132 0x2 0 0>;
|
||||
cell-index = <0xe>;
|
||||
};
|
||||
qportal15: qman-portal@3c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
|
||||
interrupts = <134 0x2 0 0>;
|
||||
cell-index = <0xf>;
|
||||
};
|
||||
qportal16: qman-portal@40000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x40000 0x4000>, <0x1010000 0x1000>;
|
||||
interrupts = <136 0x2 0 0>;
|
||||
cell-index = <0x10>;
|
||||
};
|
||||
qportal17: qman-portal@44000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x44000 0x4000>, <0x1011000 0x1000>;
|
||||
interrupts = <138 0x2 0 0>;
|
||||
cell-index = <0x11>;
|
||||
};
|
||||
qportal18: qman-portal@48000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x48000 0x4000>, <0x1012000 0x1000>;
|
||||
interrupts = <140 0x2 0 0>;
|
||||
cell-index = <0x12>;
|
||||
};
|
||||
qportal19: qman-portal@4c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
|
||||
interrupts = <142 0x2 0 0>;
|
||||
cell-index = <0x13>;
|
||||
};
|
||||
qportal20: qman-portal@50000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x50000 0x4000>, <0x1014000 0x1000>;
|
||||
interrupts = <144 0x2 0 0>;
|
||||
cell-index = <0x14>;
|
||||
};
|
||||
qportal21: qman-portal@54000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x54000 0x4000>, <0x1015000 0x1000>;
|
||||
interrupts = <146 0x2 0 0>;
|
||||
cell-index = <0x15>;
|
||||
};
|
||||
qportal22: qman-portal@58000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x58000 0x4000>, <0x1016000 0x1000>;
|
||||
interrupts = <148 0x2 0 0>;
|
||||
cell-index = <0x16>;
|
||||
};
|
||||
qportal23: qman-portal@5c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x5c000 0x4000>, <0x1017000 0x1000>;
|
||||
interrupts = <150 0x2 0 0>;
|
||||
cell-index = <0x17>;
|
||||
};
|
||||
qportal24: qman-portal@60000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x60000 0x4000>, <0x1018000 0x1000>;
|
||||
interrupts = <152 0x2 0 0>;
|
||||
cell-index = <0x18>;
|
||||
};
|
||||
qportal25: qman-portal@64000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x64000 0x4000>, <0x1019000 0x1000>;
|
||||
interrupts = <154 0x2 0 0>;
|
||||
cell-index = <0x19>;
|
||||
};
|
||||
qportal26: qman-portal@68000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x68000 0x4000>, <0x101a000 0x1000>;
|
||||
interrupts = <156 0x2 0 0>;
|
||||
cell-index = <0x1a>;
|
||||
};
|
||||
qportal27: qman-portal@6c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x6c000 0x4000>, <0x101b000 0x1000>;
|
||||
interrupts = <158 0x2 0 0>;
|
||||
cell-index = <0x1b>;
|
||||
};
|
||||
qportal28: qman-portal@70000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x70000 0x4000>, <0x101c000 0x1000>;
|
||||
interrupts = <160 0x2 0 0>;
|
||||
cell-index = <0x1c>;
|
||||
};
|
||||
qportal29: qman-portal@74000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x74000 0x4000>, <0x101d000 0x1000>;
|
||||
interrupts = <162 0x2 0 0>;
|
||||
cell-index = <0x1d>;
|
||||
};
|
||||
qportal30: qman-portal@78000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x78000 0x4000>, <0x101e000 0x1000>;
|
||||
interrupts = <164 0x2 0 0>;
|
||||
cell-index = <0x1e>;
|
||||
};
|
||||
qportal31: qman-portal@7c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x7c000 0x4000>, <0x101f000 0x1000>;
|
||||
interrupts = <166 0x2 0 0>;
|
||||
cell-index = <0x1f>;
|
||||
};
|
||||
qportal32: qman-portal@80000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x80000 0x4000>, <0x1020000 0x1000>;
|
||||
interrupts = <168 0x2 0 0>;
|
||||
cell-index = <0x20>;
|
||||
};
|
||||
qportal33: qman-portal@84000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x84000 0x4000>, <0x1021000 0x1000>;
|
||||
interrupts = <170 0x2 0 0>;
|
||||
cell-index = <0x21>;
|
||||
};
|
||||
qportal34: qman-portal@88000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x88000 0x4000>, <0x1022000 0x1000>;
|
||||
interrupts = <172 0x2 0 0>;
|
||||
cell-index = <0x22>;
|
||||
};
|
||||
qportal35: qman-portal@8c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x8c000 0x4000>, <0x1023000 0x1000>;
|
||||
interrupts = <174 0x2 0 0>;
|
||||
cell-index = <0x23>;
|
||||
};
|
||||
qportal36: qman-portal@90000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x90000 0x4000>, <0x1024000 0x1000>;
|
||||
interrupts = <384 0x2 0 0>;
|
||||
cell-index = <0x24>;
|
||||
};
|
||||
qportal37: qman-portal@94000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x94000 0x4000>, <0x1025000 0x1000>;
|
||||
interrupts = <386 0x2 0 0>;
|
||||
cell-index = <0x25>;
|
||||
};
|
||||
qportal38: qman-portal@98000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x98000 0x4000>, <0x1026000 0x1000>;
|
||||
interrupts = <388 0x2 0 0>;
|
||||
cell-index = <0x26>;
|
||||
};
|
||||
qportal39: qman-portal@9c000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x9c000 0x4000>, <0x1027000 0x1000>;
|
||||
interrupts = <390 0x2 0 0>;
|
||||
cell-index = <0x27>;
|
||||
};
|
||||
qportal40: qman-portal@a0000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xa0000 0x4000>, <0x1028000 0x1000>;
|
||||
interrupts = <392 0x2 0 0>;
|
||||
cell-index = <0x28>;
|
||||
};
|
||||
qportal41: qman-portal@a4000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xa4000 0x4000>, <0x1029000 0x1000>;
|
||||
interrupts = <394 0x2 0 0>;
|
||||
cell-index = <0x29>;
|
||||
};
|
||||
qportal42: qman-portal@a8000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xa8000 0x4000>, <0x102a000 0x1000>;
|
||||
interrupts = <396 0x2 0 0>;
|
||||
cell-index = <0x2a>;
|
||||
};
|
||||
qportal43: qman-portal@ac000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xac000 0x4000>, <0x102b000 0x1000>;
|
||||
interrupts = <398 0x2 0 0>;
|
||||
cell-index = <0x2b>;
|
||||
};
|
||||
qportal44: qman-portal@b0000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xb0000 0x4000>, <0x102c000 0x1000>;
|
||||
interrupts = <400 0x2 0 0>;
|
||||
cell-index = <0x2c>;
|
||||
};
|
||||
qportal45: qman-portal@b4000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xb4000 0x4000>, <0x102d000 0x1000>;
|
||||
interrupts = <402 0x2 0 0>;
|
||||
cell-index = <0x2d>;
|
||||
};
|
||||
qportal46: qman-portal@b8000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xb8000 0x4000>, <0x102e000 0x1000>;
|
||||
interrupts = <404 0x2 0 0>;
|
||||
cell-index = <0x2e>;
|
||||
};
|
||||
qportal47: qman-portal@bc000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xbc000 0x4000>, <0x102f000 0x1000>;
|
||||
interrupts = <406 0x2 0 0>;
|
||||
cell-index = <0x2f>;
|
||||
};
|
||||
qportal48: qman-portal@c0000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xc0000 0x4000>, <0x1030000 0x1000>;
|
||||
interrupts = <408 0x2 0 0>;
|
||||
cell-index = <0x30>;
|
||||
};
|
||||
qportal49: qman-portal@c4000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0xc4000 0x4000>, <0x1031000 0x1000>;
|
||||
interrupts = <410 0x2 0 0>;
|
||||
cell-index = <0x31>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -748,6 +1065,7 @@
|
|||
/include/ "qoriq-sata2-0.dtsi"
|
||||
/include/ "qoriq-sata2-1.dtsi"
|
||||
/include/ "qoriq-sec5.0-0.dtsi"
|
||||
/include/ "qoriq-qman3.dtsi"
|
||||
/include/ "qoriq-bman1.dtsi"
|
||||
|
||||
L2_1: l2-cache-controller@c20000 {
|
||||
|
|
|
|||
|
|
@ -34,6 +34,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
|
|
@ -44,6 +52,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x200000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff4200000 {
|
||||
ranges = <0x0 0xf 0xf4200000 0x200000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -58,6 +58,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
|
|
@ -68,6 +76,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x200000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff4200000 {
|
||||
ranges = <0x0 0xf 0xf4200000 0x200000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -56,6 +56,18 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff000000 {
|
||||
ranges = <0x0 0xf 0xff000000 0x200000>;
|
||||
};
|
||||
|
||||
bportals: bman-portals@ff200000 {
|
||||
|
|
|
|||
|
|
@ -54,6 +54,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
|
|
@ -64,6 +72,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x200000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff4200000 {
|
||||
ranges = <0x0 0xf 0xf4200000 0x200000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -54,6 +54,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
|
|
@ -64,6 +72,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x200000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff4200000 {
|
||||
ranges = <0x0 0xf 0xf4200000 0x200000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -54,6 +54,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
|
|
@ -64,6 +72,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x200000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff4200000 {
|
||||
ranges = <0x0 0xf 0xf4200000 0x200000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -54,6 +54,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
|
|
@ -64,6 +72,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x200000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff4200000 {
|
||||
ranges = <0x0 0xf 0xf4200000 0x200000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -54,6 +54,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
|
|
@ -64,6 +72,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x200000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff4200000 {
|
||||
ranges = <0x0 0xf 0xf4200000 0x200000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* T1023 RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "fsl/t102xsi-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,T1023RDB";
|
||||
compatible = "fsl,T1023RDB";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
1 0 0xf 0xff800000 0x00010000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x2 0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25fl512s";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>; /* input clk */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
eeprom@50 {
|
||||
compatible = "st,m24256";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
interrupts = <0x5 0x1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118100 {
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
reg = <0xf 0xfe240000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x10000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe250000 {
|
||||
reg = <0xf 0xfe250000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x10000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe260000 {
|
||||
reg = <0xf 0xfe260000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x10000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "fsl/t1023si-post.dtsi"
|
||||
|
|
@ -0,0 +1,251 @@
|
|||
/*
|
||||
* T1024 QDS Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "fsl/t102xsi-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,T1024QDS";
|
||||
compatible = "fsl,T1024QDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xff800000 0x00010000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x2 0x0 0x10000>;
|
||||
};
|
||||
|
||||
board-control@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,tetra-fpga", "fsl,fpga-qixis";
|
||||
reg = <3 0 0x300>;
|
||||
ranges = <0 3 0 0x300>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q128a11"; /* 16MB */
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
|
||||
flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf040"; /* 512KB */
|
||||
reg = <1>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
|
||||
flash@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "eon,en25s64"; /* 8MB */
|
||||
reg = <2>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
|
||||
slic@2 {
|
||||
compatible = "maxim,ds26522";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <2000000>;
|
||||
};
|
||||
|
||||
slic@3 {
|
||||
compatible = "maxim,ds26522";
|
||||
reg = <3>;
|
||||
spi-max-frequency = <2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
pca9547@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x57>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2>;
|
||||
|
||||
ina220@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
ina220@41 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
adt7461@4c {
|
||||
/* Thermal Monitor */
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
eeprom@55 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x55>;
|
||||
};
|
||||
|
||||
eeprom@56 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x56>;
|
||||
};
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x57>;
|
||||
};
|
||||
};
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
interrupts = <0x5 0x1 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
reg = <0xf 0xfe240000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x10000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe250000 {
|
||||
reg = <0xf 0xfe250000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x10000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe260000 {
|
||||
reg = <0xf 0xfe260000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x10000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "fsl/t1024si-post.dtsi"
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* T1024 RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "fsl/t102xsi-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,T1024RDB";
|
||||
compatible = "fsl,T1024RDB";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xff800000 0x00010000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x2 0x0 0x10000>;
|
||||
};
|
||||
|
||||
board-control@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,t1024-cpld";
|
||||
reg = <3 0 0x300>;
|
||||
ranges = <0 3 0 0x300>;
|
||||
bank-width = <1>;
|
||||
device-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q512ax3";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>; /* input clk */
|
||||
};
|
||||
|
||||
slic@1 {
|
||||
compatible = "maxim,ds26522";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <2000000>;
|
||||
};
|
||||
|
||||
slic@2 {
|
||||
compatible = "maxim,ds26522";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
adt7461@4c {
|
||||
/* Thermal Monitor */
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c256";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
interrupts = <0x1 0x1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118100 {
|
||||
pca9546@77 {
|
||||
compatible = "nxp,pca9546";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
reg = <0xf 0xfe240000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x10000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe250000 {
|
||||
reg = <0xf 0xfe250000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x10000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe260000 {
|
||||
reg = <0xf 0xfe260000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x10000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "fsl/t1024si-post.dtsi"
|
||||
|
|
@ -47,6 +47,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
|
|
@ -92,6 +100,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x2000000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff6000000 {
|
||||
ranges = <0x0 0xf 0xf6000000 0x2000000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -42,6 +42,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
|
|
@ -83,6 +91,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x2000000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff6000000 {
|
||||
ranges = <0x0 0xf 0xf6000000 0x2000000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -48,6 +48,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
|
|
@ -93,6 +101,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x2000000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff6000000 {
|
||||
ranges = <0x0 0xf 0xf6000000 0x2000000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -48,6 +48,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
|
|
@ -94,6 +102,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x2000000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff6000000 {
|
||||
ranges = <0x0 0xf 0xf6000000 0x2000000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -109,6 +109,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
|
|
@ -119,6 +127,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x2000000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff6000000 {
|
||||
ranges = <0x0 0xf 0xf6000000 0x2000000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -78,6 +78,14 @@
|
|||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
};
|
||||
qman_fqd: qman-fqd {
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
|
|
@ -88,6 +96,10 @@
|
|||
ranges = <0x0 0xf 0xf4000000 0x2000000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@ff6000000 {
|
||||
ranges = <0x0 0xf 0xf6000000 0x2000000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@ CONFIG_SENSORS_LM90=y
|
|||
CONFIG_WATCHDOG=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_ISP1760_HCD=y
|
||||
CONFIG_USB_ISP1760=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
|
|
@ -155,6 +155,7 @@ CONFIG_ACENIC=m
|
|||
CONFIG_ACENIC_OMIT_TIGON_I=y
|
||||
CONFIG_PCNET32=y
|
||||
CONFIG_TIGON3=y
|
||||
CONFIG_BNX2X=m
|
||||
CONFIG_CHELSIO_T1=m
|
||||
CONFIG_BE2NET=m
|
||||
CONFIG_S2IO=m
|
||||
|
|
|
|||
|
|
@ -154,6 +154,7 @@ CONFIG_ACENIC=m
|
|||
CONFIG_ACENIC_OMIT_TIGON_I=y
|
||||
CONFIG_PCNET32=y
|
||||
CONFIG_TIGON3=y
|
||||
CONFIG_BNX2X=m
|
||||
CONFIG_CHELSIO_T1=m
|
||||
CONFIG_BE2NET=m
|
||||
CONFIG_S2IO=m
|
||||
|
|
@ -297,7 +298,6 @@ CONFIG_CODE_PATCHING_SELFTEST=y
|
|||
CONFIG_FTR_FIXUP_SELFTEST=y
|
||||
CONFIG_MSI_BITMAP_SELFTEST=y
|
||||
CONFIG_XMON=y
|
||||
CONFIG_XMON_DEFAULT=y
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
|
|
|
|||
|
|
@ -1,319 +0,0 @@
|
|||
CONFIG_PPC64=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2048
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_AUDITSYSCALL=y
|
||||
CONFIG_IRQ_DOMAIN_DEBUG=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_TASKSTATS=y
|
||||
CONFIG_TASK_DELAY_ACCT=y
|
||||
CONFIG_TASK_XACCT=y
|
||||
CONFIG_TASK_IO_ACCOUNTING=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_NUMA_BALANCING=y
|
||||
CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CPUSETS=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_MEMCG=y
|
||||
CONFIG_MEMCG_SWAP=y
|
||||
CONFIG_CGROUP_PERF=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_MODULE_SRCVERSION_ALL=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_PPC_SPLPAR=y
|
||||
CONFIG_SCANLOG=m
|
||||
CONFIG_PPC_SMLPAR=y
|
||||
CONFIG_DTL=y
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_RTAS_FLASH=m
|
||||
CONFIG_IBMEBUS=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
CONFIG_HZ_100=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_PPC_TRANSACTIONAL_MEM=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_IRQ_ALL_CPUS=y
|
||||
CONFIG_MEMORY_HOTPLUG=y
|
||||
CONFIG_MEMORY_HOTREMOVE=y
|
||||
CONFIG_KSM=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_PPC_64K_PAGES=y
|
||||
CONFIG_PPC_SUBPAGE_PROT=y
|
||||
CONFIG_SCHED_SMT=y
|
||||
CONFIG_HOTPLUG_PCI=y
|
||||
CONFIG_HOTPLUG_PCI_RPA=m
|
||||
CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=m
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_NET_IPIP=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_NETFILTER_ADVANCED is not set
|
||||
CONFIG_BRIDGE=m
|
||||
CONFIG_VLAN_8021Q=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_PARPORT=m
|
||||
CONFIG_PARPORT_PC=m
|
||||
CONFIG_BLK_DEV_FD=m
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
||||
CONFIG_VIRTIO_BLK=m
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDECD=y
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
CONFIG_BLK_DEV_AMD74XX=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_ST=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_BLK_DEV_SR_VENDOR=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_FC_ATTRS=y
|
||||
CONFIG_SCSI_CXGB3_ISCSI=m
|
||||
CONFIG_SCSI_CXGB4_ISCSI=m
|
||||
CONFIG_SCSI_BNX2_ISCSI=m
|
||||
CONFIG_BE2ISCSI=m
|
||||
CONFIG_SCSI_MPT2SAS=m
|
||||
CONFIG_SCSI_IBMVSCSI=y
|
||||
CONFIG_SCSI_IBMVFC=m
|
||||
CONFIG_SCSI_SYM53C8XX_2=y
|
||||
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
|
||||
CONFIG_SCSI_IPR=y
|
||||
CONFIG_SCSI_QLA_FC=m
|
||||
CONFIG_SCSI_QLA_ISCSI=m
|
||||
CONFIG_SCSI_LPFC=m
|
||||
CONFIG_SCSI_VIRTIO=m
|
||||
CONFIG_SCSI_DH=m
|
||||
CONFIG_SCSI_DH_RDAC=m
|
||||
CONFIG_SCSI_DH_ALUA=m
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
# CONFIG_ATA_SFF is not set
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_MD=y
|
||||
CONFIG_MD_LINEAR=y
|
||||
CONFIG_MD_RAID0=y
|
||||
CONFIG_MD_RAID1=y
|
||||
CONFIG_MD_RAID10=m
|
||||
CONFIG_MD_RAID456=m
|
||||
CONFIG_MD_MULTIPATH=m
|
||||
CONFIG_MD_FAULTY=m
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=m
|
||||
CONFIG_DM_SNAPSHOT=m
|
||||
CONFIG_DM_THIN_PROVISIONING=m
|
||||
CONFIG_DM_MIRROR=m
|
||||
CONFIG_DM_ZERO=m
|
||||
CONFIG_DM_MULTIPATH=m
|
||||
CONFIG_DM_MULTIPATH_QL=m
|
||||
CONFIG_DM_MULTIPATH_ST=m
|
||||
CONFIG_DM_UEVENT=y
|
||||
CONFIG_BONDING=m
|
||||
CONFIG_DUMMY=m
|
||||
CONFIG_MACVLAN=m
|
||||
CONFIG_MACVTAP=m
|
||||
CONFIG_VXLAN=m
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_TUN=m
|
||||
CONFIG_VETH=m
|
||||
CONFIG_VIRTIO_NET=m
|
||||
CONFIG_VHOST_NET=m
|
||||
CONFIG_VORTEX=y
|
||||
CONFIG_ACENIC=m
|
||||
CONFIG_ACENIC_OMIT_TIGON_I=y
|
||||
CONFIG_PCNET32=y
|
||||
CONFIG_TIGON3=y
|
||||
CONFIG_CHELSIO_T1=m
|
||||
CONFIG_BE2NET=m
|
||||
CONFIG_S2IO=m
|
||||
CONFIG_IBMVETH=y
|
||||
CONFIG_EHEA=y
|
||||
CONFIG_E100=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_E1000E=y
|
||||
CONFIG_IXGB=m
|
||||
CONFIG_IXGBE=m
|
||||
CONFIG_MLX4_EN=m
|
||||
CONFIG_MYRI10GE=m
|
||||
CONFIG_QLGE=m
|
||||
CONFIG_NETXEN_NIC=m
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_BSDCOMP=m
|
||||
CONFIG_PPP_DEFLATE=m
|
||||
CONFIG_PPPOE=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_PPP_SYNC_TTY=m
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_EVDEV=m
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_PCSPKR=m
|
||||
# CONFIG_SERIO_SERPORT is not set
|
||||
CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_ICOM=m
|
||||
CONFIG_SERIAL_JSM=m
|
||||
CONFIG_HVC_CONSOLE=y
|
||||
CONFIG_HVC_RTAS=y
|
||||
CONFIG_HVCS=m
|
||||
CONFIG_VIRTIO_CONSOLE=m
|
||||
CONFIG_IBM_BSR=m
|
||||
CONFIG_GEN_RTC=y
|
||||
CONFIG_RAW_DRIVER=y
|
||||
CONFIG_MAX_RAW_DEVS=1024
|
||||
CONFIG_FB=y
|
||||
CONFIG_FIRMWARE_EDID=y
|
||||
CONFIG_FB_OF=y
|
||||
CONFIG_FB_MATROX=y
|
||||
CONFIG_FB_MATROX_MILLENIUM=y
|
||||
CONFIG_FB_MATROX_MYSTIQUE=y
|
||||
CONFIG_FB_MATROX_G=y
|
||||
CONFIG_FB_RADEON=y
|
||||
CONFIG_FB_IBM_GXT4500=y
|
||||
CONFIG_LCD_PLATFORM=m
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_LOGO=y
|
||||
CONFIG_HID_GYRATION=y
|
||||
CONFIG_HID_PANTHERLORD=y
|
||||
CONFIG_HID_PETALYNX=y
|
||||
CONFIG_HID_SAMSUNG=y
|
||||
CONFIG_HID_SUNPLUS=y
|
||||
CONFIG_USB_HIDDEV=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=m
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=m
|
||||
CONFIG_INFINIBAND=m
|
||||
CONFIG_INFINIBAND_USER_MAD=m
|
||||
CONFIG_INFINIBAND_USER_ACCESS=m
|
||||
CONFIG_INFINIBAND_MTHCA=m
|
||||
CONFIG_INFINIBAND_EHCA=m
|
||||
CONFIG_INFINIBAND_CXGB3=m
|
||||
CONFIG_INFINIBAND_CXGB4=m
|
||||
CONFIG_MLX4_INFINIBAND=m
|
||||
CONFIG_INFINIBAND_IPOIB=m
|
||||
CONFIG_INFINIBAND_IPOIB_CM=y
|
||||
CONFIG_INFINIBAND_SRP=m
|
||||
CONFIG_INFINIBAND_ISER=m
|
||||
CONFIG_VIRTIO_PCI=m
|
||||
CONFIG_VIRTIO_BALLOON=m
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT2_FS_SECURITY=y
|
||||
CONFIG_EXT2_FS_XIP=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS_SECURITY=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
CONFIG_REISERFS_FS=y
|
||||
CONFIG_REISERFS_FS_XATTR=y
|
||||
CONFIG_REISERFS_FS_POSIX_ACL=y
|
||||
CONFIG_REISERFS_FS_SECURITY=y
|
||||
CONFIG_JFS_FS=m
|
||||
CONFIG_JFS_POSIX_ACL=y
|
||||
CONFIG_JFS_SECURITY=y
|
||||
CONFIG_XFS_FS=m
|
||||
CONFIG_XFS_POSIX_ACL=y
|
||||
CONFIG_BTRFS_FS=m
|
||||
CONFIG_BTRFS_FS_POSIX_ACL=y
|
||||
CONFIG_NILFS2_FS=m
|
||||
CONFIG_AUTOFS4_FS=m
|
||||
CONFIG_FUSE_FS=m
|
||||
CONFIG_OVERLAY_FS=m
|
||||
CONFIG_ISO9660_FS=y
|
||||
CONFIG_UDF_FS=m
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_CRAMFS=m
|
||||
CONFIG_SQUASHFS=m
|
||||
CONFIG_SQUASHFS_XATTR=y
|
||||
CONFIG_SQUASHFS_LZO=y
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_PSTORE=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_NFSD=m
|
||||
CONFIG_NFSD_V3_ACL=y
|
||||
CONFIG_NFSD_V4=y
|
||||
CONFIG_CIFS=m
|
||||
CONFIG_CIFS_XATTR=y
|
||||
CONFIG_CIFS_POSIX=y
|
||||
CONFIG_NLS_DEFAULT="utf8"
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_UTF8=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_STACK_USAGE=y
|
||||
CONFIG_DEBUG_STACKOVERFLOW=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
CONFIG_LATENCYTOP=y
|
||||
CONFIG_SCHED_TRACER=y
|
||||
CONFIG_BLK_DEV_IO_TRACE=y
|
||||
CONFIG_CODE_PATCHING_SELFTEST=y
|
||||
CONFIG_FTR_FIXUP_SELFTEST=y
|
||||
CONFIG_MSI_BITMAP_SELFTEST=y
|
||||
CONFIG_XMON=y
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=m
|
||||
CONFIG_CRYPTO_TGR192=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
CONFIG_CRYPTO_SALSA20=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_TEA=m
|
||||
CONFIG_CRYPTO_TWOFISH=m
|
||||
CONFIG_CRYPTO_LZO=m
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_KVM_BOOK3S_64=m
|
||||
CONFIG_KVM_BOOK3S_64_HV=m
|
||||
|
|
@ -242,11 +242,13 @@ enum {
|
|||
|
||||
/* We only set the TM feature if the kernel was compiled with TM supprt */
|
||||
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||||
#define CPU_FTR_TM_COMP CPU_FTR_TM
|
||||
#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
|
||||
#define CPU_FTR_TM_COMP CPU_FTR_TM
|
||||
#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
|
||||
#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
|
||||
#else
|
||||
#define CPU_FTR_TM_COMP 0
|
||||
#define PPC_FEATURE2_HTM_COMP 0
|
||||
#define CPU_FTR_TM_COMP 0
|
||||
#define PPC_FEATURE2_HTM_COMP 0
|
||||
#define PPC_FEATURE2_HTM_NOSC_COMP 0
|
||||
#endif
|
||||
|
||||
/* We need to mark all pages as being coherent if we're SMP or we have a
|
||||
|
|
@ -366,7 +368,7 @@ enum {
|
|||
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
|
||||
CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
|
||||
#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
|
||||
#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
|
||||
#define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
|
||||
#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
|
||||
#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
|
||||
#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
|
||||
|
|
|
|||
|
|
@ -31,9 +31,9 @@ extern cpumask_t threads_core_mask;
|
|||
/* cpu_thread_mask_to_cores - Return a cpumask of one per cores
|
||||
* hit by the argument
|
||||
*
|
||||
* @threads: a cpumask of threads
|
||||
* @threads: a cpumask of online threads
|
||||
*
|
||||
* This function returns a cpumask which will have one "cpu" (or thread)
|
||||
* This function returns a cpumask which will have one online cpu's
|
||||
* bit set for each core that has at least one thread set in the argument.
|
||||
*
|
||||
* This can typically be used for things like IPI for tlb invalidations
|
||||
|
|
@ -42,13 +42,16 @@ extern cpumask_t threads_core_mask;
|
|||
static inline cpumask_t cpu_thread_mask_to_cores(const struct cpumask *threads)
|
||||
{
|
||||
cpumask_t tmp, res;
|
||||
int i;
|
||||
int i, cpu;
|
||||
|
||||
cpumask_clear(&res);
|
||||
for (i = 0; i < NR_CPUS; i += threads_per_core) {
|
||||
cpumask_shift_left(&tmp, &threads_core_mask, i);
|
||||
if (cpumask_intersects(threads, &tmp))
|
||||
cpumask_set_cpu(i, &res);
|
||||
if (cpumask_intersects(threads, &tmp)) {
|
||||
cpu = cpumask_next_and(-1, &tmp, cpu_online_mask);
|
||||
if (cpu < nr_cpu_ids)
|
||||
cpumask_set_cpu(cpu, &res);
|
||||
}
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -46,6 +46,9 @@ struct dev_archdata {
|
|||
#ifdef CONFIG_FAIL_IOMMU
|
||||
int fail_iommu;
|
||||
#endif
|
||||
#ifdef CONFIG_CXL_BASE
|
||||
struct cxl_context *cxl_ctx;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct pdev_archdata {
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@
|
|||
#include <linux/time.h>
|
||||
#include <linux/atomic.h>
|
||||
|
||||
#include <uapi/asm/eeh.h>
|
||||
|
||||
struct pci_dev;
|
||||
struct pci_bus;
|
||||
struct pci_dn;
|
||||
|
|
@ -185,11 +187,6 @@ enum {
|
|||
#define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
|
||||
#define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
|
||||
#define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
|
||||
#define EEH_PE_STATE_NORMAL 0 /* Normal state */
|
||||
#define EEH_PE_STATE_RESET 1 /* PE reset asserted */
|
||||
#define EEH_PE_STATE_STOPPED_IO_DMA 2 /* Frozen PE */
|
||||
#define EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA, Enabled IO */
|
||||
#define EEH_PE_STATE_UNAVAIL 5 /* Unavailable */
|
||||
#define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
|
||||
#define EEH_RESET_HOT 1 /* Hot reset */
|
||||
#define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
|
||||
|
|
@ -294,6 +291,8 @@ int eeh_pe_set_option(struct eeh_pe *pe, int option);
|
|||
int eeh_pe_get_state(struct eeh_pe *pe);
|
||||
int eeh_pe_reset(struct eeh_pe *pe, int option);
|
||||
int eeh_pe_configure(struct eeh_pe *pe);
|
||||
int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
|
||||
unsigned long addr, unsigned long mask);
|
||||
|
||||
/**
|
||||
* EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
|
||||
|
|
|
|||
|
|
@ -44,6 +44,39 @@
|
|||
extern int iommu_is_off;
|
||||
extern int iommu_force_on;
|
||||
|
||||
struct iommu_table_ops {
|
||||
/*
|
||||
* When called with direction==DMA_NONE, it is equal to clear().
|
||||
* uaddr is a linear map address.
|
||||
*/
|
||||
int (*set)(struct iommu_table *tbl,
|
||||
long index, long npages,
|
||||
unsigned long uaddr,
|
||||
enum dma_data_direction direction,
|
||||
struct dma_attrs *attrs);
|
||||
#ifdef CONFIG_IOMMU_API
|
||||
/*
|
||||
* Exchanges existing TCE with new TCE plus direction bits;
|
||||
* returns old TCE and DMA direction mask.
|
||||
* @tce is a physical address.
|
||||
*/
|
||||
int (*exchange)(struct iommu_table *tbl,
|
||||
long index,
|
||||
unsigned long *hpa,
|
||||
enum dma_data_direction *direction);
|
||||
#endif
|
||||
void (*clear)(struct iommu_table *tbl,
|
||||
long index, long npages);
|
||||
/* get() returns a physical address */
|
||||
unsigned long (*get)(struct iommu_table *tbl, long index);
|
||||
void (*flush)(struct iommu_table *tbl);
|
||||
void (*free)(struct iommu_table *tbl);
|
||||
};
|
||||
|
||||
/* These are used by VIO */
|
||||
extern struct iommu_table_ops iommu_table_lpar_multi_ops;
|
||||
extern struct iommu_table_ops iommu_table_pseries_ops;
|
||||
|
||||
/*
|
||||
* IOMAP_MAX_ORDER defines the largest contiguous block
|
||||
* of dma space we can get. IOMAP_MAX_ORDER = 13
|
||||
|
|
@ -64,6 +97,9 @@ struct iommu_pool {
|
|||
struct iommu_table {
|
||||
unsigned long it_busno; /* Bus number this table belongs to */
|
||||
unsigned long it_size; /* Size of iommu table in entries */
|
||||
unsigned long it_indirect_levels;
|
||||
unsigned long it_level_size;
|
||||
unsigned long it_allocated_size;
|
||||
unsigned long it_offset; /* Offset into global table */
|
||||
unsigned long it_base; /* mapped address of tce table */
|
||||
unsigned long it_index; /* which iommu table this is */
|
||||
|
|
@ -75,15 +111,16 @@ struct iommu_table {
|
|||
struct iommu_pool pools[IOMMU_NR_POOLS];
|
||||
unsigned long *it_map; /* A simple allocation bitmap for now */
|
||||
unsigned long it_page_shift;/* table iommu page size */
|
||||
#ifdef CONFIG_IOMMU_API
|
||||
struct iommu_group *it_group;
|
||||
#endif
|
||||
void (*set_bypass)(struct iommu_table *tbl, bool enable);
|
||||
#ifdef CONFIG_PPC_POWERNV
|
||||
void *data;
|
||||
#endif
|
||||
struct list_head it_group_list;/* List of iommu_table_group_link */
|
||||
unsigned long *it_userspace; /* userspace view of the table */
|
||||
struct iommu_table_ops *it_ops;
|
||||
};
|
||||
|
||||
#define IOMMU_TABLE_USERSPACE_ENTRY(tbl, entry) \
|
||||
((tbl)->it_userspace ? \
|
||||
&((tbl)->it_userspace[(entry) - (tbl)->it_offset]) : \
|
||||
NULL)
|
||||
|
||||
/* Pure 2^n version of get_order */
|
||||
static inline __attribute_const__
|
||||
int get_iommu_order(unsigned long size, struct iommu_table *tbl)
|
||||
|
|
@ -112,14 +149,62 @@ extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
|
|||
*/
|
||||
extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
|
||||
int nid);
|
||||
#define IOMMU_TABLE_GROUP_MAX_TABLES 2
|
||||
|
||||
struct iommu_table_group;
|
||||
|
||||
struct iommu_table_group_ops {
|
||||
unsigned long (*get_table_size)(
|
||||
__u32 page_shift,
|
||||
__u64 window_size,
|
||||
__u32 levels);
|
||||
long (*create_table)(struct iommu_table_group *table_group,
|
||||
int num,
|
||||
__u32 page_shift,
|
||||
__u64 window_size,
|
||||
__u32 levels,
|
||||
struct iommu_table **ptbl);
|
||||
long (*set_window)(struct iommu_table_group *table_group,
|
||||
int num,
|
||||
struct iommu_table *tblnew);
|
||||
long (*unset_window)(struct iommu_table_group *table_group,
|
||||
int num);
|
||||
/* Switch ownership from platform code to external user (e.g. VFIO) */
|
||||
void (*take_ownership)(struct iommu_table_group *table_group);
|
||||
/* Switch ownership from external user (e.g. VFIO) back to core */
|
||||
void (*release_ownership)(struct iommu_table_group *table_group);
|
||||
};
|
||||
|
||||
struct iommu_table_group_link {
|
||||
struct list_head next;
|
||||
struct rcu_head rcu;
|
||||
struct iommu_table_group *table_group;
|
||||
};
|
||||
|
||||
struct iommu_table_group {
|
||||
/* IOMMU properties */
|
||||
__u32 tce32_start;
|
||||
__u32 tce32_size;
|
||||
__u64 pgsizes; /* Bitmap of supported page sizes */
|
||||
__u32 max_dynamic_windows_supported;
|
||||
__u32 max_levels;
|
||||
|
||||
struct iommu_group *group;
|
||||
struct iommu_table *tables[IOMMU_TABLE_GROUP_MAX_TABLES];
|
||||
struct iommu_table_group_ops *ops;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_IOMMU_API
|
||||
extern void iommu_register_group(struct iommu_table *tbl,
|
||||
|
||||
extern void iommu_register_group(struct iommu_table_group *table_group,
|
||||
int pci_domain_number, unsigned long pe_num);
|
||||
extern int iommu_add_device(struct device *dev);
|
||||
extern void iommu_del_device(struct device *dev);
|
||||
extern int __init tce_iommu_bus_notifier_init(void);
|
||||
extern long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry,
|
||||
unsigned long *hpa, enum dma_data_direction *direction);
|
||||
#else
|
||||
static inline void iommu_register_group(struct iommu_table *tbl,
|
||||
static inline void iommu_register_group(struct iommu_table_group *table_group,
|
||||
int pci_domain_number,
|
||||
unsigned long pe_num)
|
||||
{
|
||||
|
|
@ -140,13 +225,6 @@ static inline int __init tce_iommu_bus_notifier_init(void)
|
|||
}
|
||||
#endif /* !CONFIG_IOMMU_API */
|
||||
|
||||
static inline void set_iommu_table_base_and_group(struct device *dev,
|
||||
void *base)
|
||||
{
|
||||
set_iommu_table_base(dev, base);
|
||||
iommu_add_device(dev);
|
||||
}
|
||||
|
||||
extern int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
|
||||
struct scatterlist *sglist, int nelems,
|
||||
unsigned long mask,
|
||||
|
|
@ -197,20 +275,13 @@ extern int iommu_tce_clear_param_check(struct iommu_table *tbl,
|
|||
unsigned long npages);
|
||||
extern int iommu_tce_put_param_check(struct iommu_table *tbl,
|
||||
unsigned long ioba, unsigned long tce);
|
||||
extern int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,
|
||||
unsigned long hwaddr, enum dma_data_direction direction);
|
||||
extern unsigned long iommu_clear_tce(struct iommu_table *tbl,
|
||||
unsigned long entry);
|
||||
extern int iommu_clear_tces_and_put_pages(struct iommu_table *tbl,
|
||||
unsigned long entry, unsigned long pages);
|
||||
extern int iommu_put_tce_user_mode(struct iommu_table *tbl,
|
||||
unsigned long entry, unsigned long tce);
|
||||
|
||||
extern void iommu_flush_tce(struct iommu_table *tbl);
|
||||
extern int iommu_take_ownership(struct iommu_table *tbl);
|
||||
extern void iommu_release_ownership(struct iommu_table *tbl);
|
||||
|
||||
extern enum dma_data_direction iommu_tce_direction(unsigned long tce);
|
||||
extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_IOMMU_H */
|
||||
|
|
|
|||
|
|
@ -65,31 +65,6 @@ struct machdep_calls {
|
|||
* destroyed as well */
|
||||
void (*hpte_clear_all)(void);
|
||||
|
||||
int (*tce_build)(struct iommu_table *tbl,
|
||||
long index,
|
||||
long npages,
|
||||
unsigned long uaddr,
|
||||
enum dma_data_direction direction,
|
||||
struct dma_attrs *attrs);
|
||||
void (*tce_free)(struct iommu_table *tbl,
|
||||
long index,
|
||||
long npages);
|
||||
unsigned long (*tce_get)(struct iommu_table *tbl,
|
||||
long index);
|
||||
void (*tce_flush)(struct iommu_table *tbl);
|
||||
|
||||
/* _rm versions are for real mode use only */
|
||||
int (*tce_build_rm)(struct iommu_table *tbl,
|
||||
long index,
|
||||
long npages,
|
||||
unsigned long uaddr,
|
||||
enum dma_data_direction direction,
|
||||
struct dma_attrs *attrs);
|
||||
void (*tce_free_rm)(struct iommu_table *tbl,
|
||||
long index,
|
||||
long npages);
|
||||
void (*tce_flush_rm)(struct iommu_table *tbl);
|
||||
|
||||
void __iomem * (*ioremap)(phys_addr_t addr, unsigned long size,
|
||||
unsigned long flags, void *caller);
|
||||
void (*iounmap)(volatile void __iomem *token);
|
||||
|
|
@ -131,12 +106,6 @@ struct machdep_calls {
|
|||
/* To setup PHBs when using automatic OF platform driver for PCI */
|
||||
int (*pci_setup_phb)(struct pci_controller *host);
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
int (*setup_msi_irqs)(struct pci_dev *dev,
|
||||
int nvec, int type);
|
||||
void (*teardown_msi_irqs)(struct pci_dev *dev);
|
||||
#endif
|
||||
|
||||
void (*restart)(char *cmd);
|
||||
void (*halt)(void);
|
||||
void (*panic)(char *str);
|
||||
|
|
|
|||
|
|
@ -27,6 +27,19 @@
|
|||
#define MI_Ks 0x80000000 /* Should not be set */
|
||||
#define MI_Kp 0x40000000 /* Should always be set */
|
||||
|
||||
/*
|
||||
* All pages' PP exec bits are set to 000, which means Execute for Supervisor
|
||||
* and no Execute for User.
|
||||
* Then we use the APG to say whether accesses are according to Page rules,
|
||||
* "all Supervisor" rules (Exec for all) and "all User" rules (Exec for noone)
|
||||
* Therefore, we define 4 APG groups. msb is _PAGE_EXEC, lsb is _PAGE_USER
|
||||
* 0 (00) => Not User, no exec => 11 (all accesses performed as user)
|
||||
* 1 (01) => User but no exec => 11 (all accesses performed as user)
|
||||
* 2 (10) => Not User, exec => 01 (rights according to page definition)
|
||||
* 3 (11) => User, exec => 00 (all accesses performed as supervisor)
|
||||
*/
|
||||
#define MI_APG_INIT 0xf4ffffff
|
||||
|
||||
/* The effective page number register. When read, contains the information
|
||||
* about the last instruction TLB miss. When MI_RPN is written, bits in
|
||||
* this register are used to create the TLB entry.
|
||||
|
|
@ -87,6 +100,19 @@
|
|||
#define MD_Ks 0x80000000 /* Should not be set */
|
||||
#define MD_Kp 0x40000000 /* Should always be set */
|
||||
|
||||
/*
|
||||
* All pages' PP data bits are set to either 000 or 011, which means
|
||||
* respectively RW for Supervisor and no access for User, or RO for
|
||||
* Supervisor and no access for user.
|
||||
* Then we use the APG to say whether accesses are according to Page rules or
|
||||
* "all Supervisor" rules (Access to all)
|
||||
* Therefore, we define 2 APG groups. lsb is _PAGE_USER
|
||||
* 0 => No user => 01 (all accesses performed according to page definition)
|
||||
* 1 => User => 00 (all accesses performed as supervisor
|
||||
* according to page definition)
|
||||
*/
|
||||
#define MD_APG_INIT 0x4fffffff
|
||||
|
||||
/* The effective page number register. When read, contains the information
|
||||
* about the last instruction TLB miss. When MD_RPN is written, bits in
|
||||
* this register are used to create the TLB entry.
|
||||
|
|
@ -145,7 +171,14 @@ typedef struct {
|
|||
} mm_context_t;
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#if (PAGE_SHIFT == 12)
|
||||
#define mmu_virtual_psize MMU_PAGE_4K
|
||||
#elif (PAGE_SHIFT == 14)
|
||||
#define mmu_virtual_psize MMU_PAGE_16K
|
||||
#else
|
||||
#error "Unsupported PAGE_SIZE"
|
||||
#endif
|
||||
|
||||
#define mmu_linear_psize MMU_PAGE_8M
|
||||
|
||||
#endif /* _ASM_POWERPC_MMU_8XX_H_ */
|
||||
|
|
|
|||
|
|
@ -536,6 +536,9 @@ typedef struct {
|
|||
/* for 4K PTE fragment support */
|
||||
void *pte_frag;
|
||||
#endif
|
||||
#ifdef CONFIG_SPAPR_TCE_IOMMU
|
||||
struct list_head iommu_group_mem_list;
|
||||
#endif
|
||||
} mm_context_t;
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,24 @@
|
|||
*/
|
||||
extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
|
||||
extern void destroy_context(struct mm_struct *mm);
|
||||
#ifdef CONFIG_SPAPR_TCE_IOMMU
|
||||
struct mm_iommu_table_group_mem_t;
|
||||
|
||||
extern bool mm_iommu_preregistered(void);
|
||||
extern long mm_iommu_get(unsigned long ua, unsigned long entries,
|
||||
struct mm_iommu_table_group_mem_t **pmem);
|
||||
extern long mm_iommu_put(struct mm_iommu_table_group_mem_t *mem);
|
||||
extern void mm_iommu_init(mm_context_t *ctx);
|
||||
extern void mm_iommu_cleanup(mm_context_t *ctx);
|
||||
extern struct mm_iommu_table_group_mem_t *mm_iommu_lookup(unsigned long ua,
|
||||
unsigned long size);
|
||||
extern struct mm_iommu_table_group_mem_t *mm_iommu_find(unsigned long ua,
|
||||
unsigned long entries);
|
||||
extern long mm_iommu_ua_to_hpa(struct mm_iommu_table_group_mem_t *mem,
|
||||
unsigned long ua, unsigned long *hpa);
|
||||
extern long mm_iommu_mapped_inc(struct mm_iommu_table_group_mem_t *mem);
|
||||
extern void mm_iommu_mapped_dec(struct mm_iommu_table_group_mem_t *mem);
|
||||
#endif
|
||||
|
||||
extern void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
|
||||
extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
|
||||
|
|
|
|||
|
|
@ -153,7 +153,8 @@
|
|||
#define OPAL_FLASH_READ 110
|
||||
#define OPAL_FLASH_WRITE 111
|
||||
#define OPAL_FLASH_ERASE 112
|
||||
#define OPAL_LAST 112
|
||||
#define OPAL_PRD_MSG 113
|
||||
#define OPAL_LAST 113
|
||||
|
||||
/* Device tree flags */
|
||||
|
||||
|
|
@ -165,6 +166,13 @@
|
|||
#define OPAL_PM_WINKLE_ENABLED 0x00040000
|
||||
#define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
|
||||
|
||||
/*
|
||||
* OPAL_CONFIG_CPU_IDLE_STATE parameters
|
||||
*/
|
||||
#define OPAL_CONFIG_IDLE_FASTSLEEP 1
|
||||
#define OPAL_CONFIG_IDLE_UNDO 0
|
||||
#define OPAL_CONFIG_IDLE_APPLY 1
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* Other enums */
|
||||
|
|
@ -352,6 +360,7 @@ enum opal_msg_type {
|
|||
OPAL_MSG_SHUTDOWN, /* params[0] = 1 reboot, 0 shutdown */
|
||||
OPAL_MSG_HMI_EVT,
|
||||
OPAL_MSG_DPO,
|
||||
OPAL_MSG_PRD,
|
||||
OPAL_MSG_TYPE_MAX,
|
||||
};
|
||||
|
||||
|
|
@ -674,6 +683,23 @@ typedef struct oppanel_line {
|
|||
__be64 line_len;
|
||||
} oppanel_line_t;
|
||||
|
||||
enum opal_prd_msg_type {
|
||||
OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */
|
||||
OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */
|
||||
OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */
|
||||
OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */
|
||||
OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */
|
||||
OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */
|
||||
};
|
||||
|
||||
struct opal_prd_msg_header {
|
||||
uint8_t type;
|
||||
uint8_t pad[1];
|
||||
__be16 size;
|
||||
};
|
||||
|
||||
struct opal_prd_msg;
|
||||
|
||||
/*
|
||||
* SG entries
|
||||
*
|
||||
|
|
|
|||
|
|
@ -186,6 +186,7 @@ int64_t opal_handle_hmi(void);
|
|||
int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
|
||||
int64_t opal_unregister_dump_region(uint32_t id);
|
||||
int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
|
||||
int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
|
||||
int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
|
||||
int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
|
||||
uint64_t msg_len);
|
||||
|
|
@ -193,6 +194,7 @@ int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
|
|||
uint64_t *msg_len);
|
||||
int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
|
||||
struct opal_i2c_request *oreq);
|
||||
int64_t opal_prd_msg(struct opal_prd_msg *msg);
|
||||
|
||||
int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
|
||||
uint64_t size, uint64_t token);
|
||||
|
|
@ -239,6 +241,10 @@ extern int opal_elog_init(void);
|
|||
extern void opal_platform_dump_init(void);
|
||||
extern void opal_sys_param_init(void);
|
||||
extern void opal_msglog_init(void);
|
||||
extern int opal_async_comp_init(void);
|
||||
extern int opal_sensor_init(void);
|
||||
extern int opal_hmi_handler_init(void);
|
||||
extern int opal_event_init(void);
|
||||
|
||||
extern int opal_machine_check(struct pt_regs *regs);
|
||||
extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
|
||||
|
|
@ -250,6 +256,8 @@ extern int opal_resync_timebase(void);
|
|||
|
||||
extern void opal_lpc_init(void);
|
||||
|
||||
extern int opal_event_request(unsigned int opal_event_nr);
|
||||
|
||||
struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
|
||||
unsigned long vmalloc_size);
|
||||
void opal_free_sg_list(struct opal_sg_list *sg);
|
||||
|
|
|
|||
|
|
@ -278,9 +278,7 @@ extern long long virt_phys_offset;
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef STRICT_MM_TYPECHECKS
|
||||
|
||||
#ifdef STRICT_MM_TYPECHECKS
|
||||
#ifdef CONFIG_STRICT_MM_TYPECHECKS
|
||||
/* These are used to make use of C type-checking. */
|
||||
|
||||
/* PTE level */
|
||||
|
|
|
|||
|
|
@ -27,9 +27,23 @@ struct pci_controller_ops {
|
|||
* allow assignment/enabling of the device. */
|
||||
bool (*enable_device_hook)(struct pci_dev *);
|
||||
|
||||
void (*disable_device)(struct pci_dev *);
|
||||
|
||||
void (*release_device)(struct pci_dev *);
|
||||
|
||||
/* Called during PCI resource reassignment */
|
||||
resource_size_t (*window_alignment)(struct pci_bus *, unsigned long type);
|
||||
void (*reset_secondary_bus)(struct pci_dev *dev);
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
int (*setup_msi_irqs)(struct pci_dev *dev,
|
||||
int nvec, int type);
|
||||
void (*teardown_msi_irqs)(struct pci_dev *dev);
|
||||
#endif
|
||||
|
||||
int (*dma_set_mask)(struct pci_dev *dev, u64 dma_mask);
|
||||
|
||||
void (*shutdown)(struct pci_controller *);
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -185,7 +199,7 @@ struct pci_dn {
|
|||
|
||||
struct pci_dn *parent;
|
||||
struct pci_controller *phb; /* for pci devices */
|
||||
struct iommu_table *iommu_table; /* for phb's or bridges */
|
||||
struct iommu_table_group *table_group; /* for phb's or bridges */
|
||||
struct device_node *node; /* back-pointer to the device_node */
|
||||
|
||||
int pci_ext_config_space; /* for pci devices */
|
||||
|
|
|
|||
|
|
@ -170,24 +170,6 @@ static inline unsigned long pte_update(pte_t *p,
|
|||
#ifdef PTE_ATOMIC_UPDATES
|
||||
unsigned long old, tmp;
|
||||
|
||||
#ifdef CONFIG_PPC_8xx
|
||||
unsigned long tmp2;
|
||||
|
||||
__asm__ __volatile__("\
|
||||
1: lwarx %0,0,%4\n\
|
||||
andc %1,%0,%5\n\
|
||||
or %1,%1,%6\n\
|
||||
/* 0x200 == Extended encoding, bit 22 */ \
|
||||
/* Bit 22 has to be 1 when _PAGE_USER is unset and _PAGE_RO is set */ \
|
||||
rlwimi %1,%1,32-1,0x200\n /* get _PAGE_RO */ \
|
||||
rlwinm %3,%1,32-2,0x200\n /* get _PAGE_USER */ \
|
||||
andc %1,%1,%3\n\
|
||||
stwcx. %1,0,%4\n\
|
||||
bne- 1b"
|
||||
: "=&r" (old), "=&r" (tmp), "=m" (*p), "=&r" (tmp2)
|
||||
: "r" (p), "r" (clr), "r" (set), "m" (*p)
|
||||
: "cc" );
|
||||
#else /* CONFIG_PPC_8xx */
|
||||
__asm__ __volatile__("\
|
||||
1: lwarx %0,0,%3\n\
|
||||
andc %1,%0,%4\n\
|
||||
|
|
@ -198,7 +180,6 @@ static inline unsigned long pte_update(pte_t *p,
|
|||
: "=&r" (old), "=&r" (tmp), "=m" (*p)
|
||||
: "r" (p), "r" (clr), "r" (set), "m" (*p)
|
||||
: "cc" );
|
||||
#endif /* CONFIG_PPC_8xx */
|
||||
#else /* PTE_ATOMIC_UPDATES */
|
||||
unsigned long old = pte_val(*p);
|
||||
*p = __pte((old & ~clr) | set);
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@
|
|||
*/
|
||||
#ifndef __real_pte
|
||||
|
||||
#ifdef STRICT_MM_TYPECHECKS
|
||||
#ifdef CONFIG_STRICT_MM_TYPECHECKS
|
||||
#define __real_pte(e,p) ((real_pte_t){(e)})
|
||||
#define __rpte_to_pte(r) ((r).pte)
|
||||
#else
|
||||
|
|
@ -347,11 +347,27 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
|
|||
pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
|
||||
|
||||
/* Encode and de-code a swap entry */
|
||||
#define __swp_type(entry) (((entry).val >> 1) & 0x3f)
|
||||
#define __swp_offset(entry) ((entry).val >> 8)
|
||||
#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
|
||||
#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
|
||||
#define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT })
|
||||
#define MAX_SWAPFILES_CHECK() do { \
|
||||
BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
|
||||
/* \
|
||||
* Don't have overlapping bits with _PAGE_HPTEFLAGS \
|
||||
* We filter HPTEFLAGS on set_pte. \
|
||||
*/ \
|
||||
BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
|
||||
} while (0)
|
||||
/*
|
||||
* on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
|
||||
*/
|
||||
#define SWP_TYPE_BITS 5
|
||||
#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
|
||||
& ((1UL << SWP_TYPE_BITS) - 1))
|
||||
#define __swp_offset(x) ((x).val >> PTE_RPN_SHIFT)
|
||||
#define __swp_entry(type, offset) ((swp_entry_t) { \
|
||||
((type) << _PAGE_BIT_SWAP_TYPE) \
|
||||
| ((offset) << PTE_RPN_SHIFT) })
|
||||
|
||||
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) })
|
||||
#define __swp_entry_to_pte(x) __pte((x).val)
|
||||
|
||||
void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
|
||||
void pgtable_cache_init(void);
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#define _ASM_PNV_PCI_H
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <misc/cxl.h>
|
||||
#include <misc/cxl-base.h>
|
||||
|
||||
int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode);
|
||||
int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
|
||||
|
|
|
|||
|
|
@ -295,6 +295,15 @@ struct thread_struct {
|
|||
#endif
|
||||
#ifdef CONFIG_PPC64
|
||||
unsigned long dscr;
|
||||
/*
|
||||
* This member element dscr_inherit indicates that the process
|
||||
* has explicitly attempted and changed the DSCR register value
|
||||
* for itself. Hence kernel wont use the default CPU DSCR value
|
||||
* contained in the PACA structure anymore during process context
|
||||
* switch. Once this variable is set, this behaviour will also be
|
||||
* inherited to all the children of this process from that point
|
||||
* onwards.
|
||||
*/
|
||||
int dscr_inherit;
|
||||
unsigned long ppr; /* used to save/restore SMT priority */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -34,35 +34,32 @@
|
|||
#define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
|
||||
#define _PAGE_DIRTY 0x0100 /* C: page changed */
|
||||
|
||||
/* These 4 software bits must be masked out when the entry is loaded
|
||||
* into the TLB, 1 SW bit left(0x0080).
|
||||
/* These 4 software bits must be masked out when the L2 entry is loaded
|
||||
* into the TLB.
|
||||
*/
|
||||
#define _PAGE_GUARDED 0x0010 /* software: guarded access */
|
||||
#define _PAGE_ACCESSED 0x0020 /* software: page referenced */
|
||||
#define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */
|
||||
#define _PAGE_GUARDED 0x0010 /* Copied to L1 G entry in DTLB */
|
||||
#define _PAGE_USER 0x0020 /* Copied to L1 APG lsb */
|
||||
#define _PAGE_EXEC 0x0040 /* Copied to L1 APG */
|
||||
#define _PAGE_WRITETHRU 0x0080 /* software: caching is write through */
|
||||
#define _PAGE_ACCESSED 0x0800 /* software: page referenced */
|
||||
|
||||
/* Setting any bits in the nibble with the follow two controls will
|
||||
* require a TLB exception handler change. It is assumed unused bits
|
||||
* are always zero.
|
||||
*/
|
||||
#define _PAGE_RO 0x0400 /* lsb PP bits */
|
||||
#define _PAGE_USER 0x0800 /* msb PP bits */
|
||||
/* set when _PAGE_USER is unset and _PAGE_RO is set */
|
||||
#define _PAGE_KNLRO 0x0200
|
||||
#define _PAGE_RO 0x0600 /* Supervisor RO, User no access */
|
||||
|
||||
#define _PMD_PRESENT 0x0001
|
||||
#define _PMD_BAD 0x0ff0
|
||||
#define _PMD_PAGE_MASK 0x000c
|
||||
#define _PMD_PAGE_8M 0x000c
|
||||
|
||||
#define _PTE_NONE_MASK _PAGE_KNLRO
|
||||
|
||||
/* Until my rework is finished, 8xx still needs atomic PTE updates */
|
||||
#define PTE_ATOMIC_UPDATES 1
|
||||
|
||||
/* We need to add _PAGE_SHARED to kernel pages */
|
||||
#define _PAGE_KERNEL_RO (_PAGE_SHARED | _PAGE_RO | _PAGE_KNLRO)
|
||||
#define _PAGE_KERNEL_ROX (_PAGE_EXEC | _PAGE_RO | _PAGE_KNLRO)
|
||||
#define _PAGE_KERNEL_RO (_PAGE_SHARED | _PAGE_RO)
|
||||
#define _PAGE_KERNEL_ROX (_PAGE_SHARED | _PAGE_RO | _PAGE_EXEC)
|
||||
#define _PAGE_KERNEL_RW (_PAGE_SHARED | _PAGE_DIRTY | _PAGE_RW | \
|
||||
_PAGE_HWWRITE)
|
||||
#define _PAGE_KERNEL_RWX (_PAGE_SHARED | _PAGE_DIRTY | _PAGE_RW | \
|
||||
_PAGE_HWWRITE | _PAGE_EXEC)
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_PTE_8xx_H */
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
/* Architected bits */
|
||||
#define _PAGE_PRESENT 0x000001 /* software: pte contains a translation */
|
||||
#define _PAGE_SW1 0x000002
|
||||
#define _PAGE_BIT_SWAP_TYPE 2
|
||||
#define _PAGE_BAP_SR 0x000004
|
||||
#define _PAGE_BAP_UR 0x000008
|
||||
#define _PAGE_BAP_SW 0x000010
|
||||
|
|
|
|||
|
|
@ -85,10 +85,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
|
|||
* 64-bit PTEs
|
||||
*/
|
||||
#if defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
|
||||
#define PTE_RPN_MAX (1ULL << (64 - PTE_RPN_SHIFT))
|
||||
#define PTE_RPN_MASK (~((1ULL<<PTE_RPN_SHIFT)-1))
|
||||
#else
|
||||
#define PTE_RPN_MAX (1UL << (32 - PTE_RPN_SHIFT))
|
||||
#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
*/
|
||||
#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
|
||||
#define _PAGE_USER 0x0002 /* matches one of the PP bits */
|
||||
#define _PAGE_BIT_SWAP_TYPE 2
|
||||
#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
|
||||
#define _PAGE_GUARDED 0x0008
|
||||
/* We can derive Memory coherence from _PAGE_NO_CACHE */
|
||||
|
|
|
|||
|
|
@ -358,7 +358,7 @@ SYSCALL_SPU(setns)
|
|||
COMPAT_SYS(process_vm_readv)
|
||||
COMPAT_SYS(process_vm_writev)
|
||||
SYSCALL(finit_module)
|
||||
SYSCALL(ni_syscall) /* sys_kcmp */
|
||||
SYSCALL(kcmp) /* sys_kcmp */
|
||||
SYSCALL_SPU(sched_setattr)
|
||||
SYSCALL_SPU(sched_getattr)
|
||||
SYSCALL_SPU(renameat2)
|
||||
|
|
|
|||
|
|
@ -144,6 +144,26 @@ TRACE_EVENT_FN(opal_exit,
|
|||
);
|
||||
#endif
|
||||
|
||||
TRACE_EVENT(hash_fault,
|
||||
|
||||
TP_PROTO(unsigned long addr, unsigned long access, unsigned long trap),
|
||||
TP_ARGS(addr, access, trap),
|
||||
TP_STRUCT__entry(
|
||||
__field(unsigned long, addr)
|
||||
__field(unsigned long, access)
|
||||
__field(unsigned long, trap)
|
||||
),
|
||||
|
||||
TP_fast_assign(
|
||||
__entry->addr = addr;
|
||||
__entry->access = access;
|
||||
__entry->trap = trap;
|
||||
),
|
||||
|
||||
TP_printk("hash fault with addr 0x%lx and access = 0x%lx trap = 0x%lx",
|
||||
__entry->addr, __entry->access, __entry->trap)
|
||||
);
|
||||
|
||||
#endif /* _TRACE_POWERPC_H */
|
||||
|
||||
#undef TRACE_INCLUDE_PATH
|
||||
|
|
|
|||
|
|
@ -265,7 +265,7 @@ do { \
|
|||
({ \
|
||||
long __gu_err; \
|
||||
unsigned long __gu_val; \
|
||||
const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__chk_user_ptr(ptr); \
|
||||
if (!is_kernel_addr((unsigned long)__gu_addr)) \
|
||||
might_fault(); \
|
||||
|
|
@ -279,7 +279,7 @@ do { \
|
|||
({ \
|
||||
long __gu_err; \
|
||||
long long __gu_val; \
|
||||
const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__chk_user_ptr(ptr); \
|
||||
if (!is_kernel_addr((unsigned long)__gu_addr)) \
|
||||
might_fault(); \
|
||||
|
|
@ -293,7 +293,7 @@ do { \
|
|||
({ \
|
||||
long __gu_err = -EFAULT; \
|
||||
unsigned long __gu_val = 0; \
|
||||
const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
might_fault(); \
|
||||
if (access_ok(VERIFY_READ, __gu_addr, (size))) \
|
||||
__get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
|
||||
|
|
@ -305,7 +305,7 @@ do { \
|
|||
({ \
|
||||
long __gu_err; \
|
||||
unsigned long __gu_val; \
|
||||
const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__chk_user_ptr(ptr); \
|
||||
__get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
|
||||
(x) = (__force __typeof__(*(ptr)))__gu_val; \
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ header-y += kvm_para.h
|
|||
header-y += mman.h
|
||||
header-y += msgbuf.h
|
||||
header-y += nvram.h
|
||||
header-y += opal-prd.h
|
||||
header-y += param.h
|
||||
header-y += perf_event.h
|
||||
header-y += poll.h
|
||||
|
|
|
|||
|
|
@ -42,5 +42,6 @@
|
|||
#define PPC_FEATURE2_ISEL 0x08000000
|
||||
#define PPC_FEATURE2_TAR 0x04000000
|
||||
#define PPC_FEATURE2_VEC_CRYPTO 0x02000000
|
||||
#define PPC_FEATURE2_HTM_NOSC 0x01000000
|
||||
|
||||
#endif /* _UAPI__ASM_POWERPC_CPUTABLE_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*
|
||||
* Copyright IBM Corp. 2015
|
||||
*
|
||||
* Authors: Gavin Shan <gwshan@linux.vnet.ibm.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_POWERPC_EEH_H
|
||||
#define _ASM_POWERPC_EEH_H
|
||||
|
||||
/* PE states */
|
||||
#define EEH_PE_STATE_NORMAL 0 /* Normal state */
|
||||
#define EEH_PE_STATE_RESET 1 /* PE reset asserted */
|
||||
#define EEH_PE_STATE_STOPPED_IO_DMA 2 /* Frozen PE */
|
||||
#define EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA only */
|
||||
#define EEH_PE_STATE_UNAVAIL 5 /* Unavailable */
|
||||
|
||||
/* EEH error types and functions */
|
||||
#define EEH_ERR_TYPE_32 0 /* 32-bits error */
|
||||
#define EEH_ERR_TYPE_64 1 /* 64-bits error */
|
||||
#define EEH_ERR_FUNC_MIN 0
|
||||
#define EEH_ERR_FUNC_LD_MEM_ADDR 0 /* Memory load */
|
||||
#define EEH_ERR_FUNC_LD_MEM_DATA 1
|
||||
#define EEH_ERR_FUNC_LD_IO_ADDR 2 /* IO load */
|
||||
#define EEH_ERR_FUNC_LD_IO_DATA 3
|
||||
#define EEH_ERR_FUNC_LD_CFG_ADDR 4 /* Config load */
|
||||
#define EEH_ERR_FUNC_LD_CFG_DATA 5
|
||||
#define EEH_ERR_FUNC_ST_MEM_ADDR 6 /* Memory store */
|
||||
#define EEH_ERR_FUNC_ST_MEM_DATA 7
|
||||
#define EEH_ERR_FUNC_ST_IO_ADDR 8 /* IO store */
|
||||
#define EEH_ERR_FUNC_ST_IO_DATA 9
|
||||
#define EEH_ERR_FUNC_ST_CFG_ADDR 10 /* Config store */
|
||||
#define EEH_ERR_FUNC_ST_CFG_DATA 11
|
||||
#define EEH_ERR_FUNC_DMA_RD_ADDR 12 /* DMA read */
|
||||
#define EEH_ERR_FUNC_DMA_RD_DATA 13
|
||||
#define EEH_ERR_FUNC_DMA_RD_MASTER 14
|
||||
#define EEH_ERR_FUNC_DMA_RD_TARGET 15
|
||||
#define EEH_ERR_FUNC_DMA_WR_ADDR 16 /* DMA write */
|
||||
#define EEH_ERR_FUNC_DMA_WR_DATA 17
|
||||
#define EEH_ERR_FUNC_DMA_WR_MASTER 18
|
||||
#define EEH_ERR_FUNC_DMA_WR_TARGET 19
|
||||
#define EEH_ERR_FUNC_MAX 19
|
||||
|
||||
#endif /* _ASM_POWERPC_EEH_H */
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* OPAL Runtime Diagnostics interface driver
|
||||
* Supported on POWERNV platform
|
||||
*
|
||||
* (C) Copyright IBM 2015
|
||||
*
|
||||
* Author: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>
|
||||
* Author: Jeremy Kerr <jk@ozlabs.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _UAPI_ASM_POWERPC_OPAL_PRD_H_
|
||||
#define _UAPI_ASM_POWERPC_OPAL_PRD_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/**
|
||||
* The version of the kernel interface of the PRD system. This describes the
|
||||
* interface available for the /dev/opal-prd device. The actual PRD message
|
||||
* layout and content is private to the firmware <--> userspace interface, so
|
||||
* is not covered by this versioning.
|
||||
*
|
||||
* Future interface versions are backwards-compatible; if a later kernel
|
||||
* version is encountered, functionality provided in earlier versions
|
||||
* will work.
|
||||
*/
|
||||
#define OPAL_PRD_KERNEL_VERSION 1
|
||||
|
||||
#define OPAL_PRD_GET_INFO _IOR('o', 0x01, struct opal_prd_info)
|
||||
#define OPAL_PRD_SCOM_READ _IOR('o', 0x02, struct opal_prd_scom)
|
||||
#define OPAL_PRD_SCOM_WRITE _IOW('o', 0x03, struct opal_prd_scom)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct opal_prd_info {
|
||||
__u64 version;
|
||||
__u64 reserved[3];
|
||||
};
|
||||
|
||||
struct opal_prd_scom {
|
||||
__u64 chip;
|
||||
__u64 addr;
|
||||
__u64 data;
|
||||
__s64 rc;
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _UAPI_ASM_POWERPC_OPAL_PRD_H */
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
#define TM_CAUSE_RESCHED 0xde
|
||||
#define TM_CAUSE_TLBI 0xdc
|
||||
#define TM_CAUSE_FAC_UNAV 0xda
|
||||
#define TM_CAUSE_SYSCALL 0xd8 /* future use */
|
||||
#define TM_CAUSE_SYSCALL 0xd8
|
||||
#define TM_CAUSE_MISC 0xd6 /* future use */
|
||||
#define TM_CAUSE_SIGNAL 0xd4
|
||||
#define TM_CAUSE_ALIGNMENT 0xd2
|
||||
|
|
|
|||
|
|
@ -33,11 +33,12 @@ obj-y := cputable.o ptrace.o syscalls.o \
|
|||
signal.o sysfs.o cacheinfo.o time.o \
|
||||
prom.o traps.o setup-common.o \
|
||||
udbg.o misc.o io.o dma.o \
|
||||
misc_$(CONFIG_WORD_SIZE).o vdso32/ \
|
||||
misc_$(CONFIG_WORD_SIZE).o \
|
||||
of_platform.o prom_parse.o
|
||||
obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
|
||||
signal_64.o ptrace32.o \
|
||||
paca.o nvram_64.o firmware.o
|
||||
obj-$(CONFIG_VDSO32) += vdso32/
|
||||
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
|
||||
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
|
||||
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o
|
||||
|
|
|
|||
|
|
@ -247,7 +247,7 @@ int main(void)
|
|||
#endif
|
||||
DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
|
||||
DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state));
|
||||
DEFINE(PACA_DSCR, offsetof(struct paca_struct, dscr_default));
|
||||
DEFINE(PACA_DSCR_DEFAULT, offsetof(struct paca_struct, dscr_default));
|
||||
DEFINE(PACA_STARTTIME, offsetof(struct paca_struct, starttime));
|
||||
DEFINE(PACA_STARTTIME_USER, offsetof(struct paca_struct, starttime_user));
|
||||
DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
|
||||
|
|
|
|||
|
|
@ -108,7 +108,9 @@ extern void __restore_cpu_e6500(void);
|
|||
PPC_FEATURE_TRUE_LE | \
|
||||
PPC_FEATURE_PSERIES_PERFMON_COMPAT)
|
||||
#define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \
|
||||
PPC_FEATURE2_HTM_COMP | PPC_FEATURE2_DSCR | \
|
||||
PPC_FEATURE2_HTM_COMP | \
|
||||
PPC_FEATURE2_HTM_NOSC_COMP | \
|
||||
PPC_FEATURE2_DSCR | \
|
||||
PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \
|
||||
PPC_FEATURE2_VEC_CRYPTO)
|
||||
#define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
|
||||
|
|
|
|||
|
|
@ -248,6 +248,14 @@ int dma_set_mask(struct device *dev, u64 dma_mask)
|
|||
{
|
||||
if (ppc_md.dma_set_mask)
|
||||
return ppc_md.dma_set_mask(dev, dma_mask);
|
||||
|
||||
if (dev_is_pci(dev)) {
|
||||
struct pci_dev *pdev = to_pci_dev(dev);
|
||||
struct pci_controller *phb = pci_bus_to_host(pdev->bus);
|
||||
if (phb->controller_ops.dma_set_mask)
|
||||
return phb->controller_ops.dma_set_mask(pdev, dma_mask);
|
||||
}
|
||||
|
||||
return __dma_set_mask(dev, dma_mask);
|
||||
}
|
||||
EXPORT_SYMBOL(dma_set_mask);
|
||||
|
|
|
|||
|
|
@ -144,8 +144,6 @@ struct eeh_stats {
|
|||
|
||||
static struct eeh_stats eeh_stats;
|
||||
|
||||
#define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE)
|
||||
|
||||
static int __init eeh_setup(char *str)
|
||||
{
|
||||
if (!strcmp(str, "off"))
|
||||
|
|
@ -719,7 +717,7 @@ static void *eeh_restore_dev_state(void *data, void *userdata)
|
|||
|
||||
/* The caller should restore state for the specified device */
|
||||
if (pdev != dev)
|
||||
pci_save_state(pdev);
|
||||
pci_restore_state(pdev);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
|
@ -1412,13 +1410,11 @@ static int dev_has_iommu_table(struct device *dev, void *data)
|
|||
{
|
||||
struct pci_dev *pdev = to_pci_dev(dev);
|
||||
struct pci_dev **ppdev = data;
|
||||
struct iommu_table *tbl;
|
||||
|
||||
if (!dev)
|
||||
return 0;
|
||||
|
||||
tbl = get_iommu_table_base(dev);
|
||||
if (tbl && tbl->it_group) {
|
||||
if (dev->iommu_group) {
|
||||
*ppdev = pdev;
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -1647,6 +1643,41 @@ int eeh_pe_configure(struct eeh_pe *pe)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(eeh_pe_configure);
|
||||
|
||||
/**
|
||||
* eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE
|
||||
* @pe: the indicated PE
|
||||
* @type: error type
|
||||
* @function: error function
|
||||
* @addr: address
|
||||
* @mask: address mask
|
||||
*
|
||||
* The routine is called to inject the specified PCI error, which
|
||||
* is determined by @type and @function, to the indicated PE for
|
||||
* testing purpose.
|
||||
*/
|
||||
int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
|
||||
unsigned long addr, unsigned long mask)
|
||||
{
|
||||
/* Invalid PE ? */
|
||||
if (!pe)
|
||||
return -ENODEV;
|
||||
|
||||
/* Unsupported operation ? */
|
||||
if (!eeh_ops || !eeh_ops->err_inject)
|
||||
return -ENOENT;
|
||||
|
||||
/* Check on PCI error type */
|
||||
if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64)
|
||||
return -EINVAL;
|
||||
|
||||
/* Check on PCI error function */
|
||||
if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
return eeh_ops->err_inject(pe, type, func, addr, mask);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(eeh_pe_inject_err);
|
||||
|
||||
static int proc_eeh_show(struct seq_file *m, void *v)
|
||||
{
|
||||
if (!eeh_enabled()) {
|
||||
|
|
|
|||
|
|
@ -48,11 +48,11 @@
|
|||
*/
|
||||
struct pci_io_addr_range {
|
||||
struct rb_node rb_node;
|
||||
unsigned long addr_lo;
|
||||
unsigned long addr_hi;
|
||||
resource_size_t addr_lo;
|
||||
resource_size_t addr_hi;
|
||||
struct eeh_dev *edev;
|
||||
struct pci_dev *pcidev;
|
||||
unsigned int flags;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
static struct pci_io_addr_cache {
|
||||
|
|
@ -125,8 +125,8 @@ static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
|
|||
|
||||
/* Insert address range into the rb tree. */
|
||||
static struct pci_io_addr_range *
|
||||
eeh_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
|
||||
unsigned long ahi, unsigned int flags)
|
||||
eeh_addr_cache_insert(struct pci_dev *dev, resource_size_t alo,
|
||||
resource_size_t ahi, unsigned long flags)
|
||||
{
|
||||
struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
|
||||
struct rb_node *parent = NULL;
|
||||
|
|
@ -197,9 +197,9 @@ static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
|
|||
|
||||
/* Walk resources on this device, poke them into the tree */
|
||||
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
||||
unsigned long start = pci_resource_start(dev,i);
|
||||
unsigned long end = pci_resource_end(dev,i);
|
||||
unsigned int flags = pci_resource_flags(dev,i);
|
||||
resource_size_t start = pci_resource_start(dev,i);
|
||||
resource_size_t end = pci_resource_end(dev,i);
|
||||
unsigned long flags = pci_resource_flags(dev,i);
|
||||
|
||||
/* We are interested only bus addresses, not dma or other stuff */
|
||||
if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM)))
|
||||
|
|
|
|||
|
|
@ -660,7 +660,7 @@ static void eeh_handle_normal_event(struct eeh_pe *pe)
|
|||
eeh_pe_dev_traverse(pe, eeh_report_error, &result);
|
||||
|
||||
/* Get the current PCI slot state. This can take a long time,
|
||||
* sometimes over 3 seconds for certain systems.
|
||||
* sometimes over 300 seconds for certain systems.
|
||||
*/
|
||||
rc = eeh_ops->wait_state(pe, MAX_WAIT_FOR_RECOVERY*1000);
|
||||
if (rc < 0 || rc == EEH_STATE_NOT_SUPPORT) {
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
#include <asm/ftrace.h>
|
||||
#include <asm/hw_irq.h>
|
||||
#include <asm/context_tracking.h>
|
||||
#include <asm/tm.h>
|
||||
|
||||
/*
|
||||
* System calls.
|
||||
|
|
@ -51,6 +52,12 @@ exception_marker:
|
|||
|
||||
.globl system_call_common
|
||||
system_call_common:
|
||||
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||||
BEGIN_FTR_SECTION
|
||||
extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
|
||||
bne tabort_syscall
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_TM)
|
||||
#endif
|
||||
andi. r10,r12,MSR_PR
|
||||
mr r10,r1
|
||||
addi r1,r1,-INT_FRAME_SIZE
|
||||
|
|
@ -311,6 +318,34 @@ syscall_exit_work:
|
|||
bl do_syscall_trace_leave
|
||||
b ret_from_except
|
||||
|
||||
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||||
tabort_syscall:
|
||||
/* Firstly we need to enable TM in the kernel */
|
||||
mfmsr r10
|
||||
li r13, 1
|
||||
rldimi r10, r13, MSR_TM_LG, 63-MSR_TM_LG
|
||||
mtmsrd r10, 0
|
||||
|
||||
/* tabort, this dooms the transaction, nothing else */
|
||||
li r13, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
|
||||
TABORT(R13)
|
||||
|
||||
/*
|
||||
* Return directly to userspace. We have corrupted user register state,
|
||||
* but userspace will never see that register state. Execution will
|
||||
* resume after the tbegin of the aborted transaction with the
|
||||
* checkpointed register state.
|
||||
*/
|
||||
li r13, MSR_RI
|
||||
andc r10, r10, r13
|
||||
mtmsrd r10, 1
|
||||
mtspr SPRN_SRR0, r11
|
||||
mtspr SPRN_SRR1, r12
|
||||
|
||||
rfid
|
||||
b . /* prevent speculative execution */
|
||||
#endif
|
||||
|
||||
/* Save non-volatile GPRs, if not already saved. */
|
||||
_GLOBAL(save_nvgprs)
|
||||
ld r11,_TRAP(r1)
|
||||
|
|
@ -556,7 +591,7 @@ BEGIN_FTR_SECTION
|
|||
ld r0,THREAD_DSCR(r4)
|
||||
cmpwi r6,0
|
||||
bne 1f
|
||||
ld r0,PACA_DSCR(r13)
|
||||
ld r0,PACA_DSCR_DEFAULT(r13)
|
||||
1:
|
||||
BEGIN_FTR_SECTION_NESTED(70)
|
||||
mfspr r8, SPRN_FSCR
|
||||
|
|
|
|||
|
|
@ -59,14 +59,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
|
|||
|
||||
#if defined(CONFIG_RELOCATABLE)
|
||||
/*
|
||||
* We can't branch directly; in the direct case we use LR
|
||||
* and system_call_entry restores LR. (We thus need to move
|
||||
* LR to r10 in the RFID case too.)
|
||||
* We can't branch directly so we do it via the CTR which
|
||||
* is volatile across system calls.
|
||||
*/
|
||||
#define SYSCALL_PSERIES_2_DIRECT \
|
||||
mflr r10 ; \
|
||||
ld r12,PACAKBASE(r13) ; \
|
||||
LOAD_HANDLER(r12, system_call_entry_direct) ; \
|
||||
LOAD_HANDLER(r12, system_call_entry) ; \
|
||||
mtctr r12 ; \
|
||||
mfspr r12,SPRN_SRR1 ; \
|
||||
/* Re-use of r13... No spare regs to do this */ \
|
||||
|
|
@ -80,7 +79,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
|
|||
mfspr r12,SPRN_SRR1 ; \
|
||||
li r10,MSR_RI ; \
|
||||
mtmsrd r10,1 ; /* Set RI (EE=0) */ \
|
||||
b system_call_entry_direct ;
|
||||
b system_call_common ;
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -969,13 +968,6 @@ hv_facility_unavailable_relon_trampoline:
|
|||
__end_interrupts:
|
||||
|
||||
.align 7
|
||||
system_call_entry_direct:
|
||||
#if defined(CONFIG_RELOCATABLE)
|
||||
/* The first level prologue may have used LR to get here, saving
|
||||
* orig in r10. To save hacking/ifdeffing common code, restore here.
|
||||
*/
|
||||
mtlr r10
|
||||
#endif
|
||||
system_call_entry:
|
||||
b system_call_common
|
||||
|
||||
|
|
|
|||
|
|
@ -48,6 +48,19 @@
|
|||
mtspr spr, reg
|
||||
#endif
|
||||
|
||||
/* Macro to test if an address is a kernel address */
|
||||
#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
|
||||
#define IS_KERNEL(tmp, addr) \
|
||||
andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */
|
||||
#define BRANCH_UNLESS_KERNEL(label) beq label
|
||||
#else
|
||||
#define IS_KERNEL(tmp, addr) \
|
||||
rlwinm tmp, addr, 16, 16, 31; \
|
||||
cmpli cr0, tmp, PAGE_OFFSET >> 16
|
||||
#define BRANCH_UNLESS_KERNEL(label) blt label
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Value for the bits that have fixed value in RPN entries.
|
||||
* Also used for tagging DAR for DTLBerror.
|
||||
|
|
@ -116,13 +129,13 @@ turn_on_mmu:
|
|||
*/
|
||||
#define EXCEPTION_PROLOG \
|
||||
EXCEPTION_PROLOG_0; \
|
||||
mfcr r10; \
|
||||
EXCEPTION_PROLOG_1; \
|
||||
EXCEPTION_PROLOG_2
|
||||
|
||||
#define EXCEPTION_PROLOG_0 \
|
||||
mtspr SPRN_SPRG_SCRATCH0,r10; \
|
||||
mtspr SPRN_SPRG_SCRATCH1,r11; \
|
||||
mfcr r10
|
||||
mtspr SPRN_SPRG_SCRATCH1,r11
|
||||
|
||||
#define EXCEPTION_PROLOG_1 \
|
||||
mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
|
||||
|
|
@ -162,7 +175,6 @@ turn_on_mmu:
|
|||
* Exception exit code.
|
||||
*/
|
||||
#define EXCEPTION_EPILOG_0 \
|
||||
mtcr r10; \
|
||||
mfspr r10,SPRN_SPRG_SCRATCH0; \
|
||||
mfspr r11,SPRN_SPRG_SCRATCH1
|
||||
|
||||
|
|
@ -297,19 +309,22 @@ SystemCall:
|
|||
* We have to use the MD_xxx registers for the tablewalk because the
|
||||
* equivalent MI_xxx registers only perform the attribute functions.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_8xx_CPU15
|
||||
#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
|
||||
addi tmp, addr, PAGE_SIZE; \
|
||||
tlbie tmp; \
|
||||
addi tmp, addr, -PAGE_SIZE; \
|
||||
tlbie tmp
|
||||
#else
|
||||
#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
|
||||
#endif
|
||||
|
||||
InstructionTLBMiss:
|
||||
#ifdef CONFIG_8xx_CPU6
|
||||
mtspr SPRN_DAR, r3
|
||||
mtspr SPRN_SPRG_SCRATCH2, r3
|
||||
#endif
|
||||
EXCEPTION_PROLOG_0
|
||||
mtspr SPRN_SPRG_SCRATCH2, r10
|
||||
mfspr r10, SPRN_SRR0 /* Get effective address of fault */
|
||||
#ifdef CONFIG_8xx_CPU15
|
||||
addi r11, r10, PAGE_SIZE
|
||||
tlbie r11
|
||||
addi r11, r10, -PAGE_SIZE
|
||||
tlbie r11
|
||||
#endif
|
||||
|
||||
/* If we are faulting a kernel address, we have to use the
|
||||
* kernel page tables.
|
||||
|
|
@ -317,24 +332,34 @@ InstructionTLBMiss:
|
|||
#ifdef CONFIG_MODULES
|
||||
/* Only modules will cause ITLB Misses as we always
|
||||
* pin the first 8MB of kernel memory */
|
||||
andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
|
||||
#endif
|
||||
mfspr r11, SPRN_SRR0 /* Get effective address of fault */
|
||||
INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11)
|
||||
mfcr r10
|
||||
IS_KERNEL(r11, r11)
|
||||
mfspr r11, SPRN_M_TW /* Get level 1 table */
|
||||
#ifdef CONFIG_MODULES
|
||||
beq 3f
|
||||
BRANCH_UNLESS_KERNEL(3f)
|
||||
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
|
||||
3:
|
||||
mtcr r10
|
||||
mfspr r10, SPRN_SRR0 /* Get effective address of fault */
|
||||
#else
|
||||
mfspr r10, SPRN_SRR0 /* Get effective address of fault */
|
||||
INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
|
||||
mfspr r11, SPRN_M_TW /* Get level 1 table base address */
|
||||
#endif
|
||||
/* Insert level 1 index */
|
||||
rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
|
||||
lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
|
||||
|
||||
/* Load the MI_TWC with the attributes for this "segment." */
|
||||
MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
|
||||
rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
|
||||
/* Extract level 2 index */
|
||||
rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
|
||||
lwzx r10, r10, r11 /* Get the pte */
|
||||
rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
|
||||
lwz r10, 0(r10) /* Get the pte */
|
||||
|
||||
/* Insert the APG into the TWC from the Linux PTE. */
|
||||
rlwimi r11, r10, 0, 25, 26
|
||||
/* Load the MI_TWC with the attributes for this "segment." */
|
||||
MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
|
||||
|
||||
#ifdef CONFIG_SWAP
|
||||
rlwinm r11, r10, 32-5, _PAGE_PRESENT
|
||||
|
|
@ -343,40 +368,41 @@ InstructionTLBMiss:
|
|||
#endif
|
||||
li r11, RPN_PATTERN
|
||||
/* The Linux PTE won't go exactly into the MMU TLB.
|
||||
* Software indicator bits 21 and 28 must be clear.
|
||||
* Software indicator bits 20-23 and 28 must be clear.
|
||||
* Software indicator bits 24, 25, 26, and 27 must be
|
||||
* set. All other Linux PTE bits control the behavior
|
||||
* of the MMU.
|
||||
*/
|
||||
rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
|
||||
rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */
|
||||
MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
|
||||
|
||||
/* Restore registers */
|
||||
#ifdef CONFIG_8xx_CPU6
|
||||
mfspr r3, SPRN_DAR
|
||||
mtspr SPRN_DAR, r11 /* Tag DAR */
|
||||
mfspr r3, SPRN_SPRG_SCRATCH2
|
||||
#endif
|
||||
mfspr r10, SPRN_SPRG_SCRATCH2
|
||||
EXCEPTION_EPILOG_0
|
||||
rfi
|
||||
|
||||
. = 0x1200
|
||||
DataStoreTLBMiss:
|
||||
#ifdef CONFIG_8xx_CPU6
|
||||
mtspr SPRN_DAR, r3
|
||||
mtspr SPRN_SPRG_SCRATCH2, r3
|
||||
#endif
|
||||
EXCEPTION_PROLOG_0
|
||||
mtspr SPRN_SPRG_SCRATCH2, r10
|
||||
mfspr r10, SPRN_MD_EPN
|
||||
mfcr r10
|
||||
|
||||
/* If we are faulting a kernel address, we have to use the
|
||||
* kernel page tables.
|
||||
*/
|
||||
andis. r11, r10, 0x8000
|
||||
mfspr r11, SPRN_MD_EPN
|
||||
IS_KERNEL(r11, r11)
|
||||
mfspr r11, SPRN_M_TW /* Get level 1 table */
|
||||
beq 3f
|
||||
BRANCH_UNLESS_KERNEL(3f)
|
||||
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
|
||||
3:
|
||||
mtcr r10
|
||||
mfspr r10, SPRN_MD_EPN
|
||||
|
||||
/* Insert level 1 index */
|
||||
rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
|
||||
lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
|
||||
|
|
@ -388,13 +414,13 @@ DataStoreTLBMiss:
|
|||
rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
|
||||
lwz r10, 0(r10) /* Get the pte */
|
||||
|
||||
/* Insert the Guarded flag into the TWC from the Linux PTE.
|
||||
* It is bit 27 of both the Linux PTE and the TWC (at least
|
||||
/* Insert the Guarded flag and APG into the TWC from the Linux PTE.
|
||||
* It is bit 26-27 of both the Linux PTE and the TWC (at least
|
||||
* I got that right :-). It will be better when we can put
|
||||
* this into the Linux pgd/pmd and load it in the operation
|
||||
* above.
|
||||
*/
|
||||
rlwimi r11, r10, 0, 27, 27
|
||||
rlwimi r11, r10, 0, 26, 27
|
||||
/* Insert the WriteThru flag into the TWC from the Linux PTE.
|
||||
* It is bit 25 in the Linux PTE and bit 30 in the TWC
|
||||
*/
|
||||
|
|
@ -423,14 +449,14 @@ DataStoreTLBMiss:
|
|||
*/
|
||||
li r11, RPN_PATTERN
|
||||
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
|
||||
rlwimi r10, r11, 0, 20, 20 /* clear 20 */
|
||||
MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
|
||||
|
||||
/* Restore registers */
|
||||
#ifdef CONFIG_8xx_CPU6
|
||||
mfspr r3, SPRN_DAR
|
||||
mfspr r3, SPRN_SPRG_SCRATCH2
|
||||
#endif
|
||||
mtspr SPRN_DAR, r11 /* Tag DAR */
|
||||
mfspr r10, SPRN_SPRG_SCRATCH2
|
||||
EXCEPTION_EPILOG_0
|
||||
rfi
|
||||
|
||||
|
|
@ -456,6 +482,7 @@ InstructionTLBError:
|
|||
. = 0x1400
|
||||
DataTLBError:
|
||||
EXCEPTION_PROLOG_0
|
||||
mfcr r10
|
||||
|
||||
mfspr r11, SPRN_DAR
|
||||
cmpwi cr0, r11, RPN_PATTERN
|
||||
|
|
@ -503,9 +530,9 @@ FixupDAR:/* Entry point for dcbx workaround. */
|
|||
mtspr SPRN_SPRG_SCRATCH2, r10
|
||||
/* fetch instruction from memory. */
|
||||
mfspr r10, SPRN_SRR0
|
||||
andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
|
||||
IS_KERNEL(r11, r10)
|
||||
mfspr r11, SPRN_M_TW /* Get level 1 table */
|
||||
beq 3f
|
||||
BRANCH_UNLESS_KERNEL(3f)
|
||||
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
|
||||
/* Insert level 1 index */
|
||||
3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
|
||||
|
|
@ -743,15 +770,20 @@ initial_mmu:
|
|||
ori r8, r8, MI_EVALID /* Mark it valid */
|
||||
mtspr SPRN_MI_EPN, r8
|
||||
mtspr SPRN_MD_EPN, r8
|
||||
li r8, MI_PS8MEG /* Set 8M byte page */
|
||||
li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */
|
||||
ori r8, r8, MI_SVALID /* Make it valid */
|
||||
mtspr SPRN_MI_TWC, r8
|
||||
li r8, MI_PS8MEG /* Set 8M byte page, APG 0 */
|
||||
ori r8, r8, MI_SVALID /* Make it valid */
|
||||
mtspr SPRN_MD_TWC, r8
|
||||
li r8, MI_BOOTINIT /* Create RPN for address 0 */
|
||||
mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
|
||||
mtspr SPRN_MD_RPN, r8
|
||||
lis r8, MI_Kp@h /* Set the protection mode */
|
||||
lis r8, MI_APG_INIT@h /* Set protection modes */
|
||||
ori r8, r8, MI_APG_INIT@l
|
||||
mtspr SPRN_MI_AP, r8
|
||||
lis r8, MD_APG_INIT@h
|
||||
ori r8, r8, MD_APG_INIT@l
|
||||
mtspr SPRN_MD_AP, r8
|
||||
|
||||
/* Map another 8 MByte at the IMMR to get the processor
|
||||
|
|
|
|||
|
|
@ -58,15 +58,6 @@ BEGIN_FTR_SECTION
|
|||
mtlr r0
|
||||
lis r3,HID0_NAP@h
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
|
||||
BEGIN_FTR_SECTION
|
||||
msync
|
||||
li r7,L2CSR0_L2FL@l
|
||||
mtspr SPRN_L2CSR0,r7
|
||||
2:
|
||||
mfspr r7,SPRN_L2CSR0
|
||||
andi. r4,r7,L2CSR0_L2FL@l
|
||||
bne 2b
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
|
||||
1:
|
||||
/* Go to NAP or DOZE now */
|
||||
mfspr r4,SPRN_HID0
|
||||
|
|
|
|||
|
|
@ -322,11 +322,11 @@ static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
|
|||
ret = entry << tbl->it_page_shift; /* Set the return dma address */
|
||||
|
||||
/* Put the TCEs in the HW table */
|
||||
build_fail = ppc_md.tce_build(tbl, entry, npages,
|
||||
build_fail = tbl->it_ops->set(tbl, entry, npages,
|
||||
(unsigned long)page &
|
||||
IOMMU_PAGE_MASK(tbl), direction, attrs);
|
||||
|
||||
/* ppc_md.tce_build() only returns non-zero for transient errors.
|
||||
/* tbl->it_ops->set() only returns non-zero for transient errors.
|
||||
* Clean up the table bitmap in this case and return
|
||||
* DMA_ERROR_CODE. For all other errors the functionality is
|
||||
* not altered.
|
||||
|
|
@ -337,8 +337,8 @@ static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
|
|||
}
|
||||
|
||||
/* Flush/invalidate TLB caches if necessary */
|
||||
if (ppc_md.tce_flush)
|
||||
ppc_md.tce_flush(tbl);
|
||||
if (tbl->it_ops->flush)
|
||||
tbl->it_ops->flush(tbl);
|
||||
|
||||
/* Make sure updates are seen by hardware */
|
||||
mb();
|
||||
|
|
@ -408,7 +408,7 @@ static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
|
|||
if (!iommu_free_check(tbl, dma_addr, npages))
|
||||
return;
|
||||
|
||||
ppc_md.tce_free(tbl, entry, npages);
|
||||
tbl->it_ops->clear(tbl, entry, npages);
|
||||
|
||||
spin_lock_irqsave(&(pool->lock), flags);
|
||||
bitmap_clear(tbl->it_map, free_entry, npages);
|
||||
|
|
@ -424,8 +424,8 @@ static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
|
|||
* not do an mb() here on purpose, it is not needed on any of
|
||||
* the current platforms.
|
||||
*/
|
||||
if (ppc_md.tce_flush)
|
||||
ppc_md.tce_flush(tbl);
|
||||
if (tbl->it_ops->flush)
|
||||
tbl->it_ops->flush(tbl);
|
||||
}
|
||||
|
||||
int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
|
||||
|
|
@ -495,7 +495,7 @@ int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
|
|||
npages, entry, dma_addr);
|
||||
|
||||
/* Insert into HW table */
|
||||
build_fail = ppc_md.tce_build(tbl, entry, npages,
|
||||
build_fail = tbl->it_ops->set(tbl, entry, npages,
|
||||
vaddr & IOMMU_PAGE_MASK(tbl),
|
||||
direction, attrs);
|
||||
if(unlikely(build_fail))
|
||||
|
|
@ -534,8 +534,8 @@ int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
|
|||
}
|
||||
|
||||
/* Flush/invalidate TLB caches if necessary */
|
||||
if (ppc_md.tce_flush)
|
||||
ppc_md.tce_flush(tbl);
|
||||
if (tbl->it_ops->flush)
|
||||
tbl->it_ops->flush(tbl);
|
||||
|
||||
DBG("mapped %d elements:\n", outcount);
|
||||
|
||||
|
|
@ -600,8 +600,8 @@ void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
|
|||
* do not do an mb() here, the affected platforms do not need it
|
||||
* when freeing.
|
||||
*/
|
||||
if (ppc_md.tce_flush)
|
||||
ppc_md.tce_flush(tbl);
|
||||
if (tbl->it_ops->flush)
|
||||
tbl->it_ops->flush(tbl);
|
||||
}
|
||||
|
||||
static void iommu_table_clear(struct iommu_table *tbl)
|
||||
|
|
@ -613,17 +613,17 @@ static void iommu_table_clear(struct iommu_table *tbl)
|
|||
*/
|
||||
if (!is_kdump_kernel() || is_fadump_active()) {
|
||||
/* Clear the table in case firmware left allocations in it */
|
||||
ppc_md.tce_free(tbl, tbl->it_offset, tbl->it_size);
|
||||
tbl->it_ops->clear(tbl, tbl->it_offset, tbl->it_size);
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CRASH_DUMP
|
||||
if (ppc_md.tce_get) {
|
||||
if (tbl->it_ops->get) {
|
||||
unsigned long index, tceval, tcecount = 0;
|
||||
|
||||
/* Reserve the existing mappings left by the first kernel. */
|
||||
for (index = 0; index < tbl->it_size; index++) {
|
||||
tceval = ppc_md.tce_get(tbl, index + tbl->it_offset);
|
||||
tceval = tbl->it_ops->get(tbl, index + tbl->it_offset);
|
||||
/*
|
||||
* Freed TCE entry contains 0x7fffffffffffffff on JS20
|
||||
*/
|
||||
|
|
@ -657,6 +657,8 @@ struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
|
|||
unsigned int i;
|
||||
struct iommu_pool *p;
|
||||
|
||||
BUG_ON(!tbl->it_ops);
|
||||
|
||||
/* number of bytes needed for the bitmap */
|
||||
sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
|
||||
|
||||
|
|
@ -713,9 +715,11 @@ void iommu_free_table(struct iommu_table *tbl, const char *node_name)
|
|||
unsigned long bitmap_sz;
|
||||
unsigned int order;
|
||||
|
||||
if (!tbl || !tbl->it_map) {
|
||||
printk(KERN_ERR "%s: expected TCE map for %s\n", __func__,
|
||||
node_name);
|
||||
if (!tbl)
|
||||
return;
|
||||
|
||||
if (!tbl->it_map) {
|
||||
kfree(tbl);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -726,13 +730,6 @@ void iommu_free_table(struct iommu_table *tbl, const char *node_name)
|
|||
if (tbl->it_offset == 0)
|
||||
clear_bit(0, tbl->it_map);
|
||||
|
||||
#ifdef CONFIG_IOMMU_API
|
||||
if (tbl->it_group) {
|
||||
iommu_group_put(tbl->it_group);
|
||||
BUG_ON(tbl->it_group);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* verify that table contains no entries */
|
||||
if (!bitmap_empty(tbl->it_map, tbl->it_size))
|
||||
pr_warn("%s: Unexpected TCEs for %s\n", __func__, node_name);
|
||||
|
|
@ -871,17 +868,33 @@ void iommu_free_coherent(struct iommu_table *tbl, size_t size,
|
|||
}
|
||||
}
|
||||
|
||||
unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir)
|
||||
{
|
||||
switch (dir) {
|
||||
case DMA_BIDIRECTIONAL:
|
||||
return TCE_PCI_READ | TCE_PCI_WRITE;
|
||||
case DMA_FROM_DEVICE:
|
||||
return TCE_PCI_WRITE;
|
||||
case DMA_TO_DEVICE:
|
||||
return TCE_PCI_READ;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_direction_to_tce_perm);
|
||||
|
||||
#ifdef CONFIG_IOMMU_API
|
||||
/*
|
||||
* SPAPR TCE API
|
||||
*/
|
||||
static void group_release(void *iommu_data)
|
||||
{
|
||||
struct iommu_table *tbl = iommu_data;
|
||||
tbl->it_group = NULL;
|
||||
struct iommu_table_group *table_group = iommu_data;
|
||||
|
||||
table_group->group = NULL;
|
||||
}
|
||||
|
||||
void iommu_register_group(struct iommu_table *tbl,
|
||||
void iommu_register_group(struct iommu_table_group *table_group,
|
||||
int pci_domain_number, unsigned long pe_num)
|
||||
{
|
||||
struct iommu_group *grp;
|
||||
|
|
@ -893,8 +906,8 @@ void iommu_register_group(struct iommu_table *tbl,
|
|||
PTR_ERR(grp));
|
||||
return;
|
||||
}
|
||||
tbl->it_group = grp;
|
||||
iommu_group_set_iommudata(grp, tbl, group_release);
|
||||
table_group->group = grp;
|
||||
iommu_group_set_iommudata(grp, table_group, group_release);
|
||||
name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
|
||||
pci_domain_number, pe_num);
|
||||
if (!name)
|
||||
|
|
@ -919,8 +932,8 @@ EXPORT_SYMBOL_GPL(iommu_tce_direction);
|
|||
void iommu_flush_tce(struct iommu_table *tbl)
|
||||
{
|
||||
/* Flush/invalidate TLB caches if necessary */
|
||||
if (ppc_md.tce_flush)
|
||||
ppc_md.tce_flush(tbl);
|
||||
if (tbl->it_ops->flush)
|
||||
tbl->it_ops->flush(tbl);
|
||||
|
||||
/* Make sure updates are seen by hardware */
|
||||
mb();
|
||||
|
|
@ -931,7 +944,7 @@ int iommu_tce_clear_param_check(struct iommu_table *tbl,
|
|||
unsigned long ioba, unsigned long tce_value,
|
||||
unsigned long npages)
|
||||
{
|
||||
/* ppc_md.tce_free() does not support any value but 0 */
|
||||
/* tbl->it_ops->clear() does not support any value but 0 */
|
||||
if (tce_value)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
@ -952,10 +965,7 @@ EXPORT_SYMBOL_GPL(iommu_tce_clear_param_check);
|
|||
int iommu_tce_put_param_check(struct iommu_table *tbl,
|
||||
unsigned long ioba, unsigned long tce)
|
||||
{
|
||||
if (!(tce & (TCE_PCI_WRITE | TCE_PCI_READ)))
|
||||
return -EINVAL;
|
||||
|
||||
if (tce & ~(IOMMU_PAGE_MASK(tbl) | TCE_PCI_WRITE | TCE_PCI_READ))
|
||||
if (tce & ~IOMMU_PAGE_MASK(tbl))
|
||||
return -EINVAL;
|
||||
|
||||
if (ioba & ~IOMMU_PAGE_MASK(tbl))
|
||||
|
|
@ -972,68 +982,16 @@ int iommu_tce_put_param_check(struct iommu_table *tbl,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_tce_put_param_check);
|
||||
|
||||
unsigned long iommu_clear_tce(struct iommu_table *tbl, unsigned long entry)
|
||||
long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry,
|
||||
unsigned long *hpa, enum dma_data_direction *direction)
|
||||
{
|
||||
unsigned long oldtce;
|
||||
struct iommu_pool *pool = get_pool(tbl, entry);
|
||||
long ret;
|
||||
|
||||
spin_lock(&(pool->lock));
|
||||
ret = tbl->it_ops->exchange(tbl, entry, hpa, direction);
|
||||
|
||||
oldtce = ppc_md.tce_get(tbl, entry);
|
||||
if (oldtce & (TCE_PCI_WRITE | TCE_PCI_READ))
|
||||
ppc_md.tce_free(tbl, entry, 1);
|
||||
else
|
||||
oldtce = 0;
|
||||
|
||||
spin_unlock(&(pool->lock));
|
||||
|
||||
return oldtce;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_clear_tce);
|
||||
|
||||
int iommu_clear_tces_and_put_pages(struct iommu_table *tbl,
|
||||
unsigned long entry, unsigned long pages)
|
||||
{
|
||||
unsigned long oldtce;
|
||||
struct page *page;
|
||||
|
||||
for ( ; pages; --pages, ++entry) {
|
||||
oldtce = iommu_clear_tce(tbl, entry);
|
||||
if (!oldtce)
|
||||
continue;
|
||||
|
||||
page = pfn_to_page(oldtce >> PAGE_SHIFT);
|
||||
WARN_ON(!page);
|
||||
if (page) {
|
||||
if (oldtce & TCE_PCI_WRITE)
|
||||
SetPageDirty(page);
|
||||
put_page(page);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_clear_tces_and_put_pages);
|
||||
|
||||
/*
|
||||
* hwaddr is a kernel virtual address here (0xc... bazillion),
|
||||
* tce_build converts it to a physical address.
|
||||
*/
|
||||
int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,
|
||||
unsigned long hwaddr, enum dma_data_direction direction)
|
||||
{
|
||||
int ret = -EBUSY;
|
||||
unsigned long oldtce;
|
||||
struct iommu_pool *pool = get_pool(tbl, entry);
|
||||
|
||||
spin_lock(&(pool->lock));
|
||||
|
||||
oldtce = ppc_md.tce_get(tbl, entry);
|
||||
/* Add new entry if it is not busy */
|
||||
if (!(oldtce & (TCE_PCI_WRITE | TCE_PCI_READ)))
|
||||
ret = ppc_md.tce_build(tbl, entry, 1, hwaddr, direction, NULL);
|
||||
|
||||
spin_unlock(&(pool->lock));
|
||||
if (!ret && ((*direction == DMA_FROM_DEVICE) ||
|
||||
(*direction == DMA_BIDIRECTIONAL)))
|
||||
SetPageDirty(pfn_to_page(*hpa >> PAGE_SHIFT));
|
||||
|
||||
/* if (unlikely(ret))
|
||||
pr_err("iommu_tce: %s failed on hwaddr=%lx ioba=%lx kva=%lx ret=%d\n",
|
||||
|
|
@ -1042,84 +1000,72 @@ int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,
|
|||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_tce_build);
|
||||
|
||||
int iommu_put_tce_user_mode(struct iommu_table *tbl, unsigned long entry,
|
||||
unsigned long tce)
|
||||
{
|
||||
int ret;
|
||||
struct page *page = NULL;
|
||||
unsigned long hwaddr, offset = tce & IOMMU_PAGE_MASK(tbl) & ~PAGE_MASK;
|
||||
enum dma_data_direction direction = iommu_tce_direction(tce);
|
||||
|
||||
ret = get_user_pages_fast(tce & PAGE_MASK, 1,
|
||||
direction != DMA_TO_DEVICE, &page);
|
||||
if (unlikely(ret != 1)) {
|
||||
/* pr_err("iommu_tce: get_user_pages_fast failed tce=%lx ioba=%lx ret=%d\n",
|
||||
tce, entry << tbl->it_page_shift, ret); */
|
||||
return -EFAULT;
|
||||
}
|
||||
hwaddr = (unsigned long) page_address(page) + offset;
|
||||
|
||||
ret = iommu_tce_build(tbl, entry, hwaddr, direction);
|
||||
if (ret)
|
||||
put_page(page);
|
||||
|
||||
if (ret < 0)
|
||||
pr_err("iommu_tce: %s failed ioba=%lx, tce=%lx, ret=%d\n",
|
||||
__func__, entry << tbl->it_page_shift, tce, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_put_tce_user_mode);
|
||||
EXPORT_SYMBOL_GPL(iommu_tce_xchg);
|
||||
|
||||
int iommu_take_ownership(struct iommu_table *tbl)
|
||||
{
|
||||
unsigned long sz = (tbl->it_size + 7) >> 3;
|
||||
unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
|
||||
int ret = 0;
|
||||
|
||||
/*
|
||||
* VFIO does not control TCE entries allocation and the guest
|
||||
* can write new TCEs on top of existing ones so iommu_tce_build()
|
||||
* must be able to release old pages. This functionality
|
||||
* requires exchange() callback defined so if it is not
|
||||
* implemented, we disallow taking ownership over the table.
|
||||
*/
|
||||
if (!tbl->it_ops->exchange)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&tbl->large_pool.lock, flags);
|
||||
for (i = 0; i < tbl->nr_pools; i++)
|
||||
spin_lock(&tbl->pools[i].lock);
|
||||
|
||||
if (tbl->it_offset == 0)
|
||||
clear_bit(0, tbl->it_map);
|
||||
|
||||
if (!bitmap_empty(tbl->it_map, tbl->it_size)) {
|
||||
pr_err("iommu_tce: it_map is not empty");
|
||||
return -EBUSY;
|
||||
ret = -EBUSY;
|
||||
/* Restore bit#0 set by iommu_init_table() */
|
||||
if (tbl->it_offset == 0)
|
||||
set_bit(0, tbl->it_map);
|
||||
} else {
|
||||
memset(tbl->it_map, 0xff, sz);
|
||||
}
|
||||
|
||||
memset(tbl->it_map, 0xff, sz);
|
||||
iommu_clear_tces_and_put_pages(tbl, tbl->it_offset, tbl->it_size);
|
||||
for (i = 0; i < tbl->nr_pools; i++)
|
||||
spin_unlock(&tbl->pools[i].lock);
|
||||
spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
|
||||
|
||||
/*
|
||||
* Disable iommu bypass, otherwise the user can DMA to all of
|
||||
* our physical memory via the bypass window instead of just
|
||||
* the pages that has been explicitly mapped into the iommu
|
||||
*/
|
||||
if (tbl->set_bypass)
|
||||
tbl->set_bypass(tbl, false);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_take_ownership);
|
||||
|
||||
void iommu_release_ownership(struct iommu_table *tbl)
|
||||
{
|
||||
unsigned long sz = (tbl->it_size + 7) >> 3;
|
||||
unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
|
||||
|
||||
spin_lock_irqsave(&tbl->large_pool.lock, flags);
|
||||
for (i = 0; i < tbl->nr_pools; i++)
|
||||
spin_lock(&tbl->pools[i].lock);
|
||||
|
||||
iommu_clear_tces_and_put_pages(tbl, tbl->it_offset, tbl->it_size);
|
||||
memset(tbl->it_map, 0, sz);
|
||||
|
||||
/* Restore bit#0 set by iommu_init_table() */
|
||||
if (tbl->it_offset == 0)
|
||||
set_bit(0, tbl->it_map);
|
||||
|
||||
/* The kernel owns the device now, we can restore the iommu bypass */
|
||||
if (tbl->set_bypass)
|
||||
tbl->set_bypass(tbl, true);
|
||||
for (i = 0; i < tbl->nr_pools; i++)
|
||||
spin_unlock(&tbl->pools[i].lock);
|
||||
spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_release_ownership);
|
||||
|
||||
int iommu_add_device(struct device *dev)
|
||||
{
|
||||
struct iommu_table *tbl;
|
||||
struct iommu_table_group_link *tgl;
|
||||
|
||||
/*
|
||||
* The sysfs entries should be populated before
|
||||
|
|
@ -1137,15 +1083,22 @@ int iommu_add_device(struct device *dev)
|
|||
}
|
||||
|
||||
tbl = get_iommu_table_base(dev);
|
||||
if (!tbl || !tbl->it_group) {
|
||||
if (!tbl) {
|
||||
pr_debug("%s: Skipping device %s with no tbl\n",
|
||||
__func__, dev_name(dev));
|
||||
return 0;
|
||||
}
|
||||
|
||||
tgl = list_first_entry_or_null(&tbl->it_group_list,
|
||||
struct iommu_table_group_link, next);
|
||||
if (!tgl) {
|
||||
pr_debug("%s: Skipping device %s with no group\n",
|
||||
__func__, dev_name(dev));
|
||||
return 0;
|
||||
}
|
||||
pr_debug("%s: Adding %s to iommu group %d\n",
|
||||
__func__, dev_name(dev),
|
||||
iommu_group_id(tbl->it_group));
|
||||
iommu_group_id(tgl->table_group->group));
|
||||
|
||||
if (PAGE_SIZE < IOMMU_PAGE_SIZE(tbl)) {
|
||||
pr_err("%s: Invalid IOMMU page size %lx (%lx) on %s\n",
|
||||
|
|
@ -1154,7 +1107,7 @@ int iommu_add_device(struct device *dev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
return iommu_group_add_device(tbl->it_group, dev);
|
||||
return iommu_group_add_device(tgl->table_group->group, dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_add_device);
|
||||
|
||||
|
|
|
|||
|
|
@ -15,7 +15,10 @@
|
|||
|
||||
int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
|
||||
{
|
||||
if (!ppc_md.setup_msi_irqs || !ppc_md.teardown_msi_irqs) {
|
||||
struct pci_controller *phb = pci_bus_to_host(dev->bus);
|
||||
|
||||
if (!phb->controller_ops.setup_msi_irqs ||
|
||||
!phb->controller_ops.teardown_msi_irqs) {
|
||||
pr_debug("msi: Platform doesn't provide MSI callbacks.\n");
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
|
@ -24,10 +27,12 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
|
|||
if (type == PCI_CAP_ID_MSI && nvec > 1)
|
||||
return 1;
|
||||
|
||||
return ppc_md.setup_msi_irqs(dev, nvec, type);
|
||||
return phb->controller_ops.setup_msi_irqs(dev, nvec, type);
|
||||
}
|
||||
|
||||
void arch_teardown_msi_irqs(struct pci_dev *dev)
|
||||
{
|
||||
ppc_md.teardown_msi_irqs(dev);
|
||||
struct pci_controller *phb = pci_bus_to_host(dev->bus);
|
||||
|
||||
phb->controller_ops.teardown_msi_irqs(dev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -89,6 +89,7 @@ struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
|
|||
#endif
|
||||
return phb;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
|
||||
|
||||
void pcibios_free_controller(struct pci_controller *phb)
|
||||
{
|
||||
|
|
@ -1447,6 +1448,7 @@ void pcibios_claim_one_bus(struct pci_bus *bus)
|
|||
list_for_each_entry(child_bus, &bus->children, node)
|
||||
pcibios_claim_one_bus(child_bus);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
|
||||
|
||||
|
||||
/* pcibios_finish_adding_to_bus
|
||||
|
|
@ -1488,6 +1490,14 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
|
|||
return pci_enable_resources(dev, mask);
|
||||
}
|
||||
|
||||
void pcibios_disable_device(struct pci_dev *dev)
|
||||
{
|
||||
struct pci_controller *phb = pci_bus_to_host(dev->bus);
|
||||
|
||||
if (phb->controller_ops.disable_device)
|
||||
phb->controller_ops.disable_device(dev);
|
||||
}
|
||||
|
||||
resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
|
||||
{
|
||||
return (unsigned long) hose->io_base_virt - _IO_BASE;
|
||||
|
|
@ -1680,6 +1690,7 @@ void pcibios_scan_phb(struct pci_controller *hose)
|
|||
pcie_bus_configure_settings(child);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pcibios_scan_phb);
|
||||
|
||||
static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -29,7 +29,12 @@
|
|||
*/
|
||||
void pcibios_release_device(struct pci_dev *dev)
|
||||
{
|
||||
struct pci_controller *phb = pci_bus_to_host(dev->bus);
|
||||
|
||||
eeh_remove_device(dev);
|
||||
|
||||
if (phb->controller_ops.release_device)
|
||||
phb->controller_ops.release_device(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -1112,7 +1112,6 @@ static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
|
|||
/*
|
||||
* Copy a thread..
|
||||
*/
|
||||
extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */
|
||||
|
||||
/*
|
||||
* Copy architecture-specific thread state
|
||||
|
|
|
|||
|
|
@ -523,7 +523,8 @@ void __init setup_system(void)
|
|||
smp_release_cpus();
|
||||
#endif
|
||||
|
||||
pr_info("Starting Linux PPC64 %s\n", init_utsname()->version);
|
||||
pr_info("Starting Linux %s %s\n", init_utsname()->machine,
|
||||
init_utsname()->version);
|
||||
|
||||
pr_info("-----------------------------------------------------\n");
|
||||
pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
|
||||
|
|
@ -685,6 +686,9 @@ void __init setup_arch(char **cmdline_p)
|
|||
init_mm.brk = klimit;
|
||||
#ifdef CONFIG_PPC_64K_PAGES
|
||||
init_mm.context.pte_frag = NULL;
|
||||
#endif
|
||||
#ifdef CONFIG_SPAPR_TCE_IOMMU
|
||||
mm_iommu_init(&init_mm.context);
|
||||
#endif
|
||||
irqstack_early_init();
|
||||
exc_lvl_early_init();
|
||||
|
|
|
|||
|
|
@ -496,13 +496,34 @@ static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
|
|||
static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
|
||||
static DEVICE_ATTR(pir, 0400, show_pir, NULL);
|
||||
|
||||
/*
|
||||
* This is the system wide DSCR register default value. Any
|
||||
* change to this default value through the sysfs interface
|
||||
* will update all per cpu DSCR default values across the
|
||||
* system stored in their respective PACA structures.
|
||||
*/
|
||||
static unsigned long dscr_default;
|
||||
|
||||
/**
|
||||
* read_dscr() - Fetch the cpu specific DSCR default
|
||||
* @val: Returned cpu specific DSCR default value
|
||||
*
|
||||
* This function returns the per cpu DSCR default value
|
||||
* for any cpu which is contained in it's PACA structure.
|
||||
*/
|
||||
static void read_dscr(void *val)
|
||||
{
|
||||
*(unsigned long *)val = get_paca()->dscr_default;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* write_dscr() - Update the cpu specific DSCR default
|
||||
* @val: New cpu specific DSCR default value to update
|
||||
*
|
||||
* This function updates the per cpu DSCR default value
|
||||
* for any cpu which is contained in it's PACA structure.
|
||||
*/
|
||||
static void write_dscr(void *val)
|
||||
{
|
||||
get_paca()->dscr_default = *(unsigned long *)val;
|
||||
|
|
@ -520,12 +541,29 @@ static void add_write_permission_dev_attr(struct device_attribute *attr)
|
|||
attr->attr.mode |= 0200;
|
||||
}
|
||||
|
||||
/**
|
||||
* show_dscr_default() - Fetch the system wide DSCR default
|
||||
* @dev: Device structure
|
||||
* @attr: Device attribute structure
|
||||
* @buf: Interface buffer
|
||||
*
|
||||
* This function returns the system wide DSCR default value.
|
||||
*/
|
||||
static ssize_t show_dscr_default(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
return sprintf(buf, "%lx\n", dscr_default);
|
||||
}
|
||||
|
||||
/**
|
||||
* store_dscr_default() - Update the system wide DSCR default
|
||||
* @dev: Device structure
|
||||
* @attr: Device attribute structure
|
||||
* @buf: Interface buffer
|
||||
* @count: Size of the update
|
||||
*
|
||||
* This function updates the system wide DSCR default value.
|
||||
*/
|
||||
static ssize_t __used store_dscr_default(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf,
|
||||
size_t count)
|
||||
|
|
|
|||
|
|
@ -293,7 +293,7 @@ dont_backup_fp:
|
|||
ld r2, STK_GOT(r1)
|
||||
|
||||
/* Load CPU's default DSCR */
|
||||
ld r0, PACA_DSCR(r13)
|
||||
ld r0, PACA_DSCR_DEFAULT(r13)
|
||||
mtspr SPRN_DSCR, r0
|
||||
|
||||
blr
|
||||
|
|
@ -473,7 +473,7 @@ restore_gprs:
|
|||
ld r2, STK_GOT(r1)
|
||||
|
||||
/* Load CPU's default DSCR */
|
||||
ld r0, PACA_DSCR(r13)
|
||||
ld r0, PACA_DSCR_DEFAULT(r13)
|
||||
mtspr SPRN_DSCR, r0
|
||||
|
||||
blr
|
||||
|
|
|
|||
|
|
@ -1377,6 +1377,7 @@ void facility_unavailable_exception(struct pt_regs *regs)
|
|||
};
|
||||
char *facility = "unknown";
|
||||
u64 value;
|
||||
u32 instword, rd;
|
||||
u8 status;
|
||||
bool hv;
|
||||
|
||||
|
|
@ -1388,12 +1389,46 @@ void facility_unavailable_exception(struct pt_regs *regs)
|
|||
|
||||
status = value >> 56;
|
||||
if (status == FSCR_DSCR_LG) {
|
||||
/* User is acessing the DSCR. Set the inherit bit and allow
|
||||
* the user to set it directly in future by setting via the
|
||||
* FSCR DSCR bit. We always leave HFSCR DSCR set.
|
||||
/*
|
||||
* User is accessing the DSCR register using the problem
|
||||
* state only SPR number (0x03) either through a mfspr or
|
||||
* a mtspr instruction. If it is a write attempt through
|
||||
* a mtspr, then we set the inherit bit. This also allows
|
||||
* the user to write or read the register directly in the
|
||||
* future by setting via the FSCR DSCR bit. But in case it
|
||||
* is a read DSCR attempt through a mfspr instruction, we
|
||||
* just emulate the instruction instead. This code path will
|
||||
* always emulate all the mfspr instructions till the user
|
||||
* has attempted atleast one mtspr instruction. This way it
|
||||
* preserves the same behaviour when the user is accessing
|
||||
* the DSCR through privilege level only SPR number (0x11)
|
||||
* which is emulated through illegal instruction exception.
|
||||
* We always leave HFSCR DSCR set.
|
||||
*/
|
||||
current->thread.dscr_inherit = 1;
|
||||
mtspr(SPRN_FSCR, value | FSCR_DSCR);
|
||||
if (get_user(instword, (u32 __user *)(regs->nip))) {
|
||||
pr_err("Failed to fetch the user instruction\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Write into DSCR (mtspr 0x03, RS) */
|
||||
if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
|
||||
== PPC_INST_MTSPR_DSCR_USER) {
|
||||
rd = (instword >> 21) & 0x1f;
|
||||
current->thread.dscr = regs->gpr[rd];
|
||||
current->thread.dscr_inherit = 1;
|
||||
mtspr(SPRN_FSCR, value | FSCR_DSCR);
|
||||
}
|
||||
|
||||
/* Read from DSCR (mfspr RT, 0x03) */
|
||||
if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
|
||||
== PPC_INST_MFSPR_DSCR_USER) {
|
||||
if (emulate_instruction(regs)) {
|
||||
pr_err("DSCR based mfspr emulation failed\n");
|
||||
return;
|
||||
}
|
||||
regs->nip += 4;
|
||||
emulate_single_step(regs);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue