[PARISC] Add support for Quicksilver AGPGART
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
This commit is contained in:
Kyle McMartin
Matthew Wilcox
parent
983daeec99
commit
08a6436816
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@ -1,6 +1,6 @@
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config AGP
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tristate "/dev/agpgart (AGP Support)"
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depends on ALPHA || IA64 || PPC || X86
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depends on ALPHA || IA64 || PARISC || PPC || X86
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depends on PCI
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---help---
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AGP (Accelerated Graphics Port) is a bus system mainly used to
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@ -122,6 +122,14 @@ config AGP_HP_ZX1
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This option gives you AGP GART support for the HP ZX1 chipset
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for IA64 processors.
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config AGP_PARISC
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tristate "HP Quicksilver AGP support"
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depends on AGP && PARISC && 64BIT
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help
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This option gives you AGP GART support for the HP Quicksilver
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AGP bus adapter on HP PA-RISC machines (Ok, just on the C8000
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workstation...)
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config AGP_ALPHA_CORE
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tristate "Alpha AGP support"
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depends on AGP && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL)
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@ -8,6 +8,7 @@ obj-$(CONFIG_AGP_AMD64) += amd64-agp.o
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obj-$(CONFIG_AGP_ALPHA_CORE) += alpha-agp.o
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obj-$(CONFIG_AGP_EFFICEON) += efficeon-agp.o
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obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
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obj-$(CONFIG_AGP_PARISC) += parisc-agp.o
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obj-$(CONFIG_AGP_I460) += i460-agp.o
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obj-$(CONFIG_AGP_INTEL) += intel-agp.o
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obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o
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@ -0,0 +1,416 @@
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/*
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* HP Quicksilver AGP GART routines
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*
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* Copyright (c) 2006, Kyle McMartin <kyle@parisc-linux.org>
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*
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* Based on drivers/char/agpgart/hp-agp.c which is
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* (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
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* Bjorn Helgaas <bjorn.helgaas@hp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/klist.h>
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#include <linux/agp_backend.h>
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#include <asm-parisc/parisc-device.h>
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#include <asm-parisc/ropes.h>
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#include "agp.h"
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#define DRVNAME "quicksilver"
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#define DRVPFX DRVNAME ": "
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#ifndef log2
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#define log2(x) ffz(~(x))
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#endif
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#define AGP8X_MODE_BIT 3
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#define AGP8X_MODE (1 << AGP8X_MODE_BIT)
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static struct _parisc_agp_info {
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void __iomem *ioc_regs;
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void __iomem *lba_regs;
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int lba_cap_offset;
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u64 *gatt;
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u64 gatt_entries;
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u64 gart_base;
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u64 gart_size;
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int io_page_size;
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int io_pages_per_kpage;
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} parisc_agp_info;
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static struct gatt_mask parisc_agp_masks[] =
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{
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{
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.mask = SBA_PDIR_VALID_BIT,
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.type = 0
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}
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};
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static struct aper_size_info_fixed parisc_agp_sizes[] =
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{
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{0, 0, 0}, /* filled in by parisc_agp_fetch_size() */
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};
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static int
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parisc_agp_fetch_size(void)
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{
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int size;
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size = parisc_agp_info.gart_size / MB(1);
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parisc_agp_sizes[0].size = size;
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agp_bridge->current_size = (void *) &parisc_agp_sizes[0];
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return size;
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}
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static int
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parisc_agp_configure(void)
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{
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struct _parisc_agp_info *info = &parisc_agp_info;
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agp_bridge->gart_bus_addr = info->gart_base;
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agp_bridge->capndx = info->lba_cap_offset;
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agp_bridge->mode = readl(info->lba_regs+info->lba_cap_offset+PCI_AGP_STATUS);
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return 0;
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}
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static void
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parisc_agp_tlbflush(struct agp_memory *mem)
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{
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struct _parisc_agp_info *info = &parisc_agp_info;
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writeq(info->gart_base | log2(info->gart_size), info->ioc_regs+IOC_PCOM);
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readq(info->ioc_regs+IOC_PCOM); /* flush */
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}
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static int
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parisc_agp_create_gatt_table(struct agp_bridge_data *bridge)
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{
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struct _parisc_agp_info *info = &parisc_agp_info;
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int i;
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for (i = 0; i < info->gatt_entries; i++) {
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info->gatt[i] = (unsigned long)agp_bridge->scratch_page;
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}
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return 0;
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}
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static int
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parisc_agp_free_gatt_table(struct agp_bridge_data *bridge)
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{
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struct _parisc_agp_info *info = &parisc_agp_info;
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info->gatt[0] = SBA_AGPGART_COOKIE;
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return 0;
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}
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static int
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parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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struct _parisc_agp_info *info = &parisc_agp_info;
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int i, k;
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off_t j, io_pg_start;
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int io_pg_count;
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if (type != 0 || mem->type != 0) {
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return -EINVAL;
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}
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io_pg_start = info->io_pages_per_kpage * pg_start;
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io_pg_count = info->io_pages_per_kpage * mem->page_count;
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if ((io_pg_start + io_pg_count) > info->gatt_entries) {
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return -EINVAL;
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}
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j = io_pg_start;
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while (j < (io_pg_start + io_pg_count)) {
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if (info->gatt[j])
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return -EBUSY;
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j++;
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}
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if (mem->is_flushed == FALSE) {
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global_cache_flush();
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mem->is_flushed = TRUE;
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}
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for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
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unsigned long paddr;
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paddr = mem->memory[i];
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for (k = 0;
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k < info->io_pages_per_kpage;
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k++, j++, paddr += info->io_page_size) {
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info->gatt[j] =
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agp_bridge->driver->mask_memory(agp_bridge,
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paddr, type);
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}
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}
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agp_bridge->driver->tlb_flush(mem);
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return 0;
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}
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static int
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parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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struct _parisc_agp_info *info = &parisc_agp_info;
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int i, io_pg_start, io_pg_count;
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if (type != 0 || mem->type != 0) {
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return -EINVAL;
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}
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io_pg_start = info->io_pages_per_kpage * pg_start;
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io_pg_count = info->io_pages_per_kpage * mem->page_count;
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for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
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info->gatt[i] = agp_bridge->scratch_page;
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}
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agp_bridge->driver->tlb_flush(mem);
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return 0;
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}
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static unsigned long
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parisc_agp_mask_memory(struct agp_bridge_data *bridge,
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unsigned long addr, int type)
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{
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return SBA_PDIR_VALID_BIT | addr;
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}
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static void
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parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode)
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{
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struct _parisc_agp_info *info = &parisc_agp_info;
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u32 command;
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command = readl(info->lba_regs + info->lba_cap_offset + PCI_AGP_STATUS);
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command = agp_collect_device_status(bridge, mode, command);
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command |= 0x00000100;
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writel(command, info->lba_regs + info->lba_cap_offset + PCI_AGP_COMMAND);
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agp_device_command(command, (mode & AGP8X_MODE) != 0);
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}
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struct agp_bridge_driver parisc_agp_driver = {
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.owner = THIS_MODULE,
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.size_type = FIXED_APER_SIZE,
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.configure = parisc_agp_configure,
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.fetch_size = parisc_agp_fetch_size,
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.tlb_flush = parisc_agp_tlbflush,
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.mask_memory = parisc_agp_mask_memory,
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.masks = parisc_agp_masks,
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.agp_enable = parisc_agp_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = parisc_agp_create_gatt_table,
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.free_gatt_table = parisc_agp_free_gatt_table,
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.insert_memory = parisc_agp_insert_memory,
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.remove_memory = parisc_agp_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_destroy_page = agp_generic_destroy_page,
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.cant_use_aperture = 1,
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};
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static int __init
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agp_ioc_init(void __iomem *ioc_regs)
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{
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struct _parisc_agp_info *info = &parisc_agp_info;
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u64 *iova_base, *io_pdir, io_tlb_ps;
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int io_tlb_shift;
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printk(KERN_INFO DRVPFX "IO PDIR shared with sba_iommu\n");
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info->ioc_regs = ioc_regs;
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io_tlb_ps = readq(info->ioc_regs+IOC_TCNFG);
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switch (io_tlb_ps) {
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case 0: io_tlb_shift = 12; break;
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case 1: io_tlb_shift = 13; break;
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case 2: io_tlb_shift = 14; break;
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case 3: io_tlb_shift = 16; break;
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default:
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printk(KERN_ERR DRVPFX "Invalid IOTLB page size "
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"configuration 0x%llx\n", io_tlb_ps);
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info->gatt = NULL;
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info->gatt_entries = 0;
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return -ENODEV;
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}
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info->io_page_size = 1 << io_tlb_shift;
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info->io_pages_per_kpage = PAGE_SIZE / info->io_page_size;
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iova_base = readq(info->ioc_regs+IOC_IBASE) & ~0x1;
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info->gart_base = iova_base + PLUTO_IOVA_SIZE - PLUTO_GART_SIZE;
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info->gart_size = PLUTO_GART_SIZE;
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info->gatt_entries = info->gart_size / info->io_page_size;
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io_pdir = phys_to_virt(readq(info->ioc_regs+IOC_PDIR_BASE));
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info->gatt = &io_pdir[(PLUTO_IOVA_SIZE/2) >> PAGE_SHIFT];
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if (info->gatt[0] != SBA_AGPGART_COOKIE) {
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info->gatt = NULL;
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info->gatt_entries = 0;
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printk(KERN_ERR DRVPFX "No reserved IO PDIR entry found; "
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"GART disabled\n");
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return -ENODEV;
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}
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return 0;
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}
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static int
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lba_find_capability(int cap)
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{
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struct _parisc_agp_info *info = &parisc_agp_info;
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u16 status;
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u8 pos, id;
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int ttl = 48;
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status = readw(info->lba_regs + PCI_STATUS);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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pos = readb(info->lba_regs + PCI_CAPABILITY_LIST);
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while (ttl-- && pos >= 0x40) {
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pos &= ~3;
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id = readb(info->lba_regs + pos + PCI_CAP_LIST_ID);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos = readb(info->lba_regs + pos + PCI_CAP_LIST_NEXT);
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}
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return 0;
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}
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static int __init
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agp_lba_init(void __iomem *lba_hpa)
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{
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struct _parisc_agp_info *info = &parisc_agp_info;
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int cap;
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info->lba_regs = lba_hpa;
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info->lba_cap_offset = lba_find_capability(PCI_CAP_ID_AGP);
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cap = readl(lba_hpa + info->lba_cap_offset) & 0xff;
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if (cap != PCI_CAP_ID_AGP) {
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printk(KERN_ERR DRVPFX "Invalid capability ID 0x%02x at 0x%x\n",
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cap, info->lba_cap_offset);
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return -ENODEV;
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}
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return 0;
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}
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static int __init
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parisc_agp_setup(void __iomem *ioc_hpa, void __iomem *lba_hpa)
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{
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struct pci_dev *fake_bridge_dev = NULL;
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struct agp_bridge_data *bridge;
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int error = 0;
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fake_bridge_dev = kmalloc(sizeof (struct pci_dev), GFP_KERNEL);
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if (!fake_bridge_dev) {
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error = -ENOMEM;
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goto fail;
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}
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error = agp_ioc_init(ioc_hpa);
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if (error)
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goto fail;
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error = agp_lba_init(lba_hpa);
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if (error)
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goto fail;
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bridge = agp_alloc_bridge();
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if (!bridge) {
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error = -ENOMEM;
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goto fail;
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}
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bridge->driver = &parisc_agp_driver;
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fake_bridge_dev->vendor = PCI_VENDOR_ID_HP;
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fake_bridge_dev->device = PCI_DEVICE_ID_HP_PCIX_LBA;
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bridge->dev = fake_bridge_dev;
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error = agp_add_bridge(bridge);
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fail:
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return error;
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}
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static struct device *next_device(struct klist_iter *i) {
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struct klist_node * n = klist_next(i);
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return n ? container_of(n, struct device, knode_parent) : NULL;
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}
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static int
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parisc_agp_init(void)
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{
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extern struct sba_device *sba_list;
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int err = -1;
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struct parisc_device *sba = NULL, *lba = NULL;
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struct lba_device *lbadev = NULL;
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struct device *dev = NULL;
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struct klist_iter i;
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if (!sba_list)
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goto out;
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/* Find our parent Pluto */
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sba = sba_list->dev;
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if (!IS_PLUTO(sba)) {
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printk(KERN_INFO DRVPFX "No Pluto found, so no AGPGART for you.\n");
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goto out;
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}
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/* Now search our Pluto for our precious AGP device... */
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klist_iter_init(&sba->dev.klist_children, &i);
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while ((dev = next_device(&i))) {
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struct parisc_device *padev = to_parisc_device(dev);
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if (IS_QUICKSILVER(padev))
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lba = padev;
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}
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klist_iter_exit(&i);
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if (!lba) {
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printk(KERN_INFO DRVPFX "No AGP devices found.\n");
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goto out;
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}
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lbadev = parisc_get_drvdata(lba);
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/* w00t, let's go find our cookies... */
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parisc_agp_setup(sba_list->ioc[0].ioc_hpa, lbadev->hba.base_addr);
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return 0;
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out:
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return err;
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}
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module_init(parisc_agp_init);
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MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>");
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MODULE_LICENSE("GPL");
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|
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@ -89,7 +89,8 @@
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#define DEFAULT_DMA_HINT_REG 0
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static struct sba_device *sba_list;
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struct sba_device *sba_list;
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EXPORT_SYMBOL_GPL(sba_list);
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static unsigned long ioc_needs_fdc = 0;
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@ -102,8 +103,14 @@ static unsigned long piranha_bad_128k = 0;
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/* Looks nice and keeps the compiler happy */
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#define SBA_DEV(d) ((struct sba_device *) (d))
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#ifdef CONFIG_AGP_PARISC
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#define SBA_AGP_SUPPORT
|
||||
#endif /*CONFIG_AGP_PARISC*/
|
||||
|
||||
#ifdef SBA_AGP_SUPPORT
|
||||
static int reserve_sba_gart = 1;
|
||||
static int sba_reserve_agpgart = 1;
|
||||
module_param(sba_reserve_agpgart, int, 1);
|
||||
MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
|
||||
#endif
|
||||
|
||||
#define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
|
||||
|
|
@ -1300,6 +1307,10 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
|
|||
WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
|
||||
|
||||
#ifdef SBA_AGP_SUPPORT
|
||||
{
|
||||
struct klist_iter i;
|
||||
struct device *dev = NULL;
|
||||
|
||||
/*
|
||||
** If an AGP device is present, only use half of the IOV space
|
||||
** for PCI DMA. Unfortunately we can't know ahead of time
|
||||
|
|
@ -1308,20 +1319,22 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
|
|||
** We program the next pdir index after we stop w/ a key for
|
||||
** the GART code to handshake on.
|
||||
*/
|
||||
device=NULL;
|
||||
for (lba = sba->child; lba; lba = lba->sibling) {
|
||||
klist_iter_init(&sba->dev.klist_children, &i);
|
||||
while (dev = next_device(&i)) {
|
||||
struct parisc_device *lba = to_parisc_device(dev);
|
||||
if (IS_QUICKSILVER(lba))
|
||||
break;
|
||||
agp_found = 1;
|
||||
}
|
||||
klist_iter_exit(&sba->dev.klist_children, &i);
|
||||
|
||||
if (lba) {
|
||||
DBG_INIT("%s: Reserving half of IOVA space for AGP GART support\n", __FUNCTION__);
|
||||
if (agp_found && sba_reserve_agpgart) {
|
||||
printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
|
||||
__FUNCTION__, (iova_space_size/2) >> 20);
|
||||
ioc->pdir_size /= 2;
|
||||
((u64 *)ioc->pdir_base)[PDIR_INDEX(iova_space_size/2)] = SBA_IOMMU_COOKIE;
|
||||
} else {
|
||||
DBG_INIT("%s: No GART needed - no AGP controller found\n", __FUNCTION__);
|
||||
ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
|
||||
}
|
||||
#endif /* 0 */
|
||||
}
|
||||
#endif /*SBA_AGP_SUPPORT*/
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
#ifndef _ASM_PARISC_AGP_H
|
||||
#define _ASM_PARISC_AGP_H
|
||||
|
||||
/*
|
||||
* PARISC specific AGP definitions.
|
||||
* Copyright (c) 2006 Kyle McMartin <kyle@parisc-linux.org>
|
||||
*
|
||||
*/
|
||||
|
||||
#define map_page_into_agp(page) /* nothing */
|
||||
#define unmap_page_from_agp(page) /* nothing */
|
||||
#define flush_agp_mappings() /* nothing */
|
||||
#define flush_agp_cache() mb()
|
||||
|
||||
/* Convert a physical address to an address suitable for the GART. */
|
||||
#define phys_to_gart(x) (x)
|
||||
#define gart_to_phys(x) (x)
|
||||
|
||||
/* GATT allocation. Returns/accepts GATT kernel virtual address. */
|
||||
#define alloc_gatt_pages(order) \
|
||||
((char *)__get_free_pages(GFP_KERNEL, (order)))
|
||||
#define free_gatt_pages(table, order) \
|
||||
free_pages((unsigned long)(table), (order))
|
||||
|
||||
#endif /* _ASM_PARISC_AGP_H */
|
||||
|
|
@ -1,6 +1,8 @@
|
|||
#ifndef _ASM_PARISC_ROPES_H_
|
||||
#define _ASM_PARISC_ROPES_H_
|
||||
|
||||
#include <asm-parisc/parisc-device.h>
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
|
||||
#define ZX1_SUPPORT
|
||||
|
|
@ -231,6 +233,16 @@ static inline int IS_QUICKSILVER(struct parisc_device *d) {
|
|||
return (d->id.hversion == QUICKSILVER_HVERS);
|
||||
}
|
||||
|
||||
static inline int agp_mode_mercury(void __iomem *hpa) {
|
||||
u64 bus_mode;
|
||||
|
||||
bus_mode = readl(hpa + 0x0620);
|
||||
if (bus_mode & 1)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
** I/O SAPIC init function
|
||||
** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
|
||||
|
|
|
|||
Loading…
Reference in New Issue