gpu: host1x: mipi: Calibrate clock lanes
Include the clock lanes when calibrating the MIPI PHY on Tegra124 compatible devices. Signed-off-by: Sean Paul <seanpaul@chromium.org> [treding@nvidia.com: bikeshedding] Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Sean Paul
Thierry Reding
parent
26f7a92a3a
commit
08a15cc34d
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@ -49,11 +49,24 @@
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#define MIPI_CAL_CONFIG_DSIC 0x10
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#define MIPI_CAL_CONFIG_DSID 0x11
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#define MIPI_CAL_CONFIG_DSIAB_CLK 0x19
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#define MIPI_CAL_CONFIG_DSICD_CLK 0x1a
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#define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b
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#define MIPI_CAL_CONFIG_CSICD_CLK 0x1c
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#define MIPI_CAL_CONFIG_CSIE_CLK 0x1d
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/* for data and clock lanes */
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#define MIPI_CAL_CONFIG_SELECT (1 << 21)
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/* for data lanes */
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#define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16)
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#define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8)
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#define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0)
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/* for clock lanes */
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#define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8)
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#define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0)
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#define MIPI_CAL_BIAS_PAD_CFG0 0x16
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#define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1)
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#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0)
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@ -63,21 +76,19 @@
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#define MIPI_CAL_BIAS_PAD_CFG2 0x18
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#define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1)
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static const struct module {
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unsigned long reg;
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} modules[] = {
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{ .reg = MIPI_CAL_CONFIG_CSIA },
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{ .reg = MIPI_CAL_CONFIG_CSIB },
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{ .reg = MIPI_CAL_CONFIG_CSIC },
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{ .reg = MIPI_CAL_CONFIG_CSID },
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{ .reg = MIPI_CAL_CONFIG_CSIE },
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{ .reg = MIPI_CAL_CONFIG_DSIA },
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{ .reg = MIPI_CAL_CONFIG_DSIB },
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{ .reg = MIPI_CAL_CONFIG_DSIC },
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{ .reg = MIPI_CAL_CONFIG_DSID },
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struct tegra_mipi_pad {
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unsigned long data;
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unsigned long clk;
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};
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struct tegra_mipi_soc {
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bool has_clk_lane;
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const struct tegra_mipi_pad *pads;
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unsigned int num_pads;
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};
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struct tegra_mipi {
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const struct tegra_mipi_soc *soc;
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void __iomem *regs;
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struct mutex lock;
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struct clk *clk;
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@ -117,36 +128,35 @@ struct tegra_mipi_device *tegra_mipi_request(struct device *device)
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dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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if (!dev) {
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of_node_put(args.np);
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err = -ENOMEM;
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goto out;
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}
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dev->pdev = of_find_device_by_node(args.np);
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if (!dev->pdev) {
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of_node_put(args.np);
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err = -ENODEV;
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goto free;
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}
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of_node_put(args.np);
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dev->mipi = platform_get_drvdata(dev->pdev);
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if (!dev->mipi) {
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err = -EPROBE_DEFER;
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goto pdev_put;
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goto put;
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}
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of_node_put(args.np);
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dev->pads = args.args[0];
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dev->device = device;
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return dev;
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pdev_put:
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put:
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platform_device_put(dev->pdev);
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free:
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kfree(dev);
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out:
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of_node_put(args.np);
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return ERR_PTR(err);
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}
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EXPORT_SYMBOL(tegra_mipi_request);
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@ -177,6 +187,7 @@ static int tegra_mipi_wait(struct tegra_mipi *mipi)
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int tegra_mipi_calibrate(struct tegra_mipi_device *device)
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{
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const struct tegra_mipi_soc *soc = device->mipi->soc;
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unsigned int i;
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u32 value;
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int err;
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@ -196,16 +207,23 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device)
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value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
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tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
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for (i = 0; i < ARRAY_SIZE(modules); i++) {
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if (device->pads & BIT(i))
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value = MIPI_CAL_CONFIG_SELECT |
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MIPI_CAL_CONFIG_HSPDOS(0) |
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MIPI_CAL_CONFIG_HSPUOS(4) |
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MIPI_CAL_CONFIG_TERMOS(5);
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else
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value = 0;
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for (i = 0; i < soc->num_pads; i++) {
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u32 clk = 0, data = 0;
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tegra_mipi_writel(device->mipi, value, modules[i].reg);
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if (device->pads & BIT(i)) {
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data = MIPI_CAL_CONFIG_SELECT |
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MIPI_CAL_CONFIG_HSPDOS(0) |
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MIPI_CAL_CONFIG_HSPUOS(4) |
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MIPI_CAL_CONFIG_TERMOS(5);
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clk = MIPI_CAL_CONFIG_SELECT |
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MIPI_CAL_CONFIG_HSCLKPDOSD(0) |
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MIPI_CAL_CONFIG_HSCLKPUOSD(4);
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}
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tegra_mipi_writel(device->mipi, data, soc->pads[i].data);
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if (soc->has_clk_lane)
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tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk);
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}
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value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
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@ -221,16 +239,63 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device)
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}
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EXPORT_SYMBOL(tegra_mipi_calibrate);
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static const struct tegra_mipi_pad tegra114_mipi_pads[] = {
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{ .data = MIPI_CAL_CONFIG_CSIA },
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{ .data = MIPI_CAL_CONFIG_CSIB },
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{ .data = MIPI_CAL_CONFIG_CSIC },
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{ .data = MIPI_CAL_CONFIG_CSID },
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{ .data = MIPI_CAL_CONFIG_CSIE },
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{ .data = MIPI_CAL_CONFIG_DSIA },
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{ .data = MIPI_CAL_CONFIG_DSIB },
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{ .data = MIPI_CAL_CONFIG_DSIC },
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{ .data = MIPI_CAL_CONFIG_DSID },
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};
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static const struct tegra_mipi_soc tegra114_mipi_soc = {
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.has_clk_lane = false,
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.pads = tegra114_mipi_pads,
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.num_pads = ARRAY_SIZE(tegra114_mipi_pads),
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};
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static const struct tegra_mipi_pad tegra124_mipi_pads[] = {
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{ .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
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{ .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
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{ .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
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{ .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
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{ .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK },
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{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIAB_CLK },
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{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIAB_CLK },
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};
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static const struct tegra_mipi_soc tegra124_mipi_soc = {
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.has_clk_lane = true,
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.pads = tegra124_mipi_pads,
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.num_pads = ARRAY_SIZE(tegra124_mipi_pads),
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};
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static struct of_device_id tegra_mipi_of_match[] = {
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{ .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc },
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{ .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc },
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{ },
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};
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static int tegra_mipi_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct tegra_mipi *mipi;
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struct resource *res;
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int err;
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match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node);
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if (!match)
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return -ENODEV;
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mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
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if (!mipi)
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return -ENOMEM;
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mipi->soc = match->data;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mipi->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mipi->regs))
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@ -262,11 +327,6 @@ static int tegra_mipi_remove(struct platform_device *pdev)
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return 0;
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}
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static struct of_device_id tegra_mipi_of_match[] = {
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{ .compatible = "nvidia,tegra114-mipi", },
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{ },
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};
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struct platform_driver tegra_mipi_driver = {
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.driver = {
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.name = "tegra-mipi",
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