mlxsw: reg: Add Router Adjacency Table register
The RATR register is used to configure the Router Adjacency (next-hop) Table. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yotam Gigi
David S. Miller
parent
b090ef0686
commit
089f981683
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@ -3455,6 +3455,137 @@ static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
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mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
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}
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/* RATR - Router Adjacency Table Register
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* --------------------------------------
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* The RATR register is used to configure the Router Adjacency (next-hop)
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* Table.
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*/
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#define MLXSW_REG_RATR_ID 0x8008
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#define MLXSW_REG_RATR_LEN 0x2C
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static const struct mlxsw_reg_info mlxsw_reg_ratr = {
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.id = MLXSW_REG_RATR_ID,
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.len = MLXSW_REG_RATR_LEN,
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};
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enum mlxsw_reg_ratr_op {
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/* Read */
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MLXSW_REG_RATR_OP_QUERY_READ = 0,
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/* Read and clear activity */
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MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
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/* Write Adjacency entry */
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MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
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/* Write Adjacency entry only if the activity is cleared.
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* The write may not succeed if the activity is set. There is not
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* direct feedback if the write has succeeded or not, however
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* the get will reveal the actual entry (SW can compare the get
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* response to the set command).
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*/
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MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
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};
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/* reg_ratr_op
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* Note that Write operation may also be used for updating
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* counter_set_type and counter_index. In this case all other
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* fields must not be updated.
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* Access: OP
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*/
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MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
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/* reg_ratr_v
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* Valid bit. Indicates if the adjacency entry is valid.
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* Note: the device may need some time before reusing an invalidated
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* entry. During this time the entry can not be reused. It is
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* recommended to use another entry before reusing an invalidated
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* entry (e.g. software can put it at the end of the list for
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* reusing). Trying to access an invalidated entry not yet cleared
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* by the device results with failure indicating "Try Again" status.
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* When valid is '0' then egress_router_interface,trap_action,
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* adjacency_parameters and counters are reserved
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
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/* reg_ratr_a
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* Activity. Set for new entries. Set if a packet lookup has hit on
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* the specific entry. To clear the a bit, use "clear activity".
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* Access: RO
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*/
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MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
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/* reg_ratr_adjacency_index_low
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* Bits 15:0 of index into the adjacency table.
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* For SwitchX and SwitchX-2, the adjacency table is linear and
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* used for adjacency entries only.
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* For Spectrum, the index is to the KVD linear.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
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/* reg_ratr_egress_router_interface
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* Range is 0 .. cap_max_router_interfaces - 1
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
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enum mlxsw_reg_ratr_trap_action {
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MLXSW_REG_RATR_TRAP_ACTION_NOP,
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MLXSW_REG_RATR_TRAP_ACTION_TRAP,
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MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
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MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
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MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
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};
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/* reg_ratr_trap_action
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* see mlxsw_reg_ratr_trap_action
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
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enum mlxsw_reg_ratr_trap_id {
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MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0 = 0,
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MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1 = 1,
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};
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/* reg_ratr_adjacency_index_high
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* Bits 23:16 of the adjacency_index.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
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/* reg_ratr_trap_id
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* Trap ID to be reported to CPU.
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* Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
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* For trap_action of NOP, MIRROR and DISCARD_ERROR
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* Access: RW
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*/
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MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
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/* reg_ratr_eth_destination_mac
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* MAC address of the destination next-hop.
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* Access: RW
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*/
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MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
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static inline void
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mlxsw_reg_ratr_pack(char *payload,
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enum mlxsw_reg_ratr_op op, bool valid,
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u32 adjacency_index, u16 egress_rif)
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{
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MLXSW_REG_ZERO(ratr, payload);
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mlxsw_reg_ratr_op_set(payload, op);
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mlxsw_reg_ratr_v_set(payload, valid);
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mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
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mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
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mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
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}
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static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
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const char *dest_mac)
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{
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mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
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}
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/* RALTA - Router Algorithmic LPM Tree Allocation Register
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* -------------------------------------------------------
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* RALTA is used to allocate the LPM trees of the SHSPM method.
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@ -4910,6 +5041,8 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
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return "RGCR";
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case MLXSW_REG_RITR_ID:
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return "RITR";
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case MLXSW_REG_RATR_ID:
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return "RATR";
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case MLXSW_REG_RALTA_ID:
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return "RALTA";
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case MLXSW_REG_RALST_ID:
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