Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
- Page flipping fixes, with support for syncing them to vblank (finally...). - Misc other general fixes * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau: do not map evicted vram buffers in nouveau_bo_vma_add drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800 drm/nouveau/pwr: fix missing mutex unlock in a failure path drm/nv40/therm: fix slowing down fan when pstate undefined drm/nv11-: synchronise flips to vblank, unless async flip requested drm/nvc0-: remove nasty fifo swmthd hack for flip completion method drm/nv10-: we no longer need to create nvsw object on user channels drm/nouveau: always queue flips relative to kernel channel activity drm/nouveau: there is no need to reserve/fence the new fb when flipping drm/nouveau: when bailing out of a pushbuf ioctl, do not remove previous fence drm/nouveau: allow nouveau_fence_ref() to be a noop drm/nvc8/mc: msi rearm is via the nvc0 method
This commit is contained in:
Dave Airlie
commit
0846c728e2
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|
@ -256,7 +256,7 @@ nvc0_identify(struct nouveau_device *device)
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|||
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
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@ -494,13 +494,6 @@ nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit)
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u32 mthd = (addr & 0x00003ffc);
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u32 show = stat;
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if (stat & 0x00200000) {
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if (mthd == 0x0054) {
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if (!nvc0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
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show &= ~0x00200000;
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}
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}
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if (stat & 0x00800000) {
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if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
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show &= ~0x00800000;
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@ -481,13 +481,6 @@ nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit)
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u32 mthd = (addr & 0x00003ffc);
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u32 show = stat;
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if (stat & 0x00200000) {
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if (mthd == 0x0054) {
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if (!nve0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
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show &= ~0x00200000;
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}
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}
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if (stat & 0x00800000) {
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if (!nve0_fifo_swmthd(priv, chid, mthd, data))
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show &= ~0x00800000;
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@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
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} while (!tpcnr[gpc]);
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tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
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tpc_set |= 1 << ((gpc * 8) + tpc);
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tpc_set |= 1ULL << ((gpc * 8) + tpc);
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}
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nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
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@ -32,6 +32,11 @@ nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2],
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struct nouveau_subdev *subdev = nv_subdev(ppwr);
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u32 addr;
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/* wait for a free slot in the fifo */
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addr = nv_rd32(ppwr, 0x10a4a0);
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if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8))
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return -EBUSY;
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/* we currently only support a single process at a time waiting
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* on a synchronous reply, take the PPWR mutex and tell the
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* receive handler what we're waiting for
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@ -42,11 +47,6 @@ nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2],
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ppwr->recv.process = process;
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}
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/* wait for a free slot in the fifo */
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addr = nv_rd32(ppwr, 0x10a4a0);
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if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8))
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return -EBUSY;
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/* acquire data segment access */
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do {
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nv_wr32(ppwr, 0x10a580, 0x00000001);
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@ -117,7 +117,8 @@ nouveau_therm_update(struct nouveau_therm *therm, int mode)
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priv->fan->bios.linear_max_temp) {
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duty = nouveau_therm_update_linear(therm);
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} else {
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duty = priv->cstate;
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if (priv->cstate)
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duty = priv->cstate;
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poll = false;
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}
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immd = false;
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@ -298,7 +298,7 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
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else
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init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
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if (device->card_type < NV_C0) {
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if (device->card_type < NV_10) {
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init->subchan[0].handle = 0x00000000;
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init->subchan[0].grclass = 0x0000;
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init->subchan[1].handle = NvSw;
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@ -98,12 +98,7 @@ nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
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if (tile) {
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spin_lock(&drm->tile.lock);
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if (fence) {
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/* Mark it as pending. */
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tile->fence = fence;
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nouveau_fence_ref(fence);
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}
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tile->fence = nouveau_fence_ref(fence);
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tile->used = false;
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spin_unlock(&drm->tile.lock);
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}
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@ -1462,14 +1457,12 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
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void
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nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
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{
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struct nouveau_fence *new_fence = nouveau_fence_ref(fence);
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struct nouveau_fence *old_fence = NULL;
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if (likely(fence))
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nouveau_fence_ref(fence);
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spin_lock(&nvbo->bo.bdev->fence_lock);
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old_fence = nvbo->bo.sync_obj;
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nvbo->bo.sync_obj = fence;
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nvbo->bo.sync_obj = new_fence;
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spin_unlock(&nvbo->bo.bdev->fence_lock);
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nouveau_fence_unref(&old_fence);
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@ -1552,7 +1545,8 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
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if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
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nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
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else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
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else if (nvbo->bo.mem.mem_type == TTM_PL_TT &&
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nvbo->page_shift == vma->vm->vmm->spg_shift) {
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if (node->sg)
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nouveau_vm_map_sg_table(vma, 0, size, node);
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else
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@ -346,22 +346,17 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
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for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
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OUT_RING(chan, 0x00000000);
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/* allocate software object class (used for fences on <= nv05, and
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* to signal flip completion), bind it to a subchannel.
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*/
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if ((device->card_type < NV_E0) || gart /* nve0: want_nvsw */) {
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/* allocate software object class (used for fences on <= nv05) */
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if (device->card_type < NV_10) {
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ret = nouveau_object_new(nv_object(client), chan->handle,
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NvSw, nouveau_abi16_swclass(chan->drm),
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NULL, 0, &object);
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NvSw, 0x006e, NULL, 0, &object);
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if (ret)
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return ret;
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swch = (void *)object->parent;
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swch->flip = nouveau_flip_complete;
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swch->flip_data = chan;
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}
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if (device->card_type < NV_C0) {
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ret = RING_SPACE(chan, 2);
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if (ret)
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return ret;
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@ -26,7 +26,6 @@
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/ttm/ttm_execbuf_util.h>
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#include "nouveau_fbcon.h"
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#include "dispnv04/hw.h"
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@ -399,6 +398,11 @@ nouveau_display_create(struct drm_device *dev)
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dev->mode_config.preferred_depth = 24;
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dev->mode_config.prefer_shadow = 1;
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if (nv_device(drm->device)->chipset < 0x11)
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dev->mode_config.async_page_flip = false;
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else
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dev->mode_config.async_page_flip = true;
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drm_kms_helper_poll_init(dev);
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drm_kms_helper_poll_disable(dev);
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@ -555,19 +559,15 @@ nouveau_page_flip_emit(struct nouveau_channel *chan,
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goto fail;
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/* Emit the pageflip */
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ret = RING_SPACE(chan, 3);
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ret = RING_SPACE(chan, 2);
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if (ret)
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goto fail;
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if (nv_device(drm->device)->card_type < NV_C0) {
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if (nv_device(drm->device)->card_type < NV_C0)
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BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1);
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OUT_RING (chan, 0x00000000);
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OUT_RING (chan, 0x00000000);
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} else {
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BEGIN_NVC0(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
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OUT_RING (chan, 0);
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BEGIN_IMC0(chan, 0, NVSW_SUBCHAN_PAGE_FLIP, 0x0000);
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}
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else
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BEGIN_NVC0(chan, FermiSw, NV_SW_PAGE_FLIP, 1);
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OUT_RING (chan, 0x00000000);
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FIRE_RING (chan);
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ret = nouveau_fence_new(chan, false, pfence);
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@ -584,22 +584,16 @@ fail:
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int
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nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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struct drm_pending_vblank_event *event,
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uint32_t page_flip_flags)
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struct drm_pending_vblank_event *event, u32 flags)
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{
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const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1;
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struct drm_device *dev = crtc->dev;
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->fb)->nvbo;
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struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo;
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struct nouveau_page_flip_state *s;
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struct nouveau_channel *chan = NULL;
|
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struct nouveau_channel *chan = drm->channel;
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struct nouveau_fence *fence;
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struct ttm_validate_buffer resv[2] = {
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{ .bo = &old_bo->bo },
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{ .bo = &new_bo->bo },
|
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};
|
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struct ww_acquire_ctx ticket;
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LIST_HEAD(res);
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||||
int ret;
|
||||
|
||||
if (!drm->channel)
|
||||
|
|
@ -609,26 +603,22 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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|||
if (!s)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Choose the channel the flip will be handled in */
|
||||
spin_lock(&old_bo->bo.bdev->fence_lock);
|
||||
fence = new_bo->bo.sync_obj;
|
||||
if (fence)
|
||||
chan = fence->channel;
|
||||
if (!chan)
|
||||
chan = drm->channel;
|
||||
spin_unlock(&old_bo->bo.bdev->fence_lock);
|
||||
/* synchronise rendering channel with the kernel's channel */
|
||||
spin_lock(&new_bo->bo.bdev->fence_lock);
|
||||
fence = nouveau_fence_ref(new_bo->bo.sync_obj);
|
||||
spin_unlock(&new_bo->bo.bdev->fence_lock);
|
||||
ret = nouveau_fence_sync(fence, chan);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (new_bo != old_bo) {
|
||||
ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM);
|
||||
if (ret)
|
||||
goto fail_free;
|
||||
|
||||
list_add(&resv[1].head, &res);
|
||||
}
|
||||
list_add(&resv[0].head, &res);
|
||||
|
||||
mutex_lock(&chan->cli->mutex);
|
||||
ret = ttm_eu_reserve_buffers(&ticket, &res);
|
||||
ret = ttm_bo_reserve(&old_bo->bo, true, false, false, NULL);
|
||||
if (ret)
|
||||
goto fail_unpin;
|
||||
|
||||
|
|
@ -640,12 +630,29 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
|
|||
|
||||
/* Emit a page flip */
|
||||
if (nv_device(drm->device)->card_type >= NV_50) {
|
||||
ret = nv50_display_flip_next(crtc, fb, chan, 0);
|
||||
ret = nv50_display_flip_next(crtc, fb, chan, swap_interval);
|
||||
if (ret)
|
||||
goto fail_unreserve;
|
||||
} else {
|
||||
struct nv04_display *dispnv04 = nv04_display(dev);
|
||||
nouveau_bo_ref(new_bo, &dispnv04->image[nouveau_crtc(crtc)->index]);
|
||||
int head = nouveau_crtc(crtc)->index;
|
||||
|
||||
if (swap_interval) {
|
||||
ret = RING_SPACE(chan, 8);
|
||||
if (ret)
|
||||
goto fail_unreserve;
|
||||
|
||||
BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1);
|
||||
OUT_RING (chan, 0);
|
||||
BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1);
|
||||
OUT_RING (chan, head);
|
||||
BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1);
|
||||
OUT_RING (chan, 0);
|
||||
BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1);
|
||||
OUT_RING (chan, 0);
|
||||
}
|
||||
|
||||
nouveau_bo_ref(new_bo, &dispnv04->image[head]);
|
||||
}
|
||||
|
||||
ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence);
|
||||
|
|
@ -656,14 +663,15 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
|
|||
/* Update the crtc struct and cleanup */
|
||||
crtc->fb = fb;
|
||||
|
||||
ttm_eu_fence_buffer_objects(&ticket, &res, fence);
|
||||
nouveau_bo_fence(old_bo, fence);
|
||||
ttm_bo_unreserve(&old_bo->bo);
|
||||
if (old_bo != new_bo)
|
||||
nouveau_bo_unpin(old_bo);
|
||||
nouveau_fence_unref(&fence);
|
||||
return 0;
|
||||
|
||||
fail_unreserve:
|
||||
ttm_eu_backoff_reservation(&ticket, &res);
|
||||
ttm_bo_unreserve(&old_bo->bo);
|
||||
fail_unpin:
|
||||
mutex_unlock(&chan->cli->mutex);
|
||||
if (old_bo != new_bo)
|
||||
|
|
|
|||
|
|
@ -51,9 +51,11 @@ enum {
|
|||
NvSubCtxSurf2D = 0,
|
||||
NvSubSw = 1,
|
||||
NvSubImageBlit = 2,
|
||||
NvSub2D = 3,
|
||||
NvSubGdiRect = 3,
|
||||
NvSubCopy = 4,
|
||||
|
||||
NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */
|
||||
NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */
|
||||
FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */
|
||||
};
|
||||
|
||||
/* Object handles. */
|
||||
|
|
@ -194,7 +196,6 @@ WIND_RING(struct nouveau_channel *chan)
|
|||
#define NV84_SUBCHAN_UEVENT 0x00000020
|
||||
#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
|
||||
#define NV10_SUBCHAN_REF_CNT 0x00000050
|
||||
#define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
|
||||
#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
|
||||
#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
|
||||
#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@
|
|||
#include <engine/device.h>
|
||||
#include <engine/disp.h>
|
||||
#include <engine/fifo.h>
|
||||
#include <engine/software.h>
|
||||
|
||||
#include <subdev/vm.h>
|
||||
|
||||
|
|
@ -191,6 +192,32 @@ nouveau_accel_init(struct nouveau_drm *drm)
|
|||
return;
|
||||
}
|
||||
|
||||
ret = nouveau_object_new(nv_object(drm), NVDRM_CHAN, NVDRM_NVSW,
|
||||
nouveau_abi16_swclass(drm), NULL, 0, &object);
|
||||
if (ret == 0) {
|
||||
struct nouveau_software_chan *swch = (void *)object->parent;
|
||||
ret = RING_SPACE(drm->channel, 2);
|
||||
if (ret == 0) {
|
||||
if (device->card_type < NV_C0) {
|
||||
BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
|
||||
OUT_RING (drm->channel, NVDRM_NVSW);
|
||||
} else
|
||||
if (device->card_type < NV_E0) {
|
||||
BEGIN_NVC0(drm->channel, FermiSw, 0, 1);
|
||||
OUT_RING (drm->channel, 0x001f0000);
|
||||
}
|
||||
}
|
||||
swch = (void *)object->parent;
|
||||
swch->flip = nouveau_flip_complete;
|
||||
swch->flip_data = drm->channel;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
NV_ERROR(drm, "failed to allocate software object, %d\n", ret);
|
||||
nouveau_accel_fini(drm);
|
||||
return;
|
||||
}
|
||||
|
||||
if (device->card_type < NV_C0) {
|
||||
ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0,
|
||||
&drm->notify);
|
||||
|
|
|
|||
|
|
@ -56,6 +56,7 @@ enum nouveau_drm_handle {
|
|||
NVDRM_CONTROL = 0xdddddddc,
|
||||
NVDRM_PUSH = 0xbbbb0000, /* |= client chid */
|
||||
NVDRM_CHAN = 0xcccc0000, /* |= client chid */
|
||||
NVDRM_NVSW = 0x55550000,
|
||||
};
|
||||
|
||||
struct nouveau_cli {
|
||||
|
|
|
|||
|
|
@ -306,7 +306,8 @@ nouveau_fence_unref(struct nouveau_fence **pfence)
|
|||
struct nouveau_fence *
|
||||
nouveau_fence_ref(struct nouveau_fence *fence)
|
||||
{
|
||||
kref_get(&fence->kref);
|
||||
if (fence)
|
||||
kref_get(&fence->kref);
|
||||
return fence;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -106,8 +106,7 @@ nouveau_gem_object_unmap(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
|
|||
|
||||
if (mapped) {
|
||||
spin_lock(&nvbo->bo.bdev->fence_lock);
|
||||
if (nvbo->bo.sync_obj)
|
||||
fence = nouveau_fence_ref(nvbo->bo.sync_obj);
|
||||
fence = nouveau_fence_ref(nvbo->bo.sync_obj);
|
||||
spin_unlock(&nvbo->bo.bdev->fence_lock);
|
||||
}
|
||||
|
||||
|
|
@ -309,7 +308,8 @@ validate_fini_list(struct list_head *list, struct nouveau_fence *fence,
|
|||
list_for_each_safe(entry, tmp, list) {
|
||||
nvbo = list_entry(entry, struct nouveau_bo, entry);
|
||||
|
||||
nouveau_bo_fence(nvbo, fence);
|
||||
if (likely(fence))
|
||||
nouveau_bo_fence(nvbo, fence);
|
||||
|
||||
if (unlikely(nvbo->validate_mapped)) {
|
||||
ttm_bo_kunmap(&nvbo->kmap);
|
||||
|
|
@ -438,8 +438,7 @@ validate_sync(struct nouveau_channel *chan, struct nouveau_bo *nvbo)
|
|||
int ret = 0;
|
||||
|
||||
spin_lock(&nvbo->bo.bdev->fence_lock);
|
||||
if (nvbo->bo.sync_obj)
|
||||
fence = nouveau_fence_ref(nvbo->bo.sync_obj);
|
||||
fence = nouveau_fence_ref(nvbo->bo.sync_obj);
|
||||
spin_unlock(&nvbo->bo.bdev->fence_lock);
|
||||
|
||||
if (fence) {
|
||||
|
|
|
|||
|
|
@ -255,6 +255,12 @@ nv04_fbcon_accel_init(struct fb_info *info)
|
|||
OUT_RING(chan, NvCtxSurf2D);
|
||||
BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);
|
||||
OUT_RING(chan, 3);
|
||||
if (device->chipset >= 0x11 /*XXX: oclass == 0x009f*/) {
|
||||
BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3);
|
||||
OUT_RING(chan, 0);
|
||||
OUT_RING(chan, 1);
|
||||
OUT_RING(chan, 2);
|
||||
}
|
||||
|
||||
BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);
|
||||
OUT_RING(chan, NvGdiRect);
|
||||
|
|
|
|||
Loading…
Reference in New Issue