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KVM: PPC: E500: Ignore L1CSR1_ICFI,ICLFR 

The L1 instruction cache control register contains bits that indicate
that we're still handling a request. Mask those out when we set the SPR
so that a read doesn't assume we're still doing something.

Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf 2014-04-17 12:53:13 +02:00
parent 1f85411255
commit 07fec1c2e7
1 changed files with 1 additions and 0 deletions
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arch/powerpc/kvm/e500_emulate.c
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@ -222,6 +222,7 @@ int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_va
break; break;
case SPRN_L1CSR1: case SPRN_L1CSR1:
vcpu_e500->l1csr1 = spr_val; vcpu_e500->l1csr1 = spr_val;
vcpu_e500->l1csr1 &= ~(L1CSR1_ICFI | L1CSR1_ICLFR);
break; break;
case SPRN_HID0: case SPRN_HID0:
vcpu_e500->hid0 = spr_val; vcpu_e500->hid0 = spr_val;