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OMAP4 ES2: HSMMC soft reset change 

The omap4 es2 hsmmc has a updated soft reset logic.After the
reset is issued monitor a 0->1 transition first. The reset of
CMD or DATA lines is complete only after a 0->1->0 transition
of SRC or SRD bits.

Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Tested-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Madhusudhan Chikkature 2010-10-01 16:35:25 -07:00 committed by Tony Lindgren
parent e13bb34bd9
commit 07ad64b60c
3 changed files with 15 additions and 0 deletions
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3
arch/arm/mach-omap2/hsmmc.c
View File

@ -303,6 +303,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
else else
mmc->slots[0].features |= HSMMC_HAS_PBIAS; mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
switch (c->mmc) { switch (c->mmc) {
case 1: case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {

1
arch/arm/plat-omap/include/plat/mmc.h
View File

@ -103,6 +103,7 @@ struct omap_mmc_platform_data {
/* we can put the features above into this variable */ /* we can put the features above into this variable */
#define HSMMC_HAS_PBIAS (1 << 0) #define HSMMC_HAS_PBIAS (1 << 0)
#define HSMMC_HAS_UPDATED_RESET (1 << 1)
unsigned features; unsigned features;
int switch_pin; /* gpio (card detect) */ int switch_pin; /* gpio (card detect) */

11
drivers/mmc/host/omap_hsmmc.c
View File

@ -982,6 +982,17 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
OMAP_HSMMC_WRITE(host->base, SYSCTL, OMAP_HSMMC_WRITE(host->base, SYSCTL,
OMAP_HSMMC_READ(host->base, SYSCTL) | bit); OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
/*
* OMAP4 ES2 and greater has an updated reset logic.
* Monitor a 0->1 transition first
*/
if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit))
&& (i++ < limit))
cpu_relax();
}
i = 0;
while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
(i++ < limit)) (i++ < limit))
cpu_relax(); cpu_relax();